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2022-03-22compiler.h: replace QEMU_WARN_UNUSED_RESULT with G_GNUC_WARN_UNUSED_RESULTMarc-André Lureau
One less qemu-specific macro. It also helps to make some headers/units only depend on glib, and thus moved in standalone projects eventually. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-22Replace GCC_FMT_ATTR with G_GNUC_PRINTFMarc-André Lureau
One less qemu-specific macro. It also helps to make some headers/units only depend on glib, and thus moved in standalone projects eventually. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard W.M. Jones <rjones@redhat.com>
2022-03-22Drop qemu_foo() socket API wrapperMarc-André Lureau
The socket API wrappers were initially introduced in commit 00aa0040 ("Wrap recv to avoid warnings"), but made redundant with commit a2d96af4 ("osdep: add wrappers for socket functions") which fixes the win32 declarations and thus removed the earlier warnings. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-21Use g_new() & friends where that makes obvious senseMarkus Armbruster
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer, for two reasons. One, it catches multiplication overflowing size_t. Two, it returns T * rather than void *, which lets the compiler catch more type errors. This commit only touches allocations with size arguments of the form sizeof(T). Patch created mechanically with: $ spatch --in-place --sp-file scripts/coccinelle/use-g_new-etc.cocci \ --macro-file scripts/cocci-macro-file.h FILES... Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20220315144156.1595462-4-armbru@redhat.com> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
2022-03-18util/osdep: Avoid madvise proto on modern SolarisAndrew Deason
On older Solaris releases (before Solaris 11), we didn't get a prototype for madvise, and so util/osdep.c provides its own prototype. Some time between the public Solaris 11.4 release and Solaris 11.4.42 CBE, we started getting an madvise prototype that looks like this: extern int madvise(void *, size_t, int); which conflicts with the prototype in util/osdeps.c. Instead of always declaring this prototype, check if we're missing the madvise() prototype, and only declare it ourselves if the prototype is missing. Move the prototype to include/qemu/osdep.h, the normal place to handle platform-specific header quirks. The 'missing_madvise_proto' meson check contains an obviously wrong prototype for madvise. So if that code compiles and links, we must be missing the actual prototype for madvise. Signed-off-by: Andrew Deason <adeason@sinenomine.net> Message-id: 20220316035227.3702-2-adeason@sinenomine.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-18hw/arm/xlnx-zynqmp: Connect the ZynqMP APU ControlEdgar E. Iglesias
Connect the ZynqMP APU Control device. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-7-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-18hw/misc: Add a model of the Xilinx ZynqMP APU ControlEdgar E. Iglesias
Add a model of the Xilinx ZynqMP APU Control. Reviewed-by: Luc Michel <luc@lmichel.fr> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-18hw/arm/xlnx-zynqmp: Connect the ZynqMP CRFEdgar E. Iglesias
Connect the ZynqMP CRF - Clock Reset FPD device. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-18hw/misc: Add a model of the Xilinx ZynqMP CRFEdgar E. Iglesias
Add a model of the Xilinx ZynqMP CRF. At the moment this is mostly a stub model. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-18hw/arm/xlnx-zynqmp: Add an unimplemented SERDES areaEdgar E. Iglesias
Add an unimplemented SERDES (Serializer/Deserializer) area. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-16softmmu: List CPU types againPhilippe Mathieu-Daudé
Commit e0220bb5b2 made cpus.c target-agnostic but didn't notice the cpu_list() function is only defined in target-specific code in "cpu.h". Move list_cpus() declaration to "exec/cpu-common.h" because this function is not softmmu-specific and can also be used by user-mode, along with moving its implementation to cpu.c, which is compiled per target. Fixes: e0220bb5b2 ("softmmu: Build target-agnostic objects once") Reported-by: Max Filippov <jcmvbkbc@gmail.com> Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220314140108.26222-1-philippe.mathieu.daude@gmail.com> Tested-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-03-15Merge tag 'darwin-20220315' of https://github.com/philmd/qemu into stagingPeter Maydell
Darwin-based host patches - Remove various build warnings - Fix building with modules on macOS - Fix mouse/keyboard GUI interactions # gpg: Signature made Tue 15 Mar 2022 12:52:19 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'darwin-20220315' of https://github.com/philmd/qemu: (21 commits) MAINTAINERS: Volunteer to maintain Darwin-based hosts support ui/cocoa: add option to swap Option and Command ui/cocoa: capture all keys and combos when mouse is grabbed ui/cocoa: release mouse when user switches away from QEMU window ui/cocoa: add option to disable left-command forwarding to guest ui/cocoa: Constify qkeycode translation arrays configure: Pass filtered QEMU_OBJCFLAGS to meson meson: Log QEMU_CXXFLAGS content in summary meson: Resolve the entitlement.sh script once for good osdep: Avoid using Clang-specific __builtin_available() audio: Rename coreaudio extension to use Objective-C compiler coreaudio: Always return 0 in handle_voice_change audio: Log context for audio bug audio/dbus: Fix building with modules on macOS audio/coreaudio: Remove a deprecation warning on macOS 12 block/file-posix: Remove a deprecation warning on macOS 12 hvf: Remove deprecated hv_vcpu_flush() calls hvf: Make hvf_get_segments() / hvf_put_segments() local hvf: Use standard CR0 and CR4 register definitions tests/fp/berkeley-testfloat-3: Ignore ignored #pragma directives ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-15Merge tag 'dbus-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingPeter Maydell
GL & D-Bus display related fixes Hi, Here are pending fixes related to D-Bus and GL, most of them reported thanks to Akihiko Odaki. # gpg: Signature made Tue 15 Mar 2022 09:36:45 GMT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * tag 'dbus-pull-request' of gitlab.com:marcandre.lureau/qemu: ui/console: call gfx_switch() even if the current scanout is GL ui/dbus: do not send 2d scanout until gfx_update ui/dbus: fix texture sharing ui/console: optionally update after gfx switch ui/console: add a dpy_gfx_switch callback helper ui/shader: free associated programs ui/shader: fix potential leak of shader on error ui/console: move console compatibility check to dcl_display_console() ui/dbus: associate the DBusDisplayConsole listener with the given console ui/console: egl-headless is compatible with non-gl listeners ui/console: move dcl compatiblity check to a callback ui/console: move check for compatible GL context Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-15Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
* whpx fixes in preparation for GDB support (Ivan) * VSS header fixes (Marc-André) * 5-level EPT support (Vitaly) * AMX support (Jing Liu & Yang Zhong) * Bundle changes to MSI routes (Longpeng) * More precise emulation of #SS (Gareth) * Disable ASAN testing # gpg: Signature made Tue 15 Mar 2022 10:51:00 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (22 commits) gitlab-ci: do not run tests with address sanitizer KVM: SVM: always set MSR_AMD64_TSC_RATIO to default value i386: Add Icelake-Server-v6 CPU model with 5-level EPT support x86: Support XFD and AMX xsave data migration x86: add support for KVM_CAP_XSAVE2 and AMX state migration x86: Add AMX CPUIDs enumeration x86: Add XFD faulting bit for state components x86: Grant AMX permission for guest x86: Add AMX XTILECFG and XTILEDATA components x86: Fix the 64-byte boundary enumeration for extended state linux-headers: include missing changes from 5.17 target/i386: Throw a #SS when loading a non-canonical IST target/i386: only include bits in pg_mode if they are not ignored kvm/msi: do explicit commit when adding msi routes kvm-irqchip: introduce new API to support route change update meson-buildoptions.sh qga/vss: update informative message about MinGW qga/vss-win32: check old VSS SDK headers meson: fix generic location of vss headers vmxcap: Add 5-level EPT bit ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-15osdep: Avoid using Clang-specific __builtin_available()Philippe Mathieu-Daudé
Remove the Clang specific __builtin_available() to allow building with GCC, otherwise we get: include/qemu/osdep.h: In function 'qemu_thread_jit_write': include/qemu/osdep.h:787:9: warning: implicit declaration of function '__builtin_available'; did you mean '__builtin_scalbl'? [-Wimplicit-function-declaration] 787 | if (__builtin_available(macOS 11.0, *)) { | ^~~~~~~~~~~~~~~~~~~ | __builtin_scalbl include/qemu/osdep.h:787:9: warning: nested extern declaration of '__builtin_available' [-Wnested-externs] include/qemu/osdep.h:787:29: error: 'macOS' undeclared (first use in this function) 787 | if (__builtin_available(macOS 11.0, *)) { | ^~~~~ include/qemu/osdep.h:787:29: note: each undeclared identifier is reported only once for each function it appears in include/qemu/osdep.h:787:34: error: expected ')' before numeric constant 787 | if (__builtin_available(macOS 11.0, *)) { | ~ ^~~~~ | ) Beside, on macOS Catalina we get 2254 times: include/qemu/osdep.h:780:5: warning: 'pthread_jit_write_protect_np' is only available on macOS 11.0 or newer [-Wunguarded-availability-new] pthread_jit_write_protect_np(true); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fix by using a stricker toolchain version low range, replacing MAC_OS_X_VERSION_MAX_ALLOWED by MAC_OS_X_VERSION_MIN_REQUIRED. Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-15Merge tag 'pull-ppc-20220314' of https://github.com/legoater/qemu into stagingPeter Maydell
ppc-7.0 queue : * Removal of user-created PHB devices * Avocado fixes for --disable-tcg * Instruction and Radix MMU fixes # gpg: Signature made Mon 14 Mar 2022 15:16:07 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20220314' of https://github.com/legoater/qemu: ppc/pnv: Remove user-created PHB{3,4,5} devices ppc/pnv: Always create the PHB5 PEC devices ppc/pnv: Introduce a pnv-phb5 device to match root port ppc/xive2: Make type Xive2EndSource not user creatable target/ppc: fix xxspltw for big endian hosts target/ppc: fix ISI fault cause for Radix MMU avocado/ppc_virtex_ml507.py: check TCG accel in test_ppc_virtex_ml507() avocado/ppc_prep_40p.py: check TCG accel in all tests avocado/ppc_mpc8544ds.py: check TCG accel in test_ppc_mpc8544ds() avocado/ppc_bamboo.py: check TCG accel in test_ppc_bamboo() avocado/ppc_74xx.py: check TCG accel for all tests avocado/ppc_405.py: check TCG accel in test_ppc_ref405ep() avocado/ppc_405.py: remove test_ppc_taihu() avocado/boot_linux_console.py: check TCG accel in test_ppc_mac99() avocado/boot_linux_console.py: check TCG accel in test_ppc_g3beige() avocado/replay_kernel.py: make tcg-icount check in run_vm() avocado/boot_linux_console.py: check tcg accel in test_ppc64_e500 avocado/boot_linux_console.py: check for tcg in test_ppc_powernv8/9 qtest/meson.build: check CONFIG_TCG for boot-serial-test in qtests_ppc qtest/meson.build: check CONFIG_TCG for prom-env-test in qtests_ppc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-15kvm/msi: do explicit commit when adding msi routesLongpeng(Mike)
We invoke the kvm_irqchip_commit_routes() for each addition to MSI route table, which is not efficient if we are adding lots of routes in some cases. This patch lets callers invoke the kvm_irqchip_commit_routes(), so the callers can decide how to optimize. [1] https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg00967.html Signed-off-by: Longpeng <longpeng2@huawei.com> Message-Id: <20220222141116.2091-3-longpeng2@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-03-15kvm-irqchip: introduce new API to support route changeLongpeng(Mike)
Paolo suggested adding the new API to support route changes [1]. We should invoke kvm_irqchip_begin_route_changes() before changing the routes, increasing the KVMRouteChange.changes if the routes are changed, and commit the changes at last. [1] https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg02898.html Signed-off-by: Longpeng <longpeng2@huawei.com> Message-Id: <20220222141116.2091-2-longpeng2@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-03-15ui/dbus: fix texture sharingMarc-André Lureau
The DBus listener naively create, update and destroy textures without taking into account other listeners. The texture were shared, but texture update was unnecessarily duplicated. Teach DisplayGLCtx to do optionally shared texture handling. This is only implemented for DBus display at this point, however the same infrastructure could potentially be used for other future combinations. Reported-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2022-03-15vdpa: Expose VHOST_F_LOG_ALL on SVQEugenio Pérez
SVQ is able to log the dirty bits by itself, so let's use it to not block migration. Also, ignore set and clear of VHOST_F_LOG_ALL on set_features if SVQ is enabled. Even if the device supports it, the reports would be nonsense because SVQ memory is in the qemu region. The log region is still allocated. Future changes might skip that, but this series is already long enough. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-03-15vdpa: Add custom IOTLB translations to SVQEugenio Pérez
Use translations added in VhostIOVATree in SVQ. Only introduce usage here, not allocation and deallocation. As with previous patches, we use the dead code paths of shadow_vqs_enabled to avoid commiting too many changes at once. These are impossible to take at the moment. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-03-15util: add iova_tree_find_iovaEugenio Pérez
This function does the reverse operation of iova_tree_find: To look for a mapping that match a translated address so we can do the reverse. This have linear complexity instead of logarithmic, but it supports overlapping HVA. Future developments could reduce it. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-03-15util: Add iova_tree_alloc_mapEugenio Pérez
This iova tree function allows it to look for a hole in allocated regions and return a totally new translation for a given translated address. It's usage is mainly to allow devices to access qemu address space, remapping guest's one into a new iova space where qemu can add chunks of addresses. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-03-15vhost: Add Shadow VirtQueue kick forwarding capabilitiesEugenio Pérez
At this mode no buffer forwarding will be performed in SVQ mode: Qemu will just forward the guest's kicks to the device. Host memory notifiers regions are left out for simplicity, and they will not be addressed in this series. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-03-14ppc/pnv: Remove user-created PHB{3,4,5} devicesCédric Le Goater
On a real system with POWER{8,9,10} processors, PHBs are sub-units of the processor, they can be deactivated by firmware but not plugged in or out like a PCI adapter on a slot. Nevertheless, having user-created PHBs in QEMU seemed to be a good idea for testing purposes : 1. having a limited set of PHBs speedups boot time. 2. it is useful to be able to mimic a partially broken topology you some time have to deal with during bring-up. PowerNV is also used for distro install tests and having libvirt support eases these tasks. libvirt prefers to run the machine with -nodefaults to be sure not to drag unexpected devices which would need to be defined in the domain file without being specified on the QEMU command line. For this reason : 3. -nodefaults should not include default PHBs User-created PHB{3,4,5} devices satisfied all these needs but reality proves to be a bit more complex, internally when modeling such devices, and externally when dealing with the user interface. Req 1. and 2. can be simply addressed differently with a machine option: "phb-mask=<uint>", which QEMU would use to enable/disable PHB device nodes when creating the device tree. For Req 3., we need to make sure we are taking the right approach. It seems that we should expose a new type of user-created PHB device, a generic virtualized one, that libvirt would use and not one depending on the processor revision. This needs more thinking. For now, remove user-created PHB{3,4,5} devices. All the cleanups we did are not lost and they will be useful for the next steps. Fixes: 5bc67b052b51 ("ppc/pnv: Introduce user creatable pnv-phb4 devices") Fixes: 1f6a88fffc75 ("ppc/pnv: Introduce support for user created PHB3 devices") Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220314130514.529931-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-14ppc/pnv: Introduce a pnv-phb5 device to match root portFrederic Barrat
We already have the pnv-phb3 and pnv-phb4 devices for POWER8 and POWER9 respectively. POWER10 uses version 5 of the PHB. It is very close to the PHB4 from POWER9, at least in our model and we could almost keep using the PHB4 model. However the matching root port pnv-phb5-root-port is specific to POWER10 so to avoid confusion as well as making it easy to introduce differences later, we create a pnv-phb5 class, which is mostly an alias for pnv-phb4 for now. With this patch, the command line for a user-created PHB on powernv10 becomes: -machine powernv10 -nodefaults -device pnv-phb5 -device pnv-phb5-root-port Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220310155101.294568-2-fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-14ui/console: move dcl compatiblity check to a callbackMarc-André Lureau
As expected from the "compatible_dcl" comment, a simple comparison of ops isn't enough. The following patch will fix a regression introduced by this limited check by extending the compatibility callback for egl-headless. For now, this patch simply replaces the the "compatible_dcl" ops pointer with a "dpy_gl_ctx_is_compatible_ctx" callback. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2022-03-10Merge remote-tracking branch ↵Peter Maydell
'remotes/mcayland/tags/q800-updates-for-7.0-20220309' into staging q800-updates-for-7.0 queue # gpg: Signature made Wed 09 Mar 2022 10:57:07 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/q800-updates-for-7.0-20220309: (22 commits) esp: recreate ESPState current_req after migration esp: include the current PDMA callback in the migration stream esp: convert ESPState pdma_cb from a function pointer to an integer esp: introduce esp_pdma_cb() function esp: introduce esp_set_pdma_cb() function macfb: set initial value of mode control registers in macfb_common_realize() macfb: add VMStateDescription fields for display type and VBL timer macfb: increase number of registers saved in MacfbState macfb: don't use special irq_state and irq_mask variables in MacfbState macfb: add VMStateDescription for MacfbNubusState and MacfbSysBusState macio/pmu.c: remove redundant code mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQs mac_via: make SCSI_DATA (DRQ) bit live rather than latched mos6522: record last_irq_levels in mos6522_set_irq() mos6522: add "info via" HMP command for debugging mos6522: add register names to register read/write trace events mos6522: use device_class_set_parent_reset() to propagate reset to parent mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClass mos6522: switch over to use qdev gpios for IRQs mac_via: use IFR bit flag constants for VIA2 IRQs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-09Merge remote-tracking branch 'remotes/philmd/tags/pmbus-20220308' into stagingPeter Maydell
I²C / SMBus / PMBus patches - Add some Renesas models - Add Titus Rwantare to MAINTAINERS # gpg: Signature made Tue 08 Mar 2022 18:11:46 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/pmbus-20220308: hw/sensor: add Renesas raa228000 device hw/sensor: add Renesas raa229004 PMBus device hw/sensor: add Intersil ISL69260 device model hw/i2c: Added linear mode translation for pmbus devices hw/i2c: pmbus: update MAINTAINERS hw/i2c: pmbus: refactor uint handling hw/i2c: pmbus: add PEC unsupported warning hw/i2c: pmbus: fix error returns and guard against out of range accesses hw/i2c: pmbus: add registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-09Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220308' ↵Peter Maydell
into staging aspeed queue: * Fix for a potential memory leak * Aspeed SMC cleanups on the definition of the number of flash devices * New bletchley-bmc machine, AST2600 based # gpg: Signature made Tue 08 Mar 2022 08:19:25 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20220308: hw: aspeed_gpio: Cleanup stray semicolon after switch hw/arm/aspeed: add Bletchley machine type hw/arm/aspeed: allow missing spi_model hw/block: m25p80: Add support for w25q01jvq aspeed/smc: Fix error log aspeed/smc: Let the SSI core layer define the bus name aspeed/smc: Rename 'max_peripherals' to 'cs_num_max' aspeed/smc: Remove 'num_cs' field aspeed: Rework aspeed_board_init_flashes() interface aspeed/smc: Use max number of CE instead of 'num_cs' aspeed: Fix a potential memory leak bug in write_boot_rom() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-09Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2022-03-07' into ↵Peter Maydell
staging nbd patches for 2022-03-07 - Dan Berrange: Allow qemu-nbd to support TLS over Unix sockets - Eric Blake: Minor cleanups related to 64-bit block operations # gpg: Signature made Tue 08 Mar 2022 01:41:35 GMT # gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full] # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full] # gpg: aka "[jpeg image of size 6874]" [full] # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2022-03-07: qemu-io: Allow larger write zeroes under no fallback qemu-io: Utilize 64-bit status during map nbd/server: Minor cleanups tests/qemu-iotests: validate NBD TLS with UNIX sockets and PSK tests/qemu-iotests: validate NBD TLS with UNIX sockets tests/qemu-iotests: validate NBD TLS with hostname mismatch tests/qemu-iotests: convert NBD TLS test to use standard filters tests/qemu-iotests: introduce filter for qemu-nbd export list tests/qemu-iotests: expand _filter_nbd rules tests/qemu-iotests: add QEMU_IOTESTS_REGEN=1 to update reference file block/nbd: don't restrict TLS usage to IP sockets qemu-nbd: add --tls-hostname option for TLS certificate validation block/nbd: support override of hostname for TLS certificate validation block: pass desired TLS hostname through from block driver client crypto: mandate a hostname when checking x509 creds on a client Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-09esp: convert ESPState pdma_cb from a function pointer to an integerMark Cave-Ayland
This prepares for the inclusion of the current PDMA callback in the migration stream since the callback is referenced by an integer instead of a function pointer. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macfb: increase number of registers saved in MacfbStateMark Cave-Ayland
The MacOS toolbox ROM accesses a number of addresses between 0x0 and 0x200 during initialisation and resolution changes. Whilst the function of many of these registers is unknown, it is worth the minimal cost of saving these extra values as part of migration to help future-proof the migration stream for the q800 machine as it starts to stabilise. Note this is a migration break, but since there are upcoming incompatible changes for the q800 machine (and migration does not even succeed without these patches) then this is not an issue. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macfb: don't use special irq_state and irq_mask variables in MacfbStateMark Cave-Ayland
The current IRQ state and IRQ mask are handled exactly the same as standard register accesses, so store these values directly in the regs array rather than having separate variables for them. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macio/pmu.c: remove redundant codeMark Cave-Ayland
Now that the logic related to edge-triggered interrupts is all contained within the mos6522 device the redundant implementation for the mac99 PMU device can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQsMark Cave-Ayland
The mos6522 datasheet describes how the control lines IRQs are edge-triggered according to the configuration in the PCR register. Implement the logic according to the datasheet so that the interrupt bits in IFR are latched when the edge is detected, and cleared when reading portA/portB or writing to IFR as necessary. To maintain bisectibility this change also updates the SCSI, SCSI data, Nubus and VIA2 60Hz/1Hz clocks in the q800 machine to be negative edge-triggered as confirmed by the PCR programming in all of Linux, NetBSD and MacOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: record last_irq_levels in mos6522_set_irq()Mark Cave-Ayland
To detect edge-triggered IRQs it is necessary to store the last state of each IRQ in a last_irq_levels bitmap. Note: this is a migration break for machines which use mos6522 instances which are g3beige/mac99 (PPC) and q800 (m68k). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: add "info via" HMP command for debuggingMark Cave-Ayland
This displays detailed information about the device registers and timers to aid debugging problems with timers and interrupts. Currently the QAPI generators for HumanReadableText don't work correctly if used in qapi/target-misc.json when a non-specified target is built, so for now manually add a hmp_info_via() wrapper until direct support for per-device HMP/QMP commands is implemented. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: add register names to register read/write trace eventsMark Cave-Ayland
This helps to follow how the guest is programming the mos6522 when debugging. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClassMark Cave-Ayland
Now that the mos6522 IRQs are managed using standard qdev gpios these methods are no longer required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: switch over to use qdev gpios for IRQsMark Cave-Ayland
For historical reasons each mos6522 instance implements its own setting and update of the IFR flag bits using methods exposed by MOS6522DeviceClass. As of today this is no longer required, and it is now possible to implement the mos6522 IRQs as standard qdev gpios. Switch over to use qdev gpios for the mos6522 device and update all instances accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mac_via: use IFR bit flag constants for VIA2 IRQsMark Cave-Ayland
This allows us to easily see how the physical control lines are mapped to the IFR bit flags. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mac_via: use IFR bit flag constants for VIA1 IRQsMark Cave-Ayland
This allows us to easily see how the physical control lines are mapped to the IFR bit flags. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: add defines for IFR bit flagsMark Cave-Ayland
These are intended to make it easier to see how the physical control lines are wired for each instance. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into stagingPeter Maydell
MIPS patches queue - Fix CP0 cycle counter timing - Fix VMState of gt64120 IRQs - Long due PIIX4 QOM cleanups - ISA IRQ QOM'ification / cleanups # gpg: Signature made Tue 08 Mar 2022 18:39:42 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20220308: tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag hw/isa: Inline and remove one-line isa_init_irq() hw/isa: Drop unused attributes from ISADevice hw/isa/isa-bus: Remove isabus_dev_print() hw/input/pckbd: QOM'ify IRQ numbers hw/rtc/m48t59-isa: QOM'ify IRQ number hw/rtc/mc146818rtc: QOM'ify IRQ number hw/mips/gt64xxx_pci: Resolve gt64120_register() hw/isa/piix4: Replace some magic IRQ constants hw/isa/piix4: Resolve global instance variable hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq() hw/isa/piix4: Resolve redundant i8259[] attribute malta: Move PCI interrupt handling from gt64xxx_pci to piix4 hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration target/mips: Remove duplicated MIPSCPU::cp0_count_rate target/mips: Fix cycle counter timing calculations Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-08Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio,pc,pci: features, cleanups, fixes vhost-user enabled on non-linux systems beginning of nvme sriov support bigger tx queue for vdpa virtio iommu bypass FADT flag to detect legacy keyboards Fixes, cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 07 Mar 2022 22:43:31 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (47 commits) hw/acpi/microvm: turn on 8042 bit in FADT boot architecture flags if present tests/acpi: i386: update FACP table differences hw/acpi: add indication for i8042 in IA-PC boot flags of the FADT table tests/acpi: i386: allow FACP acpi table changes docs: vhost-user: add subsection for non-Linux platforms configure, meson: allow enabling vhost-user on all POSIX systems vhost: use wfd on functions setting vring call fd event_notifier: add event_notifier_get_wfd() pci: drop COMPAT_PROP_PCP for 2.0 machine types hw/smbios: Add table 4 parameter, "processor-id" x86: cleanup unused compat_apic_id_mode vhost-vsock: detach the virqueue element in case of error pc: add option to disable PS/2 mouse/keyboard acpi: pcihp: pcie: set power on cap on parent slot pci: expose TYPE_XIO3130_DOWNSTREAM name pci: show id info when pci BDF conflict hw/misc/pvpanic: Use standard headers instead headers: Add pvpanic.h pci-bridge/xio3130_downstream: Fix error handling pci-bridge/xio3130_upstream: Fix error handling ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # docs/specs/index.rst
2022-03-08hw/isa: Inline and remove one-line isa_init_irq()Bernhard Beschow
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). It can therefore be removed. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> (tpm_tis_isa) Acked-by: Corey Minyard <cminyard@mvista.com> (isa_ipmi_bt, isa_ipmi_kcs) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220301220037.76555-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-14-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/isa: Drop unused attributes from ISADeviceBernhard Beschow
Now that the last users of ISADevice::isairq[] have been resolved during the previous commits, it can be removed for good. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-13-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/rtc/mc146818rtc: QOM'ify IRQ numberBernhard Beschow
Exposing the IRQ number as a QOM property not only allows it to be configurable but also to be displayed in HMP: Before: (qemu) info qtree ... dev: mc146818rtc, id "" gpio-out "" 1 base_year = 0 (0x0) lost_tick_policy = "discard" After: dev: mc146818rtc, id "" gpio-out "" 1 base_year = 0 (0x0) irq = 8 (0x8) lost_tick_policy = "discard" The reason the IRQ number didn's show up before is that this device does not call isa_init_irq(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-9-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/mips/gt64xxx_pci: Resolve gt64120_register()Bernhard Beschow
Now that gt64120_register() lost its pic parameter, there is an opportunity to remove it. gt64120_register() is old style by wrapping qdev API, and the new style is to use qdev directly. So take the opportunity and modernize the code. Suggested-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20220217101924.15347-8-shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-25 02:05:18 +0000