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2021-05-10modules: add have_vgaGerd Hoffmann
Introduce a symbol which can be used to prevent display modules which need vga support being loaded into system emulators with CONFIG_VGA=n. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-16-kraxel@redhat.com>
2021-05-10virtio-gpu: move fields to struct VirtIOGPUGLGerd Hoffmann
Move two virglrenderer state variables to struct VirtIOGPUGL. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-14-kraxel@redhat.com>
2021-05-10virtio-gpu: drop use_virgl_rendererGerd Hoffmann
Now that we have separated the gl and non-gl code flows to two different devices there is little reason turn on and off virglrenderer usage at runtime. The gl code can simply use virglrenderer unconditionally. So drop use_virgl_renderer field and just do that. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-13-kraxel@redhat.com>
2021-05-10virtio-gpu: move update_cursor_dataGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-10-kraxel@redhat.com>
2021-05-10virtio-gpu: move virgl process_cmdGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-9-kraxel@redhat.com>
2021-05-10virtio-gpu: use class function for ctrl queue handlersGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-6-kraxel@redhat.com>
2021-05-10virtio-gpu: move virgl resetGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-5-kraxel@redhat.com>
2021-05-10virtio-gpu: move virgl realize + propertiesGerd Hoffmann
Move device init (realize) and properties. Drop the virgl property, the virtio-gpu-gl-device has virgl enabled no matter what. Just use virtio-gpu-device instead if you don't want enable virgl and opengl. This simplifies the logic and reduces the test matrix. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-4-kraxel@redhat.com>
2021-05-10virtio-gpu: add virtio-gpu-gl-deviceGerd Hoffmann
Just a skeleton for starters, following patches will add more code. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-3-kraxel@redhat.com>
2021-05-10virtio-gpu: handle partial maps properlyGerd Hoffmann
dma_memory_map() may map only a part of the request. Happens if the request can't be mapped in one go, for example due to a iommu creating a linear dma mapping for scattered physical pages. Should that be the case virtio-gpu must call dma_memory_map() again with the remaining range instead of simply throwing an error. Note that this change implies the number of iov entries may differ from the number of mapping entries sent by the guest. Therefore the iov_len bookkeeping needs some updates too, we have to explicitly pass around the iov length now. Reported-by: Auger Eric <eric.auger@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210506091001.1301250-1-kraxel@redhat.com Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20210506091001.1301250-1-kraxel@redhat.com>
2021-05-10edid: Make refresh rate configurableAkihiko Odaki
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210427150824.638359-1-kraxel@redhat.com Message-Id: <20210427150824.638359-6-kraxel@redhat.com>
2021-05-05Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-20210504' ↵Peter Maydell
into staging ppc patch queue 2021-05-04 Here's the first ppc pull request for qemu-6.1. It has a wide variety of stuff accumulated during the 6.0 freeze. Highlights are: * Multi-phase reset cleanups for PAPR * Preliminary cleanups towards allowing !CONFIG_TCG for the ppc target * Cleanup of AIL logic and extension to POWER10 * Further improvements to handling of hot unplug failures on PAPR * Allow much larger numbers of CPU on pseries * Support for the H_SCM_HEALTH hypercall * Add support for the Pegasos II board * Substantial cleanup to hflag handling * Assorted minor fixes and cleanups # gpg: Signature made Tue 04 May 2021 06:52:39 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.1-20210504: (46 commits) hw/ppc/pnv_psi: Use device_cold_reset() instead of device_legacy_reset() hw/ppc/spapr_vio: Reset TCE table object with device_cold_reset() hw/intc/spapr_xive: Use device_cold_reset() instead of device_legacy_reset() target/ppc: removed VSCR from SPR registration target/ppc: Reduce the size of ppc_spr_t target/ppc: Clean up _spr_register et al target/ppc: Add POWER10 exception model target/ppc: rework AIL logic in interrupt delivery target/ppc: move opcode table logic to translate.c target/ppc: code motion from translate_init.c.inc to gdbstub.c spapr_drc.c: handle hotunplug errors in drc_unisolate_logical() spapr.h: increase FDT_MAX_SIZE spapr.c: do not use MachineClass::max_cpus to limit CPUs ppc: Rename current DAWR macros and variables target/ppc: POWER10 supports scv target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour docs/system: ppc: Add documentation for ppce500 machine roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support roms/Makefile: Update ppce500 u-boot build directory name ppc/spapr: Add support for implement support for H_SCM_HEALTH ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-05Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging Trivial patches pull request 20210503 # gpg: Signature made Mon 03 May 2021 09:34:56 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: (23 commits) hw/rx/rx-gdbsim: Do not accept invalid memory size docs: More precisely describe memory-backend-*::id's user scripts: fix generation update-binfmts templates docs/system: Document the removal of "compat" property for POWER CPUs mc146818rtc: put it into the 'misc' category Do not include exec/address-spaces.h if it's not really necessary Do not include cpu.h if it's not really necessary Do not include hw/boards.h if it's not really necessary Do not include sysemu/sysemu.h if it's not really necessary hw: Do not include qemu/log.h if it is not necessary hw: Do not include hw/irq.h if it is not necessary hw: Do not include hw/sysbus.h if it is not necessary hw: Remove superfluous includes of hw/hw.h ui: Fix memory leak in qemu_xkeymap_mapping_table() hw/usb: Constify VMStateDescription hw/display/qxl: Constify VMStateDescription hw/arm: Constify VMStateDescription vmstate: Constify some VMStateDescriptions Fix typo in CFI build documentation hw/pcmcia: Do not register PCMCIA type if not required ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-04Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210503' ↵Peter Maydell
into staging Aspeed patches : * Fixes for the DMA space * New model for ASPEED's Hash and Crypto Engine (Joel and Klaus) * Acceptance tests (Joel) * A fix for the XDMA model * Some extra features for the SMC controller. * Two new boards : rainier-bmc and quanta-q7l1-bmc (Patrick) # gpg: Signature made Mon 03 May 2021 06:23:36 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20210503: aspeed: Add support for the quanta-q7l1-bmc board hw/block: m25p80: Add support for mt25ql02g and mt25qu02g aspeed: Add support for the rainier-bmc board aspeed: Deprecate the swift-bmc machine tests/qtest: Rename m25p80 test in aspeed_smc test aspeed/smc: Add extra controls to request DMA aspeed/smc: Add a 'features' attribute to the object class hw/misc/aspeed_xdma: Add AST2600 support tests/acceptance: Test ast2600 machine tests/acceptance: Test ast2400 and ast2500 machines tests/qtest: Add test for Aspeed HACE aspeed: Integrate HACE hw: Model ASPEED's Hash and Crypto Engine hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias aspeed/i2c: Rename DMA address space aspeed/i2c: Fix DMA address mask aspeed/smc: Remove unused "sdram-base" property aspeed/smc: Use the RAM memory region for DMAs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-04spapr.h: increase FDT_MAX_SIZEDaniel Henrique Barboza
Certain SMP topologies stress, e.g. 1 thread/core, 2048 cores and 1 socket, stress the current maximum size of the pSeries FDT: Calling ibm,client-architecture-support...qemu-system-ppc64: error creating device tree: (fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", segs, sizeof(segs))): FDT_ERR_NOSPACE 2048 is the default NR_CPUS value for the pSeries kernel. It's expected that users will want QEMU to be able to handle this kind of configuration. Bumping FDT_MAX_SIZE to 2MB is enough for these setups to be created. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210408204049.221802-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-04ppc: Rename current DAWR macros and variablesRavi Bangoria
Power10 is introducing second DAWR. Use real register names (with suffix 0) from ISA for current macros and variables used by Qemu. One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel uapi header and thus not changed in kernel as well as Qemu. Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210412114433.129702-3-ravi.bangoria@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-04ppc/spapr: Add support for implement support for H_SCM_HEALTHVaibhav Jain
Add support for H_SCM_HEALTH hcall described at [1] for spapr nvdimms. This enables guest to detect the 'unarmed' status of a specific spapr nvdimm identified by its DRC and if its unarmed, mark the region backed by the nvdimm as read-only. The patch adds h_scm_health() to handle the H_SCM_HEALTH hcall which returns two 64-bit bitmaps (health bitmap, health bitmap mask) derived from 'struct nvdimm->unarmed' member. Linux kernel side changes to enable handling of 'unarmed' nvdimms for ppc64 are proposed at [2]. References: [1] "Hypercall Op-codes (hcalls)" https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/powerpc/papr_hcalls.rst#n220 [2] "powerpc/papr_scm: Mark nvdimm as unarmed if needed during probe" https://lore.kernel.org/linux-nvdimm/20210329113103.476760-1-vaibhav@linux.ibm.com/ Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Message-Id: <20210402102128.213943-1-vaibhav@linux.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-04hw/pci-host: Add emulation of Marvell MV64361 PPC system controllerBALATON Zoltan
The Marvell Discovery II aka. MV64361 is a PowerPC system controller chip that is used on the pegasos2 PPC board. This adds emulation of it that models the device enough to boot guests on this board. The mv643xx.h header with register definitions is taken from Linux 4.15.10 only fixing white space errors, removing not needed parts and changing formatting for QEMU coding style. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <79545ebd03bfe0665b73d2d7cbc74fdf3d62629e.1616680239.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-04vt82c686: Add emulation of VT8231 south bridgeBALATON Zoltan
Add emulation of VT8231 south bridge ISA part based on the similar VT82C686B but implemented in a separate subclass that holds the differences while reusing parts that can be shared. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <10abc9f89854e7c980b9731c33d25a2e307e9c4f.1616680239.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-04vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on itBALATON Zoltan
To allow reusing ISA bridge emulation for vt8231_isa move the device state of vt82c686b_isa emulation in an abstract via_isa class. This change breaks migration back compatibility but this is not an issue for Fuloong2E machine which is not versioned or migration supported. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <0cb8fc69c7aaa555589181931b881335fecd2ef3.1616680239.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-04vt82c686: QOM-ify superio related functionalityBALATON Zoltan
Collect superio functionality and its controlling config registers handling in an abstract VIA_SUPERIO class that is a subclass of ISA_SUPERIO and put vt82c686b specific parts in a subclass of this abstract class. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <fbcc8cc8baf83f327612a1ef1c14bcbcdb0e7edb.1616680239.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-02hw: Remove superfluous includes of hw/hw.hThomas Huth
The include/hw/hw.h header only has a prototype for hw_error(), so it does not make sense to include this in files that do not use this function. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210326151848.2217216-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-02vmstate: Constify some VMStateDescriptionsKeqian Zhu
Constify vmstate_ecc_state and vmstate_x86_cpu. Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210408140706.23412-1-zhukeqian1@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-01exec: Remove accel/tcg/ from include pathsPhilippe Mathieu-Daudé
When TCG is enabled, the accel/tcg/ include path is added to the project global include search list. This accel/tcg/ directory contains a header named "internal.h" which, while intented to be internal to accel/tcg/, is accessible by all files compiled when TCG is enabled. This might lead to problem with other directories using the same "internal.h" header name: $ git ls-files | fgrep /internal.h accel/tcg/internal.h include/hw/ide/internal.h target/hexagon/internal.h target/mips/internal.h target/ppc/internal.h target/s390x/internal.h As we don't need to expose accel/tcg/ internals to the rest of the code base, simplify by removing it from the include search list, and include the accel/tcg/ public headers relative to the project root search path (which is already in the generic include search path). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210413081008.3409459-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01aspeed/smc: Add extra controls to request DMACédric Le Goater
The AST2600 SPI controllers have a set of bits to request/grant DMA access. Add a new SMC feature for these controllers and use it to check access to the DMA registers. Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210407171637.777743-16-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01aspeed/smc: Add a 'features' attribute to the object classCédric Le Goater
It will simplify extensions of the SMC model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210407171637.777743-15-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01hw/misc/aspeed_xdma: Add AST2600 supportCédric Le Goater
When we introduced support for the AST2600 SoC, the XDMA controller was forgotten. It went unnoticed because it's not used under emulation. But the register layout being different, the reset procedure is bogus and this breaks kexec. Add a AspeedXDMAClass to take into account the register differences. Cc: Eddie James <eajames@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Eddie James <eajames@linux.ibm.com> Message-Id: <20210407171637.777743-14-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01aspeed: Integrate HACEJoel Stanley
Add the hash and crypto engine model to the Aspeed socs. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210409000253.1475587-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01hw: Model ASPEED's Hash and Crypto EngineJoel Stanley
The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1, SHA2, RSA and other cryptographic algorithms. This initial model implements a subset of the device's functionality; currently only MD5/SHA hashing, and on the ast2600's scatter gather engine. Co-developed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> [ clg: - fixes for 32-bit and OSX builds ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210409000253.1475587-2-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use aliasPhilippe Mathieu-Daudé
The flash mmio region is exposed as an AddressSpace. AddressSpaces must not be sysbus-mapped, therefore map the region using an alias. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [ clg : Fix DMA_FLASH_ADDR() ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210312182851.1922972-3-f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210407171637.777743-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01aspeed/smc: Remove unused "sdram-base" propertyCédric Le Goater
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210407171637.777743-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-04-30Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block layer patches - Fix permission update order problems with block graph changes - qemu-img convert: Unshare write permission for source - vhost-user-blk: Fail gracefully on too large queue size # gpg: Signature made Fri 30 Apr 2021 11:27:51 BST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (39 commits) vhost-user-blk: Fail gracefully on too large queue size qemu-img convert: Unshare write permission for source block: Add BDRV_O_NO_SHARE for blk_new_open() block: refactor bdrv_node_check_perm() block: rename bdrv_replace_child_safe() to bdrv_replace_child() block: refactor bdrv_child_set_perm_safe() transaction action block: inline bdrv_replace_child() block: inline bdrv_check_perm_common() block: drop unused permission update functions block: bdrv_reopen_multiple: refresh permissions on updated graph block: bdrv_reopen_multiple(): move bdrv_flush to separate pre-prepare block: add bdrv_set_backing_noperm() transaction action block: make bdrv_refresh_limits() to be a transaction action block: make bdrv_unset_inherits_from to be a transaction action block: drop ignore_children for permission update functions block/backup-top: drop .active block: introduce bdrv_drop_filter() block: add bdrv_remove_filter_or_cow transaction action block: adapt bdrv_append() for inserting filters block: split out bdrv_replace_node_noperm() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-30block: Add BDRV_O_NO_SHARE for blk_new_open()Kevin Wolf
Normally, blk_new_open() just shares all permissions. This was fine originally when permissions only protected against uses in the same process because no other part of the code would actually get to access the block nodes opened with blk_new_open(). However, since we use it for file locking now, unsharing permissions becomes desirable. Add a new BDRV_O_NO_SHARE flag that is used in blk_new_open() to unshare any permissions that can be unshared. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210422164344.283389-2-kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30block: refactor bdrv_child_set_perm_safe() transaction actionVladimir Sementsov-Ogievskiy
Old interfaces dropped, nobody directly calls bdrv_child_set_perm_abort() and bdrv_child_set_perm_commit(), so we can use personal state structure for the action and stop exploiting BdrvChild structure. Also, drop "_safe" suffix which is redundant now. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210428151804.439460-35-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30block: bdrv_reopen_multiple: refresh permissions on updated graphVladimir Sementsov-Ogievskiy
Move bdrv_reopen_multiple to new paradigm of permission update: first update graph relations, then do refresh the permissions. We have to modify reopen process in file-posix driver: with new scheme we don't have prepared permissions in raw_reopen_prepare(), so we should reconfigure fd in raw_check_perm(). Still this seems more native and simple anyway. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210428151804.439460-31-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30block: make bdrv_refresh_limits() to be a transaction actionVladimir Sementsov-Ogievskiy
To be used in further commit. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210428151804.439460-28-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30block: introduce bdrv_drop_filter()Vladimir Sementsov-Ogievskiy
Using bdrv_replace_node() for removing filter is not good enough: it keeps child reference of the filter, which may conflict with original top node during permission update. Instead let's create new interface, which will do all graph modifications first and then update permissions. Let's modify bdrv_replace_node_common(), allowing it additionally drop backing chain child link pointing to new node. This is quite appropriate for bdrv_drop_intermediate() and makes possible to add new bdrv_drop_filter() as a simple wrapper. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210428151804.439460-24-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30util: add transactions.cVladimir Sementsov-Ogievskiy
Add simple transaction API to use in further update of block graph operations. Supposed usage is: - "prepare" is main function of the action and it should make the main effect of the action to be visible for the following actions, keeping possibility of roll-back, saving necessary things in action state, which is prepended to the action list (to do that, prepare func should call tran_add()). So, driver struct doesn't include "prepare" field, as it is supposed to be called directly. - commit/rollback is supposed to be called for the list of action states, to commit/rollback all the actions in reverse order - When possible "commit" should not make visible effect for other actions, which make possible transparent logical interaction between actions. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210428151804.439460-9-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30block: make bdrv_reopen_{prepare,commit,abort} privateVladimir Sementsov-Ogievskiy
These functions are called only from bdrv_reopen_multiple() in block.c. No reason to publish them. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210428151804.439460-8-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30block: drop ctx argument from bdrv_root_attach_childVladimir Sementsov-Ogievskiy
Passing parent aio context is redundant, as child_class and parent opaque pointer are enough to retrieve it. Drop the argument and use new bdrv_child_get_parent_aio_context() interface. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210428151804.439460-7-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30block: BdrvChildClass: add .get_parent_aio_context handlerVladimir Sementsov-Ogievskiy
Add new handler to get aio context and implement it in all child classes. Add corresponding public interface to be used soon. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210428151804.439460-6-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-04-30hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windowsPeter Maydell
Currently the gpex PCI controller implements no special behaviour for guest accesses to areas of the PIO and MMIO where it has not mapped any PCI devices, which means that for Arm you end up with a CPU exception due to a data abort. Most host OSes expect "like an x86 PC" behaviour, where bad accesses like this return -1 for reads and ignore writes. In the interests of not being surprising, make host CPU accesses to these windows behave as -1/discard where there's no mapped PCI device. The old behaviour generally didn't cause any problems, because almost always the guest OS will map the PCI devices and then only access where it has mapped them. One corner case where you will see this kind of access is if Linux attempts to probe legacy ISA devices via a PIO window access. So far the only case where we've seen this has been via the syzkaller fuzzer. Reported-by: Dmitry Vyukov <dvyukov@google.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20210325163315.27724-1-peter.maydell@linaro.org Fixes: https://bugs.launchpad.net/qemu/+bug/1918917 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-30hw: add compat machines for 6.1Cornelia Huck
Add 6.1 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Greg Kurz <groug@kaod.org> Message-id: 20210331111900.118274-1-cohuck@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-23net: check the existence of peer before trying to padJason Wang
There could be case that peer is NULL. This can happen when during network device hot-add where net device needs to be added first. So the patch check the existence of peer before trying to do the pad. Fixes: 969e50b61a285 ("net: Pad short frames to minimum size before sending from SLiRP/TAP") Signed-off-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 20210423031803.1479-1-jasowang@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-17include/qemu/osdep.h: Move system includes to topPeter Maydell
Mostly osdep.h puts the system includes at the top of the file; but there are a couple of exceptions where we include a system header halfway through the file. Move these up to the top with the rest so that all the system headers we include are included before we include os-win32.h or os-posix.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416135543.20382-4-peter.maydell@linaro.org Message-id: 20210414184343.26235-1-peter.maydell@linaro.org
2021-04-17osdep: protect qemu/osdep.h with extern "C"Paolo Bonzini
System headers may include templates if compiled with a C++ compiler, which cause the compiler to complain if qemu/osdep.h is included within a C++ source file's 'extern "C"' block. Add an 'extern "C"' block directly to qemu/osdep.h, so that system headers can be kept out of it. There is a stray declaration early in qemu/osdep.h, which needs to be special cased. Add a definition in qemu/compiler.h to make it look nice. config-host.h, CONFIG_TARGET, exec/poison.h and qemu/compiler.h are included outside the 'extern "C"' block; that is not an issue because they consist entirely of preprocessor directives. This allows us to move the include of osdep.h in our two C++ source files outside the extern "C" block they were previously using for it, which in turn means that they compile successfully against newer versions of glib which insist that glib.h is *not* inside an extern "C" block. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416135543.20382-3-peter.maydell@linaro.org [PMM: Moved disas/arm-a64.cc osdep.h include out of its extern "C" block; explained in commit message why we're doing this] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-17osdep: include glib-compat.h before other QEMU headersPaolo Bonzini
glib-compat.h is sort of like a system header, and it needs to include system headers (glib.h) that may dislike being included under 'extern "C"'. Move it right after all system headers and before all other QEMU headers. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416135543.20382-2-peter.maydell@linaro.org [PMM: Added comment about why glib-compat.h is special] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-13Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210412' ↵Peter Maydell
into staging ppc patch queue for 2021-04-21 Here's what I hope is the last ppc related pull request for qemu-6.0. The 2 patches here revert a behavioural change that after further discussion we concluded was a bad idea (adding a timeout for possibly-failed hot unplug requests). Instead it implements a different approach to the original problem: we again let unplug requests the guest doesn't respond to remain pending indefinitely, but no longer allow those to block attempts to retry the same unplug again. The change is a bit more complex than I'd like for this late in the freeze. Nonetheless, I think it's important to merge this for 6.0, so we don't allow a release which has the probably-a-bad-idea timeout behaviour. # gpg: Signature made Mon 12 Apr 2021 06:25:58 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.0-20210412: spapr.c: always pulse guest IRQ in spapr_core_unplug_request() spapr: rollback 'unplug timeout' for CPU hotunplugs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-12esp: fix setting of ESPState mig_version_id when launching QEMU with -S optionMark Cave-Ayland
If QEMU is launched with the -S option then the ESPState mig_version_id property is left unset due to the ordering of the VMState fields in the VMStateDescription for sysbusespscsi and pciespscsi. If the VM is migrated and restored in this stopped state, the version tests in the vmstate_esp VMStateDescription and esp_post_load() become confused causing the migration to fail. Fix the ordering problem by moving the setting of mig_version_id to a common esp_pre_save() function which is invoked first by both sysbusespscsi and pciespscsi rather than at the point where ESPState is itself serialised into the migration stream. Buglink: https://bugs.launchpad.net/qemu/+bug/1922611 Fixes: 0bd005be78 ("esp: add vmstate_esp version to embedded ESPState") Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210407124842.32695-1-mark.cave-ayland@ilande.co.uk>
2021-04-12exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1Richard Henderson
Unfortuately, the elements of PAGE_* were not in numerical order and so PAGE_ANON was added to an "unused" bit. As an arbitrary choice, move PAGE_TARGET_{1,2} together. Cc: Laurent Vivier <laurent@vivier.eu> Fixes: 26bab757d41b ("linux-user: Introduce PAGE_ANON") Buglink: https://bugs.launchpad.net/bugs/1922617 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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