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2015-05-29hw/acpi/aml-build: Add ToUUID macroShannon Zhao
Add ToUUID macro, this is useful for generating PCIe ACPI table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1432522520-8068-16-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/acpi/aml-build: Make aml_buffer() definition consistent with the specShannon Zhao
According to ACPI spec, DefBuffer can take two parameters: BufferSize and ByteList. Make it consistent with the spec. Uninitialized buffer could be requested by passing ByteList as NULL to reserve space. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1432522520-8068-15-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate RSDT tableShannon Zhao
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86. Here we still use RSDT as UEFI puts ACPI tables below 4G address space, and UEFI ignore the RSDT or XSDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-12-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate GTDT tableShannon Zhao
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate MADT tableShannon Zhao
MADT describes GIC enabled ARM platforms. The GICC and GICD subtables are used to define the GIC regions. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate FADT table and update ACPI headersShannon Zhao
In the case of mach virt, it is used to set the Hardware Reduced bit and enable PSCI SMP booting through HVC. So ignore FACS and FADT points to DSDT. Update the header definitions for FADT taking into account the new additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h` Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-9-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/acpi/aml-build: Add aml_interrupt() termShannon Zhao
Add aml_interrupt() for describing device interrupt in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-7-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/acpi/aml-build: Add aml_memory32_fixed() termShannon Zhao
Add aml_memory32_fixed() for describing device mmio region in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1432522520-8068-6-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARMShannon Zhao
Introduce a preliminary framework in virt-acpi-build.c with the main ACPI build functions. It exposes the generated ACPI contents to guest over fw_cfg. The required ACPI v5.1 tables for ARM are: - RSDP: Initial table that points to XSDT - RSDT: Points to FADT GTDT MADT tables - FADT: Generic information about the machine - GTDT: Generic timer description table - MADT: Multiple APIC description table - DSDT: Holds all information about system devices/peripherals, pointed by FADT Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-5-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Record PCIe ranges in MemMapEntry arrayShannon Zhao
To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Move common definitions to virt.hShannon Zhao
Move some common definitions to virt.h. These will be used by generating ACPI tables. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/acpi/aml-build: Make enum values to be upper case to match coding styleShannon Zhao
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-2-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-27linux/elf.h updateEric Farman
Sync with kernel elf.h updates to get s390x vector register definitions. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-26Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into stagingPeter Maydell
# gpg: Signature made Fri May 22 20:58:44 2015 BST using RSA key ID AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/ide-pull-request: ahci: do not remap clb/fis unconditionally macio: move unaligned DMA write code into separate pmac_dma_write() function macio: move unaligned DMA read code into separate pmac_dma_read() function qtest: pre-buffer hex nibs libqos/ahci: Swap memread/write with bufread/write qtest: add memset to qtest protocol qtest: Add base64 encoded read/write qtest: allow arbitrarily long sends qtest/ahci: add migrate halted dma test qtest/ahci: add halted dma test qtest/ahci: add flush migrate test qtest/ahci: add migrate dma test qtest/ahci: Add migration test ich9/ahci: Enable Migration libqos: Add migration helpers libqos/ahci: Fix sector set method libqos/ahci: Add halted command helpers glib: remove stale compat functions configure: require glib 2.22 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-22macio: move unaligned DMA write code into separate pmac_dma_write() functionMark Cave-Ayland
Similarly switch the macio IDE routines over to use the new function and tidy-up the remaining code as required. [Maintainer edit: printf format codes adjusted for 32/64bit. --js] Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: John Snow <jsnow@redhat.com> Message-id: 1425939893-14404-3-git-send-email-mark.cave-ayland@ilande.co.uk Signed-off-by: John Snow <jsnow@redhat.com>
2015-05-22glib: remove stale compat functionsJohn Snow
Since we're bumping the version to 2.22+, remove the now-stale compat functions. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1431469140-22208-2-git-send-email-jsnow@redhat.com
2015-05-22util: move read_password method out of qemu-img into osdep/oslibDaniel P. Berrange
The qemu-img.c file has a read_password() method impl that is used to prompt for passwords on the console, with impls for POSIX and Windows. This will be needed by qemu-io.c too, so move it into the QEMU osdep/oslib files where it can be shared without code duplication Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-05-22block: minimal bounce buffer alignmentDenis V. Lunev
The patch introduces new concept: minimal memory alignment for bounce buffers. Original so called "optimal" value is actually minimal required value for aligment. It should be used for validation that the IOVec is properly aligned and bounce buffer is not required. Though, from the performance point of view, it would be better if bounce buffer or IOVec allocated by QEMU will be aligned stricter. The patch does not change any alignment value yet. Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 1431441056-26198-2-git-send-email-den@openvz.org CC: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> CC: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-05-18arm: xlnx-zynqmp: Add UART supportPeter Crosthwaite
There are 2x Cadence UARTs in Zynq MP. Add them. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18char: cadence_uart: Split state struct and type into headerPeter Crosthwaite
Create a new header for Cadence UART to allow using the device with modern SoC programming conventions. The state struct needs to be visible to embed the device in SoC containers. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 46a0fbd45b6b205f54c4a8c778deb75c77f8abdf.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: xlnx-zynqmp: Add GEM supportPeter Crosthwaite
There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18net: cadence_gem: Split state struct and type into headerPeter Crosthwaite
Create a new header for Cadence GEM to allow using the device with modern SoC programming conventions. The state struct needs to be visible to embed the device in SoC containers. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a98b5df6440c5bff8f813a26bb53ce1cfefb4c4c.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: xlnx-zynqmp: Add GICPeter Crosthwaite
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: Introduce Xilinx ZynqMP SoCPeter Crosthwaite
With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Make ICCICR/GICC_CTLR bankedFabian Aggeler
ICCICR/GICC_CTLR is banked in GICv1 implementations with Security Extensions or in GICv2 in independent from Security Extensions. This makes it possible to enable forwarding of interrupts from the CPU interfaces to the connected processors for Group0 and Group1. We also allow to set additional bits like AckCtl and FIQEn by changing the type from bool to uint32. Since the field does not only store the enable bit anymore and since we are touching the vmstate, we use the opportunity to rename the field to cpu_ctlr. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-9-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-9-git-send-email-greg.bellows@linaro.org [PMM: rewrote to store state in a single uint32_t rather than keeping the NS and S banked variants separate; this considerably simplifies the get/set functions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Make ICCBPR/GICC_BPR bankedFabian Aggeler
This register is banked in GICs with Security Extensions. Storing the non-secure copy of BPR in the abpr, which is an alias to the non-secure copy for secure access. ABPR itself is only accessible from secure state if the GIC implements Security Extensions. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-8-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-10-git-send-email-greg.bellows@linaro.org [PMM: rewrote to fix style issues and correct handling of GICv2 without security extensions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Make ICDDCR/GICD_CTLR bankedFabian Aggeler
ICDDCR/GICD_CTLR is banked if the GIC has the security extensions, and the S (or only) copy has separate enable bits for Group0 and Group1 enable if the GIC implements interrupt groups. EnableGroup0 (Bit [1]) in GICv1 is architecturally IMPDEF. Since this bit (Enable Non-secure) is present in the integrated GIC of the Cortex-A9 MPCore, we support this bit in our GICv1 implementation too. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-7-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-8-git-send-email-greg.bellows@linaro.org [PMM: rewritten to store the state in a single s->ctlr uint32, with the NS register handled as an alias of bit 1 in that value; added vmstate version bump] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Add Interrupt Group RegistersFabian Aggeler
The Interrupt Group Registers allow the guest to configure interrupts into one of two groups, where Group0 are higher priority and may be routed to IRQ or FIQ, and Group1 are lower priority and always routed to IRQ. (In a GIC with the security extensions Group0 is Secure interrupts and Group 1 is NonSecure.) The GICv2 always supports interrupt grouping; the GICv1 does only if it implements the security extensions. This patch implements the ability to read and write the registers; the actual functionality the bits control will be added in a subsequent patch. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-5-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-7-git-send-email-greg.bellows@linaro.org [PMM: bring GIC_*_GROUP macros into line with the others, ie a simple SET/CLEAR/TEST rather than GROUP0/GROUP1; utility gic_has_groups() function; minor style fixes; bump vmstate version] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Add Security Extensions propertyFabian Aggeler
Add a QOM property which allows the GIC Security Extensions to be enabled. These are an optional part of the GICv1 and GICv2 architecture. This commit just adds the property and some sanity checks that it is only enabled on GIC revisions that support it. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-3-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-5-git-send-email-greg.bellows@linaro.org [PMM: changed property name, added checks that it isn't set for older GIC revisions or if using the KVM VGIC; reworded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Create outbound FIQ linesFabian Aggeler
Create the outbound FIQ lines from the GIC to the CPUs; these are used if the GIC has security extensions or grouping support. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-2-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-2-git-send-email-greg.bellows@linaro.org [PMM: added FIQ lines to kvm-arm-gic so its interface is the same; tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Mon May 11 16:25:58 2015 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/net-pull-request: rocker: timestamp on the debug logs helps correlate with events in the VM MAINTAINERS: add rocker rocker: add tests rocker: add new rocker switch device pci: add network device class 'other' for network switches pci: add rocker device ID rocker: add register programming guide virtio-net: use qemu_mac_strdup_printf net: add MAC address string printer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12Merge remote-tracking branch 'remotes/qmp-unstable/tags/for-upstream' into ↵Peter Maydell
staging QMP pull request # gpg: Signature made Mon May 11 14:15:19 2015 BST using RSA key ID E24ED5A7 # gpg: Good signature from "Luiz Capitulino <lcapitulino@gmail.com>" * remotes/qmp-unstable/tags/for-upstream: scripts: qmp-shell: Add verbose flag scripts: qmp-shell: add transaction subshell scripts: qmp-shell: Expand support for QMP expressions scripts: qmp-shell: refactor helpers MAINTAINERS: New maintainer for QMP and QAPI json-parser: Accept 'null' in QMP qobject: Add a special null QObject qobject: Clean up around qtype_code QJSON: Use OBJECT_CHECK Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-11Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
pc, virtio enhancements Memory hot-unplug support for pc, MSI-X mapping update speedup for virtio-pci, misc refactorings and bugfixes. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon May 11 08:23:43 2015 BST using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" * remotes/mst/tags/for_upstream: (28 commits) acpi: update expected files for memory unplug virtio-scsi: Move DEFINE_VIRTIO_SCSI_FEATURES to virtio-scsi virtio-net: Move DEFINE_VIRTIO_NET_FEATURES to virtio-net pci: Merge pci_nic_init() into pci_nic_init_nofail() acpi: add a missing backslash to the \_SB scope. qmp-event: add event notification for memory hot unplug error acpi: add hardware implementation for memory hot unplug acpi: fix "Memory device control fields" register acpi: extend aml_field() to support UpdateRule acpi, mem-hotplug: add unplug cb for memory device acpi, mem-hotplug: add unplug request cb for memory device acpi, mem-hotplug: add acpi_memory_slot_status() to get MemStatus docs: update documentation for memory hot unplug virtio: coding style tweak pci: remove hard-coded bar size in msix_init_exclusive_bar() virtio-pci: speedup MSI-X masking and unmasking virtio: introduce vector to virtqueues mapping virtio-ccw: using VIRTIO_NO_VECTOR instead of 0 for invalid virtqueue monitor: check return value of qemu_find_net_clients_except() monitor: replace the magic number 255 with MAX_QUEUE_NUM ... Conflicts: hw/s390x/s390-virtio-bus.c [PMM: fixed conflict in s390_virtio_scsi_properties and s390_virtio_net_properties arrays; since the result of the two conflicting patches is to empty the property arrays completely, the conflict resolution is to remove them entirely.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-11pci: add network device class 'other' for network switchesScott Feldman
Rocker is an ethernet switch device, so add 'other' network device class as defined by PCI to cover these types of devices. Signed-off-by: Scott Feldman <sfeldma@gmail.com> Signed-off-by: Jiri Pirko <jiri@resnulli.us> Message-id: 1426306173-24884-6-git-send-email-sfeldma@gmail.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-05-11pci: add rocker device IDScott Feldman
Signed-off-by: Scott Feldman <sfeldma@gmail.com> Signed-off-by: Jiri Pirko <jiri@resnulli.us> Message-id: 1426306173-24884-5-git-send-email-sfeldma@gmail.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-05-11net: add MAC address string printerScott Feldman
We can use this in virtio-net code as well as new Rocker driver code, so up-level this. Signed-off-by: Scott Feldman <sfeldma@gmail.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 1426306173-24884-2-git-send-email-sfeldma@gmail.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-05-11qobject: Add a special null QObjectMarkus Armbruster
I'm going to fix the JSON parser to recognize null. The obvious representation of JSON null as (QObject *)NULL doesn't work, because the parser already uses it as an error value. Perhaps we should change it to free NULL for null, but that's more than I can do right now. Create a special null QObject instead. The existing QDict, QList, and QString all represent something that is a pointer in C and could therefore be associated with NULL. But right now, all three of these sub-types are always non-null once created, so the new null sentinel object is intentionally unrelated to them. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com> Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
2015-05-11qobject: Clean up around qtype_codeMarkus Armbruster
QTYPE_NONE is a sentinel value. No QObject has this type code. Document it properly. Fix dump_qobject() to abort() on QTYPE_NONE, just like for any other invalid type code. Fix to_json() to abort() on all invalid type codes, not just QTYPE_MAX. Clean up Property member qtype's type: it's a qtype_code. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
2015-05-11Merge remote-tracking branch ↵Peter Maydell
'remotes/mjt/tags/pull-trivial-patches-2015-05-09' into staging trivial patches for 2015-05-09 # gpg: Signature made Fri May 8 22:58:42 2015 BST using RSA key ID A4C3D7DB # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" * remotes/mjt/tags/pull-trivial-patches-2015-05-09: docs: update BLOCK_IMAGE_CORRUPTED documentation glib-compat.h: change assert to g_assert Remove various unused functions sheepdog: fix resource leak with sd_snapshot_create xhci: remove unused code Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-11Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
- build bugfix from Fam and new configure check from Emilio - two improvements to "info mtere" from Gerd - KVM support for memory transaction attributes - one more small step towards unlocked MMIO dispatch - one piece of the qemu-nbd errno fixes - trivial-ish patches from Denis and Thomas # gpg: Signature made Fri May 8 13:47:29 2015 BST using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: qemu-nbd: only send a limited number of errno codes on the wire rules.mak: Force CFLAGS for all objects in DSO configure: require __thread support exec: move rcu_read_lock/unlock to address_space_translate callers kvm: add support for memory transaction attributes mtree: also print disabled regions mtree: tag & indent a bit better apic_common: improve readability of apic_reset_common kvm: Silence warning from valgrind Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-11Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-20150508-1' into ↵Peter Maydell
staging gtk: add ui_info support, cleanups + fixes. # gpg: Signature made Fri May 8 12:47:04 2015 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-gtk-20150508-1: gtk: update mouse position in mouse_set() gtk: create gtk.h gtk: add ui_info support console: add dpy_ui_info_supported console: delayed ui_info guest notification Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-08glib-compat.h: change assert to g_assertMichael Tokarev
include/glib-compat.h defines a bunch of functions based on glib primitives, and uses assert() without including assert.h. Replace assert() with g_assert() to make the file more self-contained, and to fix compilation breakage after 28507a415a9b1e. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2015-05-08Remove various unused functionsThomas Huth
The functions tpm_backend_thread_tpm_reset() and iothread_find() are completely unused, let's remove them. Signed-off-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-05-07migration: Use an array instead of 3 parametersLiang Li
Put the three parameters related to multiple thread (de)compression into an int array, and use an enum type to index the parameter. Signed-off-by: Liang Li <liang.z.li@intel.com> Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2015-05-06qemu-file: Add compression functions to QEMUFileLiang Li
qemu_put_compression_data() compress the data and put it to QEMUFile. qemu_put_qemu_file() put the data in the buffer of source QEMUFile to destination QEMUFile. Signed-off-by: Liang Li <liang.z.li@intel.com> Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2015-05-06migration: Add the framework of multi-thread decompressionLiang Li
Add the code to create and destroy the multiple threads those will be used to do data decompression. Left some functions empty just to keep clearness, and the code will be added later. Signed-off-by: Liang Li <liang.z.li@intel.com> Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> Reviewed-by: Dr.David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2015-05-06migration: Add the framework of multi-thread compressionLiang Li
Add the code to create and destroy the multiple threads those will be used to do data compression. Left some functions empty to keep clearness, and the code will be added later. Signed-off-by: Liang Li <liang.z.li@intel.com> Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> Reviewed-by: Dr.David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2015-05-06gtk: create gtk.hGerd Hoffmann
Move various gtk bits (includes, data structures) to a header file. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-05-06console: add dpy_ui_info_supportedGerd Hoffmann
Allow ui code to check whenever the emulated display supports display change notifications. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-05-05sdl2: Fix RGB555Max Reitz
Reproducable with: $ x86_64-softmmu/qemu-system-x86_64 \ -kernel $vmlinuz_of_your_choice \ -append vga=0x313 -sdl Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-01 16:30:35 +0000