aboutsummaryrefslogtreecommitdiff
path: root/include
AgeCommit message (Collapse)Author
2018-03-05Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Mon 05 Mar 2018 03:06:59 GMT # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: tap: setting error appropriately when calling net_init_tap_one() hw/net: Remove unnecessary header includes net: Add a new convenience option "--nic" to configure default/on-board NICs net: Remove the deprecated 'host_net_add' and 'host_net_remove' HMP commands net: Remove the deprecated way of dumping network packets net: Make net_client_init() static net: Only show vhost-user in the help text if CONFIG_POSIX is defined net: List available netdevs with "-netdev help" net: Move error reporting from net_init_client/netdev to the calling site Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-05Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Sun 04 Mar 2018 17:32:25 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: target/m68k: add fscale, fgetman and fgetexp softfloat: use floatx80_infinity in softfloat target/m68k: add fmod/frem softfloat: export some functions target/m68k: TCGv returned by gen_load() must be freed Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-05Merge remote-tracking branch 'remotes/ericb/tags/pull-qapi-2018-03-01-v4' ↵Peter Maydell
into staging qapi patches for 2018-03-01 - Markus Armbruster: Modularize generated QAPI code # gpg: Signature made Fri 02 Mar 2018 19:50:16 GMT # gpg: using RSA key A7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-qapi-2018-03-01-v4: (30 commits) qapi: Don't create useless directory qapi-generated Fix up dangling references to qmp-commands.* in comment and doc qapi: Move qapi-schema.json to qapi/, rename generated files docs: Correct outdated information on QAPI docs/devel/writing-qmp-commands: Update for modular QAPI qapi: Empty out qapi-schema.json Include less of the generated modular QAPI headers qapi: Generate separate .h, .c for each module watchdog: Consolidate QAPI into single file qapi/common: Fix guardname() for funny filenames qapi/types qapi/visit: Generate built-in stuff into separate files qapi: Make code-generating visitors use QAPIGen more qapi: Rename generated qmp-marshal.c to qmp-commands.c qapi: Record 'include' directives in intermediate representation qapi: Generate in source order qapi: Record 'include' directives in parse tree qapi: Concentrate QAPISchemaParser.exprs updates in .__init__() qapi: Lift error reporting from QAPISchema.__init__() to callers qapi/common: Eliminate QAPISchema.exprs qapi: Improve include file name reporting in error messages ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-05tap: setting error appropriately when calling net_init_tap_one()Jay Zhou
If netdev_add tap,id=net0,...,vhost=on failed in net_init_tap_one(), the followed up device_add virtio-net-pci,netdev=net0 will fail too, prints: TUNSETOFFLOAD ioctl() failed: Bad file descriptor TUNSETOFFLOAD ioctl() failed: Bad file descriptor The reason is that the fd of tap is closed when error occured after calling net_init_tap_one(). The fd should be closed when calling net_init_tap_one failed: - if tap_set_sndbuf() failed - if tap_set_sndbuf() succeeded but vhost failed to open or initialize with vhostforce flag on - with wrong vhost command line parameter The fd should not be closed just because vhost failed to open or initialize but without vhostforce flag. So the followed up device_add can fall back to userspace virtio successfully. Suggested-by: Michael S. Tsirkin <mst@redhat.com> Suggested-by: Igor Mammedov <imammedo@redhat.com> Suggested-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2018-03-05net: Add a new convenience option "--nic" to configure default/on-board NICsThomas Huth
The legacy "-net" option can be quite confusing for the users since most people do not expect to get a "vlan" hub between their emulated guest hardware and the host backend. But so far, we are also not able to get rid of "-net" completely, since it is the only way to configure on-board NICs that can not be instantiated via "-device" yet. It's also a little bit shorter to type "-net nic -net tap" instead of "-device xyz,netdev=n1 -netdev tap,id=n1". So what we need is a new convenience option that is shorter to type than the full -device + -netdev stuff, and which can be used to configure the on-board NICs that can not be handled via -device yet. Thus this patch now provides such a new option "--nic": It adds an entry in the nd_table to configure a on-board / default NIC, creates a host backend and connects the two directly, without a confusing "vlan" hub inbetween. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2018-03-05net: Make net_client_init() staticThomas Huth
The function is only used within net.c, so there's no need that this is a global function. While we're at it, also remove the unused prototype compute_mcast_idx() (the function has been removed in commit d9caeb09b107e91122d10ba4a08a). Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2018-03-05net: Move error reporting from net_init_client/netdev to the calling siteThomas Huth
It looks strange that net_init_client() and net_init_netdev() both take an "Error **errp" parameter, but then do the error reporting with "error_report_err(local_err)" on their own. Let's move the error reporting to the calling site instead to simplify this code a little bit. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2018-03-04softfloat: use floatx80_infinity in softfloatLaurent Vivier
Since f3218a8 ("softfloat: add floatx80 constants") floatx80_infinity is defined but never used. This patch updates floatx80 functions to use this definition. This allows to define a different default Infinity value on m68k: the m68k FPU defines infinity with all bits set to zero in the mantissa. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-4-laurent@vivier.eu>
2018-03-04softfloat: export some functionsLaurent Vivier
Move fpu/softfloat-macros.h to include/fpu/ Export floatx80 functions to be used by target floatx80 specific implementations. Exports: propagateFloatx80NaN(), extractFloatx80Frac(), extractFloatx80Exp(), extractFloatx80Sign(), normalizeFloatx80Subnormal(), packFloatx80(), roundAndPackFloatx80(), normalizeRoundAndPackFloatx80() Also exports packFloat32() that will be used to implement m68k fsinh, fcos, fsin, ftan operations. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-2-laurent@vivier.eu>
2018-03-02qapi: Move qapi-schema.json to qapi/, rename generated filesMarkus Armbruster
Move qapi-schema.json to qapi/, so it's next to its modules, and all files get generated to qapi/, not just the ones generated for modules. Consistently name the generated files qapi-MODULE.EXT: qmp-commands.[ch] become qapi-commands.[ch], qapi-event.[ch] become qapi-events.[ch], and qmp-introspect.[ch] become qapi-introspect.[ch]. This gets rid of the temporary hacks in scripts/qapi/commands.py, scripts/qapi/events.py, and scripts/qapi/common.py. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180211093607.27351-28-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> [eblake: Fix trailing dot in tpm.c, undo temporary hack for OSX toolchain] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-03-02qapi: Empty out qapi-schema.jsonMarkus Armbruster
The previous commit improved compile time by including less of the generated QAPI headers. This is impossible for stuff defined directly in qapi-schema.json, because that ends up in headers that that pull in everything. Move everything but include directives from qapi-schema.json to new sub-module qapi/misc.json, then include just the "misc" shard where possible. It's possible everywhere, except: * monitor.c needs qmp-command.h to get qmp_init_marshal() * monitor.c, ui/vnc.c and the generated qapi-event-FOO.c need qapi-event.h to get enum QAPIEvent Perhaps we'll get rid of those some other day. Adding a type to qapi/migration.json now recompiles some 120 instead of 2300 out of 5100 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180211093607.27351-25-armbru@redhat.com> [eblake: rebase to master] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-03-02Include less of the generated modular QAPI headersMarkus Armbruster
In my "build everything" tree, a change to the types in qapi-schema.json triggers a recompile of about 4800 out of 5100 objects. The previous commit split up qmp-commands.h, qmp-event.h, qmp-visit.h, qapi-types.h. Each of these headers still includes all its shards. Reduce compile time by including just the shards we actually need. To illustrate the benefits: adding a type to qapi/migration.json now recompiles some 2300 instead of 4800 objects. The next commit will improve it further. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180211093607.27351-24-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> [eblake: rebase to master] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-03-02net: fix misaligned member accessMarc-André Lureau
Fixes the following ASAN warnings: /home/elmarco/src/qemu/hw/net/net_tx_pkt.c:201:27: runtime error: member access within misaligned address 0x631000028846 for type 'struct ip_header', which requires 4 byte alignment 0x631000028846: note: pointer points here 01 00 00 00 45 00 01 a9 01 00 00 00 40 11 78 45 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 ^ /home/elmarco/src/qemu/hw/net/net_tx_pkt.c:208:63: runtime error: member access within misaligned address 0x631000028846 for type 'struct ip_header', which requires 4 byte alignment 0x631000028846: note: pointer points here 01 00 00 00 45 00 01 a9 01 00 00 00 40 11 78 45 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 ^ /home/elmarco/src/qemu/hw/net/net_tx_pkt.c:210:13: runtime error: member access within misaligned address 0x631000028846 for type 'struct ip_header', which requires 4 byte alignment 0x631000028846: note: pointer points here 01 00 00 00 45 00 01 a9 01 00 00 00 40 11 78 45 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180209190340.19516-1-marcandre.lureau@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180302' into staging target-arm queue: * implement FCMA and RDM v8.1 and v8.3 instructions * enable Cortex-M33 v8M core, and provide new mps2-an505 board model that uses it * decodetree: Propagate return value from translate subroutines * xlnx-zynqmp: Implement the RTC device # gpg: Signature made Fri 02 Mar 2018 11:05:40 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180302: (39 commits) target/arm: Enable ARM_FEATURE_V8_FCMA target/arm: Decode t32 simd 3reg and 2reg_scalar extension target/arm: Decode aa32 armv8.3 2-reg-index target/arm: Decode aa32 armv8.3 3-same target/arm: Decode aa64 armv8.3 fcmla target/arm: Decode aa64 armv8.3 fcadd target/arm: Add ARM_FEATURE_V8_FCMA target/arm: Enable ARM_FEATURE_V8_RDM target/arm: Decode aa32 armv8.1 two reg and a scalar target/arm: Decode aa32 armv8.1 three same target/arm: Decode aa64 armv8.1 scalar/vector x indexed element target/arm: Decode aa64 armv8.1 three same extra target/arm: Decode aa64 armv8.1 scalar three same extra target/arm: Refactor disas_simd_indexed size checks target/arm: Refactor disas_simd_indexed decode target/arm: Add ARM_FEATURE_V8_RDM mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image hw/arm/iotkit: Model Arm IOT Kit hw/misc/iotkit-secctl: Add remaining simple registers hw/misc/iotkit-secctl: Add handling for PPCs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-03-01' into ↵Peter Maydell
staging nbd patches for 2018-03-01 - Eric Blake: nbd: Honor server's advertised minimum block size - Vladimir Sementsov-Ogievskiy: partial: nbd block status base:allocation # gpg: Signature made Thu 01 Mar 2018 21:01:22 GMT # gpg: using RSA key A7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2018-03-01: nbd/client: fix error messages in nbd_handle_reply_err nbd: BLOCK_STATUS constants nbd: change indenting in nbd.h nbd: Honor server's advertised minimum block size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02hw/arm/iotkit: Model Arm IOT KitPeter Maydell
Model the Arm IoT Kit documented in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html The Arm IoT Kit is a subsystem which includes a CPU and some devices, and is intended be extended by adding extra devices to form a complete system. It is used in the MPS2 board's AN505 image for the Cortex-M33. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-19-peter.maydell@linaro.org
2018-03-02hw/misc/iotkit-secctl: Add remaining simple registersPeter Maydell
Add remaining easy registers to iotkit-secctl: * NSCCFG just routes its two bits out to external GPIO lines * BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's bus fabric can never report errors Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180220180325.29818-18-peter.maydell@linaro.org
2018-03-02hw/misc/iotkit-secctl: Add handling for PPCsPeter Maydell
The IoTKit Security Controller includes various registers that expose to software the controls for the Peripheral Protection Controllers in the system. Implement these. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-17-peter.maydell@linaro.org
2018-03-02hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeletonPeter Maydell
The Arm IoT Kit includes a "security controller" which is largely a collection of registers for controlling the PPCs and other bits of glue in the system. This commit provides the initial skeleton of the device, implementing just the ID registers, and a couple of read-only read-as-zero registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-16-peter.maydell@linaro.org
2018-03-02hw/misc/tz-ppc: Model TrustZone peripheral protection controllerPeter Maydell
Add a model of the TrustZone peripheral protection controller (PPC), which is used to gate transactions to non-TZ-aware peripherals so that secure software can configure them to not be accessible to non-secure software. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-15-peter.maydell@linaro.org
2018-03-02hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505Peter Maydell
The MPS2 AN505 FPGA image includes a "FPGA control block" which is a small set of registers handling LEDs, buttons and some counters. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-14-peter.maydell@linaro.org
2018-03-02hw/core/split-irq: Device that splits IRQ linesPeter Maydell
In some board or SoC models it is necessary to split a qemu_irq line so that one input can feed multiple outputs. We currently have qemu_irq_split() for this, but that has several deficiencies: * it can only handle splitting a line into two * it unavoidably leaks memory, so it can't be used in a device that can be deleted Implement a qdev device that encapsulates splitting of IRQs, with a configurable number of outputs. (This is in some ways the inverse of the TYPE_OR_IRQ device.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-13-peter.maydell@linaro.org
2018-03-02qdev: Add new qdev_init_gpio_in_named_with_opaque()Peter Maydell
The function qdev_init_gpio_in_named() passes the DeviceState pointer as the opaque data pointor for the irq handler function. Usually this is what you want, but in some cases it would be helpful to use some other data pointer. Add a new function qdev_init_gpio_in_named_with_opaque() which allows the caller to specify the data pointer they want. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-12-peter.maydell@linaro.org
2018-03-02include/hw/or-irq.h: Add missing include guardPeter Maydell
The or-irq.h header file is missing the customary guard against multiple inclusion, which means compilation fails if it gets included twice. Fix the omission. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-11-peter.maydell@linaro.org
2018-03-02hw/misc/unimp: Move struct to header filePeter Maydell
Move the definition of the struct for the unimplemented-device from unimp.c to unimp.h, so that users can embed the struct in their own device structs if they prefer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-10-peter.maydell@linaro.org
2018-03-02armv7m: Forward init-svtor property to CPU objectPeter Maydell
Create an "init-svtor" property on the armv7m container object which we can forward to the CPU object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-8-peter.maydell@linaro.org
2018-03-02armv7m: Forward idau property to CPU objectPeter Maydell
Create an "idau" property on the armv7m container object which we can forward to the CPU object. Annoyingly, we can't use object_property_add_alias() because the CPU object we want to forward to doesn't exist until the armv7m container is realized. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-6-peter.maydell@linaro.org
2018-03-02loader: Add new load_ramdisk_as()Peter Maydell
Add a function load_ramdisk_as() which behaves like the existing load_ramdisk() but allows the caller to specify the AddressSpace to use. This matches the pattern we have already for various other loader functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-2-peter.maydell@linaro.org
2018-03-02xlnx-zynqmp: Connect the RTC deviceAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02xlnx-zynqmp-rtc: Add basic time supportAlistair Francis
Allow the guest to determine the time set from the QEMU command line. This includes adding a trace event to debug the new time. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02xlnx-zynqmp-rtc: Initial commitAlistair Francis
Initial commit of the ZynqMP RTC device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01nbd: BLOCK_STATUS constantsVladimir Sementsov-Ogievskiy
Expose the new constants and structs that will be used by both server and client implementations of NBD_CMD_BLOCK_STATUS (the command is currently experimental at https://github.com/NetworkBlockDevice/nbd/blob/extension-blockstatus/doc/proto.md but will hopefully be stabilized soon). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <1518702707-7077-4-git-send-email-vsementsov@virtuozzo.com> [eblake: split from larger patch on server implementation] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-03-01nbd: change indenting in nbd.hVladimir Sementsov-Ogievskiy
Prepared indenting for the following patch. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <1518702707-7077-3-git-send-email-vsementsov@virtuozzo.com> Signed-off-by: Eric Blake <eblake@redhat.com>
2018-03-01Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio,vhost,pci,pc: features, fixes and cleanups - documentation updates - vhost fixes - new crypto vhost device Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Thu 01 Mar 2018 16:27:25 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: cryptodev-vhost-user: set the key length cryptodev-vhost-user: add crypto session handler cryptodev: add vhost support cryptodev: add vhost-user as a new cryptodev backend docs/vmcoreinfo: detail unsupported host format behaviour vhost: fix incorrect check in vhost_verify_ring_mappings vhost: avoid to start/stop virtqueue which is not ready vhost: fix memslot limit check docs: pcie: Spell out machine type needs for PCIe features docs: document virtio-balloon stats intel-iommu: Accept 64-bit writes to FEADDR virtio-pci: trivial fixes in error message vhost-user: fix memory leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180301-v2' into ↵Peter Maydell
staging - add query-cpus-fast and deprecate query-cpus, while adding s390 cpu information - remove s390x memory hotplug implementation, which is not useable in this form - add boot menu support in the s390-ccw bios - expose s390x guest crash information - fixes and cleaups # gpg: Signature made Thu 01 Mar 2018 12:54:47 GMT # gpg: using RSA key DECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20180301-v2: (27 commits) s390x/tcg: fix loading 31bit PSWs with the highest bit set s390x: remove s390_get_memslot_count s390x/sclp: remove memory hotplug support s390x/cpumodel: document S390FeatDef.bit not applicable hmp: change hmp_info_cpus to use query-cpus-fast qemu-doc: deprecate query-cpus qmp: add architecture specific cpu data for query-cpus-fast qmp: add query-cpus-fast qmp: expose s390-specific CPU info s390x/tcg: add various alignment checks s390x/tcg: fix disabling/enabling DAT s390/stattrib: Make SaveVMHandlers data static s390x/cpu: expose the guest crash information pc-bios/s390: Rebuild the s390x firmware images with the boot menu changes s390-ccw: interactive boot menu for scsi s390-ccw: use zipl values when no boot menu options are present s390-ccw: set cp_receive mask only when needed and consume pending service irqs s390-ccw: read user input for boot index via the SCLP console s390-ccw: print zipl boot menu s390-ccw: read stage2 boot loader data to find menu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01cryptodev-vhost-user: set the key lengthGonglei
Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01cryptodev-vhost-user: add crypto session handlerGonglei
Introduce two vhost-user meassges: VHOST_USER_CREATE_CRYPTO_SESSION and VHOST_USER_CLOSE_CRYPTO_SESSION. At this point, the QEMU side support crypto operation in cryptodev host-user backend. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01cryptodev: add vhost supportGonglei
Impliment the vhost-crypto's funtions, such as startup, stop and notification etc. Introduce an enum QCryptoCryptoDevBackendOptionsType in order to identify the cryptodev vhost backend is vhost-user or vhost-kernel-module (If exist). At this point, the cryptdoev-vhost-user works. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01cryptodev: add vhost-user as a new cryptodev backendGonglei
Usage: -chardev socket,id=charcrypto0,path=/path/to/your/socket -object cryptodev-vhost-user,id=cryptodev0,chardev=charcrypto0 -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180301' into staging target-arm queue: * update MAINTAINERS for Alistair's new email address * add Arm v8.2 FP16 arithmetic extension for linux-user * implement display connector emulation for vexpress board * xilinx_spips: Enable only two slaves when reading/writing with stripe * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands * hw: register: Run post_write hook on reset # gpg: Signature made Thu 01 Mar 2018 11:22:46 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180301: (42 commits) MAINTAINERS: Update my email address linux-user: Report AArch64 FP16 support via hwcap bits target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU arm/translate-a64: add all single op FP16 to handle_fp_1src_half arm/translate-a64: implement simd_scalar_three_reg_same_fp16 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise arm/translate-a64: add FP16 FMOV to simd_mod_imm arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 arm/helper.c: re-factor rsqrte and add rsqrte_f16 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FRECPE arm/helper.c: re-factor recpe and add recepe_f16 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 arm/translate-a64: initial decode for simd_two_reg_misc_fp16 arm/translate-a64: add FP16 x2 ops for simd_indexed ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée
As some of the constants here will also be needed elsewhere (specifically for the upcoming SVE support) we move them out to softfloat.h. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-13-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01include/exec/helper-head.h: support f16 in helper callsAlex Bennée
This allows us to explicitly pass float16 to helpers rather than assuming uint32_t and dealing with the result. Of course they will be passed in i32 sized registers by default. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01i2c: Move the bus class to i2c.hCorey Minyard
Some devices need access to it. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Message-id: 20180227104903.21353-3-linus.walleij@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01i2c: Fix some brace style issuesCorey Minyard
Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Message-id: 20180227104903.21353-2-linus.walleij@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01hw: register: Run post_write hook on resetAlistair Francis
Ensure that the post write hook is called during reset. This allows us to rely on the post write functions instead of having to call them from the reset() function. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: d131e24b911653a945e46ca2d8f90f572469e1dd.1517856214.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01Merge remote-tracking branch ↵Peter Maydell
'remotes/stefanberger/tags/pull-tpm-2018-02-21-2' into staging Merge tpm 2018/02/21 v2 # gpg: Signature made Tue 27 Feb 2018 13:50:28 GMT # gpg: using RSA key 75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * remotes/stefanberger/tags/pull-tpm-2018-02-21-2: tests: add test for TPM TIS device tests: Move common TPM test code into tpm-emu.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-27Merge remote-tracking branch 'remotes/kraxel/tags/vga-20180227-pull-request' ↵Peter Maydell
into staging virtio-gpu: add support for second capability set # gpg: Signature made Tue 27 Feb 2018 07:30:31 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20180227-pull-request: virtio-gpu-3d: add support for second capability set (v4) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-26virtio-gpu-3d: add support for second capability set (v4)Dave Airlie
Due to a kernel bug we can never increase the size of capability set 1, so introduce a new capability set in parallel, old userspace will continue to use the old set, new userspace will start using the new one when it detects a fixed kernel. v2: don't use a define from virglrenderer, just probe it. v3: fix compilation when virglrenderer disabled v4: fix style warning, just use ?: op instead. Signed-off-by: Dave Airlie <airlied@redhat.com> Message-id: 20180223023814.24459-1-airlied@gmail.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-02-26s390x: remove s390_get_memslot_countCornelia Huck
Not needed anymore after removal of the memory hotplug code. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-26s390x/sclp: remove memory hotplug supportDavid Hildenbrand
From an architecture point of view, nothing can be mapped into the address space on s390x. All there is is memory. Therefore there is also not really an interface to communicate such information to the guest. All we can do is specify the maximum ram address and guests can probe in that range if memory is available and usable (TPROT). Also memory hotplug is strange. The guest can decide at some point in time to add / remove memory in some range. While the hypervisor can deny to online an increment, all increments have to be predefined and there is no way of telling the guest about a newly "hotplugged" increment. So if we specify right now e.g. -m 2G,slots=2,maxmem=20G An ordinary fedora guest will happily online (hotplug) all memory, resulting in a guest consuming 20G. So it really behaves rather like -m 22G There is no way to hotplug memory from the outside like on other architectures. This is of course bad for upper management layers. As the guest can create/delete memory regions while it is running, of course migration support is not available and tricky to implement. With virtualization, it is different. We might want to map something into guest address space (e.g. fake DAX devices) and not detect it automatically as memory. So we really want to use the maxmem and slots parameter just like on all other architectures. Such devices will have to expose the applicable memory range themselves. To finally be able to provide memory hotplug to guests, we will need a new paravirtualized interface to do that (e.g. something into the direction of virtio-mem). This implies, that maxmem cannot be used for s390x memory hotplug anymore and has to go. This simplifies the code quite a bit. As migration support is not working, this change cannot really break migration as guests without slots and maxmem don't see the SCLP features. Also, the ram size calculation does not change. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180219174231.10874-1-david@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> [CH: tweaked patch description, as discussed on list] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-30 18:36:21 +0000