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2016-06-29ich9: implement SCI_IRQ_SEL registerPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29serial: remove watch on resetPaolo Bonzini
Otherwise, this can cause serial_xmit to be entered with LSR.TEMT=0, which is invalid and causes an assertion failure. Reported-by: Bret Ketchum <bcketchum@gmail.com> Tested-by: Bret Ketchum <bcketchum@gmail.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29char: change qemu_chr_fe_add_watch to return unsignedPaolo Bonzini
g_source_attach can return any value between 1 and UINT_MAX if you let QEMU run long enough. However, qemu_chr_fe_add_watch can also return a negative errno value when the device is disconnected or does not support chr_add_watch. Change it to return zero to avoid overloading these values. Fix the cadence_uart which asserts in this case (easily obtained with "-serial pty"). Tested-by: Bret Ketchum <bcketchum@gmail.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29serial: make tsr_retry unsignedPaolo Bonzini
It can never become negative; reflect this in the type of the field and simplify the conditions. Tested-by: Bret Ketchum <bcketchum@gmail.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29target-*: Don't redefine cpu_exec()Peter Crosthwaite
This function needs to be converted to QOM hook and virtualised for multi-arch. This rename interferes, as cpu-qom will not have access to the renaming causing name divergence. This rename doesn't really do anything anyway so just delete it. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-Id: <69bd25a8678b8b31b91cd9760c777bed1aafb44e.1437212383.git.crosthwaite.peter@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaitepeter@gmail.com>
2016-06-29vnc: generalize "VNC server running on ..." messagePaolo Bonzini
The message is useful whenever the user specifies "-vnc to=XX". Move it to ui/vnc.c. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29scsi: esp: fix migrationPaolo Bonzini
Commit 926cde5 ("scsi: esp: make cmdbuf big enough for maximum CDB size", 2016-06-16) changed the size of a migrated field. Split it in two parts, and only migrate the second part in a new vmstate version. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29isa: introduce wrapper isa_connect_gpio_outEfimov Vasily
Currently a direct access to the device structure field is used to connect ISA device IRQ to the bus. GPIO access should be used instead if possible. The patch adds wrapper isa_connect_gpio_out. The function connects specified output GPIO to specified ISA IRQ. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29ICH9 LPC: handle GSI as qdev GPIOEfimov Vasily
The ICH9 LPC bridge has 24 output IRQs connected to GSI. Currently the IRQs are referenced by pointers. The pointers are initialized at startup by direct access to the structure fields. This violates Qemu device model. The patch makes the IRQs handling to use GPIO model. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29ich9: unify pic and ioapic IRQ vectorsPaolo Bonzini
ich9->pic and ich9->ioapic differ for the first 16 GSIs (because ich9->pic is wired to 8259+IOAPIC but ich9->ioapic is wired to IOAPIC only). However, ich9->ioapic is never used for the first 16 GSIs, so the two vectors can be merged. Reviewed-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29ICH9 SMB: make TYPE_ICH9_SMB_DEVICE macro publicEfimov Vasily
ICH9 SMB bridge can be created using qdev API despite existence of helper function. The type name is needed for such creation. Using a preprocessor alias instead the string type name itself is preferable. The patch makes the alias accessible through the header. Signed-off-by: Efimov Vasily <real@ispras.ru> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29port92: handle A20 IRQ as GPIOEfimov Vasily
The port92 device has outgouing IRQ line A20. Currently the IRQ is referenced by a pointer which normally is set during machine initialization. The pointer is never changed at runtime. Hence, common GPIO model can be applied to A20 IRQ line. Note that checking for IRQ to be connected as in previous version of code is not required qemu_set_irq will do it. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29pckbd: handle A20 IRQ as GPIOEfimov Vasily
The i8042 device has outgouing IRQ line A20. Currently the IRQ is referenced by a pointer which normally is set during machine initialization. The pointer is never changed at runtime. So common GPIO model can be applied to A20 IRQ line. Note that checking for IRQ to be connected as in previous version of code is not required because qemu_set_irq will do it. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29Q35: implement property interfece to several parametersEfimov Vasily
During creation of Q35 instance several parameters are set using direct access. It violates Qemu device model. Correctly, the parameters should be handled as object properties. The patch adds four link type properties for fields: mch.ram_memory mch.pci_address_space mch.system_memory mch.address_space_io And, it adds two size type properties for fields: mch.below_4g_mem_size mch.above_4g_mem_size Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29pflash: make TYPE_CFI_PFLASH0{1,2} macros publicEfimov Vasily
qdev API can be used to create CFI pflash devices despite existance of helper functions. The type name is needed in course of such creation. Using the preprocessor alias instead of the string literal itself is preferable. The patch makes the aliases accessible through the header. Signed-off-by: Efimov Vasily <real@ispras.ru> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29vmport: identify vmport type by macro TYPE_VMPORTEfimov Vasily
Currently vmport device is identified by the string literal. Using a preprocessor alias instead is preferable. Signed-off-by: Efimov Vasily <real@ispras.ru> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29pcspk: convert "pit" property type from ptr to linkEfimov Vasily
The speaker device needs pointer to ISA PIT device to operate. But according to qdev-properties.h, properties of pointer type should be avoided. It seems a link type property is a good substitution. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29ide: move headers to include folderEfimov Vasily
The patch moves "hw/ide/achi.h", "hw/ide/pci.h" and "hw/ide/internal.h" headers to corresponding folders inside "include" folder alike other Qemu headers. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-28Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Tue 28 Jun 2016 14:23:24 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: virtio-blk: add num-queues device property virtio-blk: dataplane multiqueue support virtio-blk: live migrate s->rq with multiqueue virtio-blk: associate request with a virtqueue virtio-blk: tell dataplane which vq to notify virtio-blk: multiqueue batch notify virtio-blk: add VirtIOBlockConf->num_queues dma-helpers: dma_blk_io() cancel support Revert "virtio: sync the dataplane vring state to the virtqueue before virtio_save" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-28virtio-blk: add num-queues device propertyStefan Hajnoczi
Multiqueue virtio-blk can be enabled as follows: qemu -device virtio-blk-pci,num-queues=8 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1466511196-12612-8-git-send-email-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-28virtio-blk: associate request with a virtqueueStefan Hajnoczi
Multiqueue requires that each request knows to which virtqueue it belongs. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1466511196-12612-5-git-send-email-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-28virtio-blk: add VirtIOBlockConf->num_queuesStefan Hajnoczi
The num_queues field is always 1 for the time being. A later patch will make it a configurable device property so that multiqueue can be enabled. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1466511196-12612-2-git-send-email-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-28Change net/socket.c to use socket_*() functionsAshijeet Acharya
Use socket_*() functions from include/qemu/sockets.h instead of listen()/bind()/connect()/parse_host_port(). socket_*() fucntions are QAPI based and this patch performs this api conversion since everything will be using QAPI based sockets in the future. Also add a helper function socket_address_to_string() in util/qemu-sockets.c which returns the string representation of socket address. Thetask was listed on http://wiki.qemu.org/BiteSizedTasks page. Signed-off-by: Ashijeet Acharya <ashijeetacharya@gmail.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2016-06-27ast2400: Integrate the SCU model and set silicon revisionAndrew Jeffery
By specifying the silicon revision we select the appropriate reset values for the SoC. Additionally, expose hardware strapping properties aliasing those provided by the SCU for board-specific configuration. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1466744305-23163-3-git-send-email-andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27hw/misc: Add a model for the ASPEED System Control UnitAndrew Jeffery
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control interactions with clocks, external hardware or reset behaviour, and we can largly take a hands-off approach to reads and writes. Firmware makes heavy use of the state to determine how to boot, but the reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev property is exposed so that the integrating SoC model can configure the silicon revision, which in-turn selects the appropriate reset values. Further qdev properties are exposed so the board model can configure the board-dependent hardware strapping. Almost all provided AST2400 reset values are specified by the datasheet. The notable exception is SOC_SCRATCH1, where we mark the DRAM as successfully initialised to avoid unnecessary dark corners in the SoC's u-boot support. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1466744305-23163-2-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: drop unnecessary inttypes.h include] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160627' ↵Peter Maydell
into staging ppc patch queue for 2016-06-27 Small queue this time. Main reason for sending it is the pair of patches to fix up the new cpu hotplug model used on Power to what should be an actually usable state. There's also a small BookE bugfix and a XICS trivial cleanup. # gpg: Signature made Mon 27 Jun 2016 06:28:37 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160627: qapi: keep names in 'CpuInstanceProperties' in sync with struct CPUCore qapi: Report support for -device cpu hotplug in query-machines ppc/xics: Remove unused xics_set_irq_type() target-ppc: ppce500_spin.c uses SPR_PIR, should use SPR_BOOKE_PIR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160624' into stagingPeter Maydell
MIPS patches 2016-06-24 Changes: * support IEEE 754-2008 in MIPS CPUs # gpg: Signature made Fri 24 Jun 2016 16:09:38 BST # gpg: using RSA key 0x52118E3C0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20160624: target-mips: Add FCR31's FS bit definition target-mips: Implement FCR31's R/W bitmask and related functionalities target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D> target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA linux-user: Update preprocessor constants for Mips-specific e_flags bits softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd() softfloat: For Mips only, correct default NaN values softfloat: Clean code format in fpu/softfloat-specialize.h softfloat: Implement run-time-configurable meaning of signaling NaN bit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27qapi: keep names in 'CpuInstanceProperties' in sync with struct CPUCorePeter Krempa
struct CPUCore uses 'id' suffix in the property name. As docs for query-hotpluggable-cpus state that the cpu core properties should be passed back to device_add by management in case new members are added and thus the names for the fields should be kept in sync. Signed-off-by: Peter Krempa <pkrempa@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> [dwg: Removed a duplicated word in comment] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-27ppc/xics: Remove unused xics_set_irq_type()Benjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Adjusted for context to apply without original series] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-24linux-user: Update preprocessor constants for Mips-specific e_flags bitsAleksandar Markovic
Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic
This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In floating-point calculations, there is a need for denoting undefined or unrepresentable values. This is achieved by defining certain floating-point numerical values to be NaNs (which stands for "not a number"). For additional reasons, virtually all modern floating-point unit implementations use two kinds of NaNs: quiet and signaling. The binary representations of these two kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally, the first bit of mantissa). Up to 2008, standards for floating-point did not specify all details about binary representation of NaNs. More specifically, the meaning of the bit that is used for distinguishing between signaling and quiet NaNs was not strictly prescribed. (IEEE 754-2008 was the first floating-point standard that defined that meaning clearly, see [1], p. 35) As a result, different platforms took different approaches, and that presented considerable challenge for multi-platform emulators like QEMU. Mips platform represents the most complex case among QEMU-supported platforms regarding signaling NaN bit. Up to the Release 6 of Mips architecture, "1" in signaling NaN bit denoted signaling NaN, which is opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of that, Mips architecture for SIMD (also known as MSA, or vector instructions) also specifies signaling bit in accordance to IEEE standard. MSA unit can be implemented with both pre-Release 6 and Release 6 main processor units. QEMU uses SoftFloat library to implement various floating-point-related instructions on all platforms. The current QEMU implementation allows for defining meaning of signaling NaN bit during build time, and is implemented via preprocessor macro called SNAN_BIT_IS_ONE. On the other hand, the change in this patch enables SoftFloat library to be configured in run-time. This configuration is meant to occur during CPU initialization, at the moment when it is definitely known what desired behavior for particular CPU (or any additional FPUs) is. The change is implemented so that it is consistent with existing implementation of similar cases. This means that structure float_status is used for passing the information about desired signaling NaN bit on each invocation of SoftFloat functions. The additional field in float_status is called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE. IMPORTANT: This change is not meant to create any change in emulator behavior or functionality on any platform. It just provides the means for SoftFloat library to be used in a more flexible way - in other words, it will just prepare SoftFloat library for usage related to Mips platform and its specifics regarding signaling bit meaning, which is done in some of subsequent patches from this series. Further break down of changes: 1) Added field snan_bit_is_one to the structure float_status, and correspondent setter function set_snan_bit_is_one(). 2) Constants <float16|float32|float64|floatx80|float128>_default_nan (used both internally and externally) converted to functions <float16|float32|float64|floatx80|float128>_default_nan(float_status*). This is necessary since they are dependent on signaling bit meaning. At the same time, for the sake of code cleanup and simplicity, constants <floatx80|float128>_default_nan_<low|high> (used only internally within SoftFloat library) are removed, as not needed. 3) Added a float_status* argument to SoftFloat library functions XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_), XXX_maybe_silence_nan(XXX a_). This argument must be present in order to enable correct invocation of new version of functions XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128> here) 4) Updated code for all platforms to reflect changes in SoftFloat library. This change is twofolds: it includes modifications of SoftFloat library functions invocations, and an addition of invocation of function set_snan_bit_is_one() during CPU initialization, with arguments that are appropriate for each particular platform. It was established that all platforms zero their main CPU data structures, so snan_bit_is_one(0) in appropriate places is not added, as it is not needed. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, August 29, 2008. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * cherry-picked 2 chunks from patch #2 to fix compilation warnings] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24vmxnet3: add boot romGerd Hoffmann
Disable for old machine types as this is a guest visible change. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-06-24virtio-bus: remove old set_host_notifier callbackCornelia Huck
All users have been converted to the new ioevent callbacks. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24virtio-bus: common ioeventfd infrastructureCornelia Huck
Introduce a set of ioeventfd callbacks on the virtio-bus level that can be implemented by the individual transports. At the virtio-bus level, do common handling for host notifiers (which is actually most of it). Two things of note: - When setting the host notifier, we only switch from/to the generic ioeventfd handler. This fixes a latent bug where we had no ioeventfd assigned for a certain window. - We always iterate over all possible virtio queues, even though ccw (currently) has a lower limit. It does not really matter here. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: acpi: drop intermediate PCMachineState.node_cpuIgor Mammedov
PCMachineState.node_cpu was used for mapping APIC ID to numa node id as CPU entries in SRAT used to be built on sparse APIC ID bitmap (up to apic_id_limit). However since commit 5803fce pc: acpi: SRAT: create only valid processor lapic entries CPU entries in SRAT aren't build using apic bitmap but using 0..maxcpus index instead which is also used for creating numa_info[x].node_cpu map. So instead of doing useless intermediate conversion from 1. node by cpu index -> node by apic id i.e. numa_info[x].node_cpu -> PCMachineState.node_cpu 2. apic id -> srat entry PMX PCMachineState.node_cpu[apic id] -> PMX value use numa_info[x].node_cpu map directly like ARM does and do 1. numa_info[x].node_cpu -> PMX value using index in range 0..maxcpus and drop not necessary PCMachineState.node_cpu and related code. That also removes the last (not counting legacy hotplug) dependency of ACPI code on apic_id_limit and need to allocate huge sparse PCMachineState.node_cpu array in case of 32-bit APIC IDs. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: use new CPU hotplug interface since 2.7 machine typeIgor Mammedov
For compatibility reasons PC/Q35 will start with legacy CPU hotplug interface by default but with new CPU hotplug AML code since 2.7 machine type. That way legacy firmware that doesn't use QEMU generated ACPI tables will be able to continue using legacy CPU hotplug interface. While new machine type, with firmware supporting QEMU provided ACPI tables, will generate new CPU hotplug AML, which will switch to new CPU hotplug interface when guest OS executes its _INI method on ACPI tables loading. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: cpuhp: add cpu._OST handlingIgor Mammedov
it adds HW and AML parts for CPU_Device._OST method handling to allow OSPM reports status of hot-(un)plug operation. And extends QMP command query-acpi-ospm-status to report CPU's OST info along with already reported PC-DIMM devices. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: cpuhp: implement hot-remove parts of CPU hotplug interfaceIgor Mammedov
it adds hw registers needed for handling CPU hot-remove and corresponding AML methods to request and eject a CPU with necessary hotplug callbacks in pc,piix4,ich9 code. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: cpuhp: implement hot-add parts of CPU hotplug interfaceIgor Mammedov
it adds hw registers needed for handling CPU hot-add and corresponding AML methods to handle hot-add events on guest side. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: acpi: introduce AcpiDeviceIfClass.madt_cpu hookIgor Mammedov
Add madt_cpu callback to AcpiDeviceIfClass and use it for generating LAPIC MADT entries for CPUs. Later it will be used for generating x2APIC entries in case of more than 255 CPUs and also would be reused by ARM target when ACPI CPU hotplug is introduced there. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: cpuhp: add CPU devices AML with _STA methodIgor Mammedov
it adds CPU objects to DSDT with _STA method and QEMU side of CPU hotplug interface initialization with registers sufficient to handle _STA requests, including necessary hotplug callbacks in piix4,ich9 code. Hot-(un)plug hw/acpi parts will be added by corresponding follow up patches. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: piix4/ich9: add 'cpu-hotplug-legacy' propertyIgor Mammedov
It will be used to select which hotplug call-back is called and for switching from legacy mode into new one. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: add aml_call5Xiao Guangrong
It will be used by NVDIMM ACPI Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: add aml_object_typeXiao Guangrong
Implement ObjectType which is used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24nvdimm: support nvdimm labelXiao Guangrong
Introduce a parameter, 'label-size', which is the size of nvdimm label data area which is reserved at the end of backend memory. It is required at least 128k Two callbacks, read_label_data() and write_label_data(), are used to operate the label area Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc-dimm: introduce get_vmstate_memory_region callbackXiao Guangrong
This callback returns the MemoryRegion that is the memory of dimm should be kept during live migration nvdimm device is different with pc-dimm as its memory includes not only the MemoryRegion directly mapping to guest's address space but also the memory used as label data Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: Add IPMI table entriesCorey Minyard
Use the ACPI table construction tools to create an ACPI entry for IPMI. This adds a function called build_acpi_ipmi_devices to add an DSDT entry for IPMI if IPMI is compiled in and an IPMI device exists. It also adds a dummy function if IPMI is not compiled in. This conforms to section "C3-2 Locating IPMI System Interfaces in ACPI Name Space" in the IPMI 2.0 specification. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24ipmi: Add SMBIOS table entryCorey Minyard
Add an IPMI table entry to the SMBIOS. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-23Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160623' ↵Peter Maydell
into staging ppc patch queue for 2016-06-23 Currently outstanding patches for spapr, target-ppc and related devices. This batch has: * Significant new progress towards full support for hypervisor mode * Assorted bugfixes * Some preliminary patches towards dynamic DMA window support The last involves a change to memory.c, which Paolo has said I can take through this tree. # gpg: Signature made Thu 23 Jun 2016 06:47:53 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160623: ppc: Disable huge page support if it is not available for main RAM ppc: Add P7/P8 Power Management instructions ppc: Move exception generation code out of line ppc: Turn a bunch of booleans from int to bool ppc: Add real mode CI load/store instructions for P7 and P8 ppc: Rework generation of priv and inval interrupts ppc: Fix generation if ISI/DSI vs. HV mode ppc: Fix POWER7 and POWER8 exception definitions ppc: fix exception model for HV mode ppc: define a default LPCR value ppc: Fix rfi/rfid/hrfi/... emulation memory: Add reporting of supported page sizes ppc: Improve emulation of THRM registers target-ppc: Fix rlwimi, rlwinm, rlwnm again ppc64: disable gen_pause() for linux-user mode tests: Use '+=' to add additional tests, not '=' powerpc/mm: Update the WIMG check during H_ENTER Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-22usb: Add QOM property "attached".Gerd Hoffmann
USB devices in attached state are visible to the guest. This patch adds a QOM property for this. Write access is opt-in per device. Some devices manage attached state automatically (usb-host, usb-serial, usb-redir), so we can't enable write access universally but have to do it on a case by case base. So far, no device opts in. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1465984019-28963-4-git-send-email-kraxel@redhat.com [ minor codestyle fix ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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