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2022-06-28semihosting: Split out guestfd.cRichard Henderson
In arm-compat-semi.c, we have more advanced treatment of guest file descriptors than we do in other implementations. Split out GuestFD and related functions to a new file so that they can be shared. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Add target_strlen for softmmu-uaccess.hRichard Henderson
Mirror the interface of the user-only function of the same name. Use probe_access_flags for the common case of ram, and cpu_memory_rw_debug for the uncommon case of mmio. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v3: Use probe_access_flags (pmm)
2022-06-28semihosting: Move softmmu-uaccess.h functions out of lineRichard Henderson
Rather that static (and not even inline) functions within a header, move the functions to semihosting/uaccess.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Return failure from softmmu-uaccess.h functionsRichard Henderson
We were reporting unconditional success for these functions; pass on any failure from cpu_memory_rw_debug. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.hRichard Henderson
We have a subdirectory for semihosting; move this file out of exec. Rename to emphasize the contents are a replacement for the functions in linux-user/bsd-user uaccess.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-27accel: Introduce current_accel_name()Alexander Graf
We need to fetch the name of the current accelerator in flexible error messages more going forward. Let's create a helper that gives it to us without casting in the target code. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620192242.70573-1-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-26ps2: remove update_irq() function and update_arg parameterMark Cave-Ayland
Now that all the PS2 devices have been converted to use GPIOs the update_irq() callback function and the update_arg parameter can be removed. This allows these arguments to be completely removed from ps2_kbd_init() and ps2_mouse_init(), along with the transitional logic that was added to ps2_raise_irq() and ps2_lower_irq(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-55-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: add QEMU interface comment for I8042 deviceMark Cave-Ayland
This describes the I8042 device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220624134109.881989-54-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-26pckbd: add QEMU interface comment for I8042_MMIO deviceMark Cave-Ayland
This describes the I8042_MMIO device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220624134109.881989-51-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-26lasips2: add QEMU interface commentMark Cave-Ayland
This describes the LASI PS2 device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220624134109.881989-49-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-26lasips2: add base propertyMark Cave-Ayland
This is in preparation for handling vmstate_register() within the device. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220624134109.881989-45-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-26lasips2: move mapping of LASIPS2 registers to HPPA machineMark Cave-Ayland
Now that the register memory regions are exposed as SysBus memory regions, move the mapping of the LASIPS2 registers from lasips2_initfn() to the HPPA machine (which is its only user). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-43-mark.cave-ayland@ilande.co.uk>
2022-06-26lasips2: rename lasips2_init() to lasips2_initfn() and update it to return ↵Mark Cave-Ayland
the LASIPS2 device When QOMifying a device it is typical to use _init() as the suffix for an instance_init function, however this name is already in use by the legacy LASIPS2 wrapper function. Eventually the wrapper function will be removed, but for now rename it to lasips2_initfn() to avoid a naming collision. At the same time update lasips2_initfn() return the LASIPS2 device so that it can later be accessed using qdev APIs by the HPPA machine. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-41-mark.cave-ayland@ilande.co.uk>
2022-06-26lasips2: move lasips2 QOM types from lasips2.c to lasips2.hMark Cave-Ayland
This allows the QOM types in lasips2.c to be used elsewhere by simply including lasips2.h. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-40-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: replace irq_kbd and irq_mouse with qemu_irq array in KBDStateMark Cave-Ayland
This allows both IRQs to be declared as a single qdev gpio array. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-36-mark.cave-ayland@ilande.co.uk>
2022-06-26ps2: add gpio for output IRQ and optionally use it in ps2_raise_irq() and ↵Mark Cave-Ayland
ps2_lower_irq() Define the gpio for the PS2 output IRQ in ps2_init() and add logic to optionally use it in ps2_raise_irq() and ps2_lower_irq() if the gpio is connected. If the gpio is not connected then call the legacy update_irq() function as before. This allows the incremental conversion of devices from the legacy update_irq() function to use gpios instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-35-mark.cave-ayland@ilande.co.uk>
2022-06-26ps2: make ps2_raise_irq() function staticMark Cave-Ayland
This function is no longer used outside of ps2.c and so can be declared static. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-32-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: move mapping of I8042_MMIO registers to MIPS magnum machineMark Cave-Ayland
Now that the register memory region is exposed as a SysBus memory region, move the mapping of the I8042_MMIO registers from i8042_mm_init() to the MIPS magnum machine (which is its only user). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-29-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: alter i8042_mm_init() to return a I8042_MMIO deviceMark Cave-Ayland
This exposes the I8042_MMIO device to the caller to allow the register memory region to be mapped outside of i8042_mm_init(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-28-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: implement i8042_mmio_realize() functionMark Cave-Ayland
Move the initialisation of the register memory region to the I8042_MMIO device realize function and expose it using sysbus_init_mmio(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-26-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: add size qdev property to I8042_MMIO deviceMark Cave-Ayland
This will soon be used to set the size of the register memory region using a qdev property. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-25-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: introduce new I8042_MMIO QOM typeMark Cave-Ayland
Currently i8042_mm_init() creates a new KBDState directly which is used by the MIPS magnum machine. Introduce a new I8042_MMIO QOM type that will soon be used to allow the MIPS magnum machine to be wired up using standard qdev GPIOs. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-22-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: move ISAKBDState from pckbd.c to i8042.hMark Cave-Ayland
This allows the QOM types in pckbd.c to be used elsewhere by simply including i8042.h. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220624134109.881989-21-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: move KBDState from pckbd.c to i8042.hMark Cave-Ayland
This allows the QOM types in pckbd.c to be used elsewhere by simply including i8042.h. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220624134109.881989-20-mark.cave-ayland@ilande.co.uk>
2022-06-26ps2: implement ps2_reset() for the PS2_DEVICE QOM type based upon ↵Mark Cave-Ayland
ps2_common_reset() The functionality of ps2_common_reset() can be moved into a new ps2_reset() function for the PS2_DEVICE QOM type. Update PS2DeviceClass to hold a reference to the parent reset function and update the PS2_KBD_DEVICE and PS2_MOUSE_DEVICE types to use device_class_set_parent_reset() accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220624134109.881989-9-mark.cave-ayland@ilande.co.uk>
2022-06-26ps2: introduce PS2DeviceClassMark Cave-Ayland
This is in preparation for allowing the new PS2_KBD_DEVICE and PS2_MOUSE_DEVICE QOM types to reference the parent PS2_DEVICE device reset() function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220624134109.881989-8-mark.cave-ayland@ilande.co.uk>
2022-06-26ps2: improve function prototypes in ps2.c and ps2.hMark Cave-Ayland
With the latest changes it is now possible to improve some of the function prototypes in ps2.c and ps.h to use the appropriate PS2KbdState or PS2MouseState type instead of being a void opaque. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220624134109.881989-7-mark.cave-ayland@ilande.co.uk>
2022-06-26ps2: move QOM type definitions from ps2.c to ps2.hMark Cave-Ayland
Move the QOM type definitions into the ps2.h header file to allow the new QOM types to be used by other devices. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220624134109.881989-6-mark.cave-ayland@ilande.co.uk>
2022-06-24aio_wait_kick: add missing memory barrierEmanuele Giuseppe Esposito
It seems that aio_wait_kick always required a memory barrier or atomic operation in the caller, but nobody actually took care of doing it. Let's put the barrier in the function instead, and pair it with another one in AIO_WAIT_WHILE. Read aio_wait_kick() comment for further explanation. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Message-Id: <20220524173054.12651-1-eesposit@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-06-24block: simplify handling of try to merge different sized bitmapsVladimir Sementsov-Ogievskiy
We have too much logic to simply check that bitmaps are of the same size. Let's just define that hbitmap_merge() and bdrv_dirty_bitmap_merge_internal() require their argument bitmaps be of same size, this simplifies things. Let's look through the callers: For backup_init_bcs_bitmap() we already assert that merge can't fail. In bdrv_reclaim_dirty_bitmap_locked() we gracefully handle the error that can't happen: successor always has same size as its parent, drop this logic. In bdrv_merge_dirty_bitmap() we already has assertion and separate check. Make the check explicit and improve error message. Signed-off-by: Vladimir Sementsov-Ogievskiy <v.sementsov-og@mail.ru> Reviewed-by: Nikita Lapshin <nikita.lapshin@virtuozzo.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20220517111206.23585-4-v.sementsov-og@mail.ru> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-06-24block: get rid of blk->guest_block_sizeStefan Hajnoczi
Commit 1b7fd729559c ("block: rename buffer_alignment to guest_block_size") noted: At this point, the field is set by the device emulation, but completely ignored by the block layer. The last time the value of buffer_alignment/guest_block_size was actually used was before commit 339064d50639 ("block: Don't use guest sector size for qemu_blockalign()"). This value has not been used since 2013. Get rid of it. Cc: Xie Yongji <xieyongji@bytedance.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20220518130945.2657905-1-stefanha@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Alberto Faria <afaria@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-06-24block: drop unused bdrv_co_drain() APIStefan Hajnoczi
bdrv_co_drain() has not been used since commit 9a0cec664eef ("mirror: use bdrv_drained_begin/bdrv_drained_end") in 2016. Remove it so there are fewer drain scenarios to worry about. Use bdrv_drained_begin()/bdrv_drained_end() instead. They are "mixed" functions that can be called from coroutine context. Unlike bdrv_co_drain(), these functions provide control of the length of the drained section, which is usually the right thing. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20220521122714.3837731-1-stefanha@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Reviewed-by: Alberto Faria <afaria@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-06-23hw/nvme: Add support for the Virtualization Management commandŁukasz Gieryk
With the new command one can: - assign flexible resources (queues, interrupts) to primary and secondary controllers, - toggle the online/offline state of given controller. Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-06-23hw/nvme: Initialize capability structures for primary/secondary controllersŁukasz Gieryk
With four new properties: - sriov_v{i,q}_flexible, - sriov_max_v{i,q}_per_vf, one can configure the number of available flexible resources, as well as the limits. The primary and secondary controller capability structures are initialized accordingly. Since the number of available queues (interrupts) now varies between VF/PF, BAR size calculation is also adjusted. Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-06-23hw/nvme: Add support for Secondary Controller ListLukasz Maniak
Introduce handling for Secondary Controller List (Identify command with CNS value of 15h). Secondary controller ids are unique in the subsystem, hence they are reserved by it upon initialization of the primary controller to the number of sriov_max_vfs. ID reservation requires the addition of an intermediate controller slot state, so the reserved controller has the address 0xFFFF. A secondary controller is in the reserved state when it has no virtual function assigned, but its primary controller is realized. Secondary controller reservations are released to NULL when its primary controller is unregistered. Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-06-23hw/nvme: Add support for Primary Controller CapabilitiesLukasz Maniak
Implementation of Primary Controller Capabilities data structure (Identify command with CNS value of 14h). Currently, the command returns only ID of a primary controller. Handling of remaining fields are added in subsequent patches implementing virtualization enhancements. Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-06-23hw/nvme: Add support for SR-IOVLukasz Maniak
This patch implements initial support for Single Root I/O Virtualization on an NVMe device. Essentially, it allows to define the maximum number of virtual functions supported by the NVMe controller via sriov_max_vfs parameter. Passing a non-zero value to sriov_max_vfs triggers reporting of SR-IOV capability by a physical controller and ARI capability by both the physical and virtual function devices. NVMe controllers created via virtual functions mirror functionally the physical controller, which may not entirely be the case, thus consideration would be needed on the way to limit the capabilities of the VF. NVMe subsystem is required for the use of SR-IOV. Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-06-22io: add a QIOChannelNull equivalent to /dev/nullDaniel P. Berrangé
This is for code which needs a portable equivalent to a QIOChannelFile connected to /dev/null. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-06-22hw/i2c/aspeed: add DEV_ADDR in old register modeKlaus Jensen
Add support for writing and reading the device address register in old register mode. On the AST2400 (only 1 slave address) * no upper bits On the AST2500 (2 possible slave addresses), * bit[31] : Slave Address match indicator * bit[30] : Slave Address Receiving pending On the AST2600 (3 possible slave addresses), * bit[31-30] : Slave Address match indicator * bit[29] : Slave Address Receiving pending The model could be more precise to take into account all fields but since the Linux driver is masking the register value being set, it should be fine. See commit 3fb2e2aeafb2 ("i2c: aspeed: disable additional device addresses on ast2[56]xx") from Zeiv. This can be addressed later. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> [ clg: add details to commit log ] Message-Id: <20220601210831.67259-3-its@irrelevant.dk> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed/i2c: Add ast1030 controller modelsCédric Le Goater
Based on : https://lore.kernel.org/qemu-devel/20220324100439.478317-2-troy_lee@aspeedtech.com/ Cc: Troy Lee <troy_lee@aspeedtech.com> Cc: Jamin Lin <jamin_lin@aspeedtech.com> Cc: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: i2c: Move regs and helpers to header fileJoe Komlodi
Moves register definitions and short commonly used inlined functiosn to the header file to help tidy up the implementation file. Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: I34dff7485b6bbe3c9482715ccd94dbd65dc5f324 Message-Id: <20220331043248.2237838-8-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: i2c: Add new mode supportJoe Komlodi
On AST2600, I2C has a secondary mode, called "new mode", which changes the layout of registers, adds some minor behavior changes, and introduces a new way to transfer data called "packet mode". Most of the bit positions of the fields are the same between old and new mode, so we use SHARED_FIELD_XX macros to reuse most of the code between the different modes. For packet mode, most of the command behavior is the same compared to other modes, but there are some minor changes to how interrupts are handled compared to other modes. Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: I072f8301964f623afc74af1fe50c12e5caef199e Message-Id: <20220331043248.2237838-6-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: i2c: Use reg array instead of individual varsJoe Komlodi
Using a register array will allow us to represent old-mode and new-mode I2C registers by using the same underlying register array, instead of adding an entire new set of variables to represent new mode. As part of this, we also do additional cleanup to use ARRAY_FIELD_ macros instead of FIELD_ macros on registers. Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: Ib94996b17c361b8490c042b43c99d8abc69332e3 [ clg: use of memset in aspeed_i2c_bus_reset() ] Message-Id: <20220331043248.2237838-5-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22hw/registerfields: Add shared fields macrosJoe Komlodi
Occasionally a peripheral will have different operating modes, where the MMIO layout changes, but some of the register fields have the same offsets and behaviors. To help support this, we add SHARED_FIELD_XX macros that create SHIFT, LENGTH, and MASK macros for the fields that are shared across registers, and accessors for these fields. An example use may look as follows: There is a peripheral with registers REG_MODE1 and REG_MODE2 at different addreses, and both have a field FIELD1 initialized by SHARED_FIELD(). Depending on what mode the peripheral is operating in, the user could extract FIELD1 via SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE1, FIELD1) or SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE2, FIELD1) Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: Id3dc53e7d2f8741c95697cbae69a81bb699fa3cb Message-Id: <20220331043248.2237838-2-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-20host-utils: Implemented signed 256-by-128 divisionLucas Mateus Castro (alqotel)
Based on already existing QEMU implementation created a signed 256 bit by 128 bit division needed to implement the vector divide extended signed quadword instruction from PowerISA 3.1 Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-6-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20host-utils: Implemented unsigned 256-by-128 divisionLucas Mateus Castro (alqotel)
Based on already existing QEMU implementation, created an unsigned 256 bit by 128 bit division needed to implement the vector divide extended unsigned instruction from PowerISA3.1 Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-5-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-16crypto: Introduce RSA algorithmzhenwei pi
There are two parts in this patch: 1, support akcipher service by cryptodev-builtin driver 2, virtio-crypto driver supports akcipher service In principle, we should separate this into two patches, to avoid compiling error, merge them into one. Then virtio-crypto gets request from guest side, and forwards the request to builtin driver to handle it. Test with a guest linux: 1, The self-test framework of crypto layer works fine in guest kernel 2, Test with Linux guest(with asym support), the following script test(note that pkey_XXX is supported only in a newer version of keyutils): - both public key & private key - create/close session - encrypt/decrypt/sign/verify basic driver operation - also test with kernel crypto layer(pkey add/query) All the cases work fine. Run script in guest: rm -rf *.der *.pem *.pfx modprobe pkcs8_key_parser # if CONFIG_PKCS8_PRIVATE_KEY_PARSER=m rm -rf /tmp/data dd if=/dev/random of=/tmp/data count=1 bs=20 openssl req -nodes -x509 -newkey rsa:2048 -keyout key.pem -out cert.pem -subj "/C=CN/ST=BJ/L=HD/O=qemu/OU=dev/CN=qemu/emailAddress=qemu@qemu.org" openssl pkcs8 -in key.pem -topk8 -nocrypt -outform DER -out key.der openssl x509 -in cert.pem -inform PEM -outform DER -out cert.der PRIV_KEY_ID=`cat key.der | keyctl padd asymmetric test_priv_key @s` echo "priv key id = "$PRIV_KEY_ID PUB_KEY_ID=`cat cert.der | keyctl padd asymmetric test_pub_key @s` echo "pub key id = "$PUB_KEY_ID keyctl pkey_query $PRIV_KEY_ID 0 keyctl pkey_query $PUB_KEY_ID 0 echo "Enc with priv key..." keyctl pkey_encrypt $PRIV_KEY_ID 0 /tmp/data enc=pkcs1 >/tmp/enc.priv echo "Dec with pub key..." keyctl pkey_decrypt $PRIV_KEY_ID 0 /tmp/enc.priv enc=pkcs1 >/tmp/dec cmp /tmp/data /tmp/dec echo "Sign with priv key..." keyctl pkey_sign $PRIV_KEY_ID 0 /tmp/data enc=pkcs1 hash=sha1 > /tmp/sig echo "Verify with pub key..." keyctl pkey_verify $PRIV_KEY_ID 0 /tmp/data /tmp/sig enc=pkcs1 hash=sha1 echo "Enc with pub key..." keyctl pkey_encrypt $PUB_KEY_ID 0 /tmp/data enc=pkcs1 >/tmp/enc.pub echo "Dec with priv key..." keyctl pkey_decrypt $PRIV_KEY_ID 0 /tmp/enc.pub enc=pkcs1 >/tmp/dec cmp /tmp/data /tmp/dec echo "Verify with pub key..." keyctl pkey_verify $PUB_KEY_ID 0 /tmp/data /tmp/sig enc=pkcs1 hash=sha1 Reviewed-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: lei he <helei.sig11@bytedance.com Signed-off-by: zhenwei pi <pizhenwei@bytedance.com> Message-Id: <20220611064243.24535-2-pizhenwei@bytedance.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-16virtio-iommu: Use recursive lock to avoid deadlockZhenzhong Duan
When switching address space with mutex lock hold, mapping will be replayed for assigned device. This will trigger relock deadlock. Also release the mutex resource in unrealize routine. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Message-Id: <20220613061010.2674054-3-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-16virtio-iommu: Add bypass mode support to assigned deviceZhenzhong Duan
Currently assigned devices can not work in virtio-iommu bypass mode. Guest driver fails to probe the device due to DMA failure. And the reason is because of lacking GPA -> HPA mappings when VM is created. Add a root container memory region to hold both bypass memory region and iommu memory region, so the switch between them is supported just like the implementation in virtual VT-d. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Message-Id: <20220613061010.2674054-2-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-16pci-bridge/cxl_upstream: Add a CXL switch upstream portJonathan Cameron
An initial simple upstream port emulation to allow the creation of CXL switches. The Device ID has been allocated for this use. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220616145126.8002-2-Jonathan.Cameron@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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