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2018-02-21fpu/softfloat: re-factor round_to_intAlex Bennée
We can now add float16_round_to_int and use the common round_decomposed and canonicalize functions to have a single implementation for float16/32/64 round_to_int functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor muladdAlex Bennée
We can now add float16_muladd and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 muladd functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor divAlex Bennée
We can now add float16_div and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor mulAlex Bennée
We can now add float16_mul and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor add/subAlex Bennée
We can now add float16_add/sub and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 add and sub functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-02-21include/fpu/softfloat: add some float16 constantsAlex Bennée
This defines the same set of common constants for float 16 as defined for 32 and 64 bit floats. These are often used by target helper functions. I've also removed constants that are not used by anybody. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21include/fpu/softfloat: implement float16_set_sign helperAlex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21include/fpu/softfloat: implement float16_chs helperAlex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21include/fpu/softfloat: implement float16_abs helperAlex Bennée
This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-21fpu/softfloat-types: new header to prevent excessive re-buildsAlex Bennée
The main culprit here is bswap.h which pulled in softfloat.h so it could use the types in its CPU_Float* and ldfl/stfql functions. As bswap.h is very widely included this added a compile dependency every time we touch softfloat.h. Move the typedefs for each float type into their own file so we don't re-build the world every time we tweak the main softfloat.h header. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21include/fpu/softfloat: remove USE_SOFTFLOAT_STRUCT_TYPESAlex Bennée
It's not actively built and when enabled things fail to compile. I'm not sure the type-checking is really helping here. Seeing as we "own" our softfloat now lets remove the cruft. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21fpu/softfloat: implement float16_squash_input_denormalAlex Bennée
This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-20cocoa: use DisplayOptionsGerd Hoffmann
Switch cocoa ui to use qapi DisplayOptions for configuration. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20180202111022.19269-10-kraxel@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-02-20curses: use DisplayOptionsGerd Hoffmann
Switch curses ui to use qapi DisplayOptions for configuration. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20180202111022.19269-9-kraxel@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-02-20egl-headless: use DisplayOptionsGerd Hoffmann
Switch egl-headless ui to use qapi DisplayOptions for configuration. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20180202111022.19269-8-kraxel@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-02-20sdl: use DisplayOptionsGerd Hoffmann
Switch sdl ui to use qapi DisplayOptions for configuration. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20180202111022.19269-6-kraxel@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-02-20gtk: add and use DisplayOptions + DisplayGTKGerd Hoffmann
Add QAPI DisplayType enum, DisplayOptions union and DisplayGTK struct. Switch gtk configuration to use the qapi type. Some bookkeeping (fullscreen for example) is done twice now, this is temporary until more/all UIs are switched over to qapi configuration. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20180202111022.19269-5-kraxel@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-02-19hw/rdma: Implementation of PVRDMA deviceYuval Shaia
PVRDMA is the QEMU implementation of VMware's paravirtualized RDMA device. It works with its Linux Kernel driver AS IS, no need for any special guest modifications. While it complies with the VMware device, it can also communicate with bare metal RDMA-enabled machines and does not require an RDMA HCA in the host, it can work with Soft-RoCE (rxe). It does not require the whole guest RAM to be pinned allowing memory over-commit and, even if not implemented yet, migration support will be possible with some HW assistance. Implementation is divided into 2 components, rdma general and pvRDMA specific functions and structures. The second PVRDMA sub-module - interaction with PCI layer. - Device configuration and setup (MSIX, BARs etc). - Setup of DSR (Device Shared Resources) - Setup of device ring. - Device management. Reviewed-by: Dotan Barak <dotanb@mellanox.com> Reviewed-by: Zhu Yanjun <yanjun.zhu@oracle.com> Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
2018-02-19include/standard-headers: add pvrdma related headersMarcel Apfelbaum
Import the headers used by the pvrdma device. Part of them are interfaces between the guest driver and the device, imported under include/standart-headers/drivers/infiniband/... . Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com>
2018-02-19mem: add share parameter to memory-backend-ramMarcel Apfelbaum
Currently only file backed memory backend can be created with a "share" flag in order to allow sharing guest RAM with other processes in the host. Add the "share" flag also to RAM Memory Backend in order to allow remapping parts of the guest RAM to different host virtual addresses. This is needed by the RDMA devices in order to remap non-contiguous QEMU virtual addresses to a contiguous virtual address range. Moved the "share" flag to the Host Memory base class, modified phys_mem_alloc to include the new parameter and a new interface memory_region_init_ram_shared_nomigrate. There are no functional changes if the new flag is not used. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
2018-02-16cuda.h: Fix multiple typedefDr. David Alan Gilbert
RHEL6's compilers don't like the repeated typedef. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-16Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180216' ↵Peter Maydell
into staging ppc patch queue 2018-02-16 Highlights of this batch: * Conversion to TranslatorOps (Emilio Cota) * Further bugfixes and cleanups to vcpu id allocation for pseries (Greg Kurz) * Another bugfix for HPT resizing (Daniel Henrique-Barboza) * Macintosh CUDA cleanups (Mark Cave-Ayland) * Further tweaks to Spectre/Meltdown mitigations (Suraj Singh) # gpg: Signature made Fri 16 Feb 2018 10:00:02 GMT # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.12-20180216: ppc4xx: Add device models found in PPC440 core SoCs ppc/spapr-caps: Disallow setting workaround for spapr-cap-ibs target/ppc: convert to TranslatorOps target/ppc: convert to DisasContextBase spapr: consolidate the VCPU id numbering logic in a single place spapr: rename spapr_vcpu_id() to spapr_get_vcpu_id() spapr: move VCPU calculation to core machine code spapr: use spapr->vsmt to compute VCPU ids ppc/spapr-caps: Change migration macro to take full spapr-cap name hw/char: remove legacy interface escc_init() hw/ppc/spapr_hcall: set htab_shift after kvmppc_resize_hpt_commit cuda: convert to trace-events ppc: move CUDAState and other CUDA-related definitions into separate cuda.h file cuda: convert to use the shared mos6522 device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-16Merge remote-tracking branch 'remotes/berrange/tags/qio-next-pull-request' ↵Peter Maydell
into staging # gpg: Signature made Thu 15 Feb 2018 17:50:22 GMT # gpg: using RSA key BE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/qio-next-pull-request: allow to build with older sed io/channel-command: Do not kill the child process after closing the pipe io: Add /dev/fdset/ support to QIOChannelFile io: Don't call close multiple times in QIOChannelFile io: Fix QIOChannelFile when creating and opening read-write io/channel-websock: handle continuous reads without any data io: fix QIONetListener memory leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-16ppc4xx: Add device models found in PPC440 core SoCsBALATON Zoltan
These devices are found in newer SoCs based on 440 core e.g. the 460EX (http://www.embeddeddeveloper.com/assets/processors/amcc/datasheets/ PP460EX_DS2063.pdf) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-16spapr: rename spapr_vcpu_id() to spapr_get_vcpu_id()Greg Kurz
The spapr_vcpu_id() function is an accessor actually. Let's rename it for symmetry with the recently added spapr_set_vcpu_id() helper. The motivation behind this is that a later patch will consolidate the VCPU id formula in a function and spapr_vcpu_id looks like an appropriate name. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-16spapr: move VCPU calculation to core machine codeGreg Kurz
The VCPU ids are currently computed and assigned to each individual CPU threads in spapr_cpu_core_realize(). But the numbering logic of VCPU ids is actually a machine-level concept, and many places in hw/ppc/spapr.c also have to compute VCPU ids out of CPU indexes. The current formula used in spapr_cpu_core_realize() is: vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i where: cc->core_id is a multiple of smp_threads cpu_index = cc->core_id + i 0 <= i < smp_threads So we have: cpu_index % smp_threads == i cc->core_id / smp_threads == cpu_index / smp_threads hence: vcpu_id = (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; This formula was used before VSMT at the time VCPU ids where computed at the target emulation level. It has the advantage of being useable to derive a VPCU id out of a CPU index only. It is fitted for all the places where the machine code has to compute a VCPU id. This patch introduces an accessor to set the VCPU id in a PowerPCCPU object using the above formula. It is a first step to consolidate all the VCPU id logic in a single place. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-16hw/char: remove legacy interface escc_init()Laurent Vivier
Move necessary stuff in escc.h and update type names. Remove slavio_serial_ms_kbd_init(). Fix code style problems reported by checkpatch.pl Update mac_newworld, mac_oldworld and sun4m to use directly the QDEV interface. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-16ppc: move CUDAState and other CUDA-related definitions into separate cuda.h fileMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-15bcm2836: Make CPU type configurablePekka Enberg
This patch adds a "cpu-type" property to BCM2836 SoC in preparation for reusing the code for the Raspberry Pi 3, which has a different processor model. Signed-off-by: Pekka Enberg <penberg@iki.fi> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.ioPhilippe Mathieu-Daudé
(qemu) info mtree address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom - 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io + 000000001e600000-000000001e7fffff (prio -1000, i/o): aspeed_soc.io 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 000000001e631000-000000001e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180209085755.30414-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15io: Fix QIOChannelFile when creating and opening read-writeRoss Lagerwall
The code wrongly passes the mode to open() only if O_WRONLY is set. Instead, the mode should be passed when O_CREAT is set (or O_TMPFILE on Linux). Fix this by always passing the mode since open() will correctly ignore the mode if it is not needed. Add a testcase which exercises this bug and also change the existing testcase to check that the mode of the created file is correct. Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2018-02-15Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Pull request v2: * Dropped Fam's git-publish series because there is still ongoing discussion # gpg: Signature made Thu 15 Feb 2018 09:42:03 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: misc: fix spelling ratelimit: don't align wait time with slices vl: pause vcpus before stopping iothreads Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15ratelimit: don't align wait time with slicesWolfgang Bumiller
It is possible for rate limited writes to keep overshooting a slice's quota by a tiny amount causing the slice-aligned waiting period to effectively halve the rate. Signed-off-by: Wolfgang Bumiller <w.bumiller@proxmox.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Message-id: 20180207071758.6818-1-w.bumiller@proxmox.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-02-13Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block layer patches # gpg: Signature made Tue 13 Feb 2018 17:03:11 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (55 commits) iotests: Add l2-cache-entry-size to iotest 137 iotests: Test downgrading an image using a small L2 slice size iotests: Test valid values of l2-cache-entry-size qcow2: Allow configuring the L2 slice size qcow2: Rename l2_table in count_cow_clusters() qcow2: Rename l2_table in count_contiguous_clusters_unallocated() qcow2: Rename l2_table in count_contiguous_clusters() qcow2: Rename l2_table in qcow2_alloc_compressed_cluster_offset() qcow2: Update qcow2_truncate() to support L2 slices qcow2: Update expand_zero_clusters_in_l1() to support L2 slices qcow2: Prepare expand_zero_clusters_in_l1() for adding L2 slice support qcow2: Read refcount before L2 table in expand_zero_clusters_in_l1() qcow2: Update qcow2_update_snapshot_refcount() to support L2 slices qcow2: Prepare qcow2_update_snapshot_refcount() for adding L2 slice support qcow2: Update zero_single_l2() to support L2 slices qcow2: Update discard_single_l2() to support L2 slices qcow2: Update handle_alloc() to support L2 slices qcow2: Update handle_copied() to support L2 slices qcow2: Update qcow2_alloc_cluster_link_l2() to support L2 slices qcow2: Update qcow2_get_cluster_offset() to support L2 slices ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-13Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* CAN bus (will be under network maintainner) * scsi-block opblockers (myself) * Dirty log bitmap cleanup (myself) * SDHCI improvements and tests (Philippe) * HAX support for larger guest sizese (Yu Ning) # gpg: Signature made Tue 13 Feb 2018 15:37:14 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (48 commits) travis: use libgcc-4.8-dev (libgcc-6-dev is not available on Ubuntu 14.04) memory: unify loops to sync dirty log bitmap memory: hide memory_region_sync_dirty_bitmap behind DirtyBitmapSnapshot memory: remove memory_region_test_and_clear_dirty g364fb: switch to using DirtyBitmapSnapshot sdhci: add Spec v4.2 register definitions sdhci: add a check_capab_v3() qtest sdhci: check Spec v3 capabilities qtest hw/arm/xilinx_zynqmp: enable the UHS-I mode hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet hw/arm/fsl-imx6: implement SDHCI Spec. v3 hw/arm/bcm2835_peripherals: change maximum block size to 1kB hw/arm/bcm2835_peripherals: implement SDHCI Spec v3 sdhci: implement CMD/DAT[] fields in the Present State register sdhci: implement UHS-I voltage switch sdbus: add trace events sdhci: implement the Host Control 2 register (tuning sequence) sdhci: rename the hostctl1 register sdhci: add support for v3 capabilities hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-13Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio,vhost,pci,pc: features, fixes and cleanups - new stats in virtio balloon - virtio eventfd rework for boot speedup - vhost memory rework for boot speedup - fixes and cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 13 Feb 2018 16:29:55 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (22 commits) virtio-balloon: include statistics of disk/file caches acpi-test: update FADT lpc: drop pcie host dependency tests: acpi: fix FADT not being compared to reference table hw/pci-bridge: fix pcie root port's IO hints capability libvhost-user: Support across-memory-boundary access libvhost-user: Fix resource leak virtio-balloon: unref the memory region before continuing pci: removed the is_express field since a uniform interface was inserted virtio-blk: enable multiple vectors when using multiple I/O queues pci/bus: let it has higher migration priority pci-bridge/i82801b11: clear bridge registers on platform reset vhost: Move log_dirty check vhost: Merge and delete unused callbacks vhost: Clean out old vhost_set_memory and friends vhost: Regenerate region list from changed sections list vhost: Merge sections added to temporary list vhost: Simplify ring verification checks vhost: Build temporary section list and deref after commit virtio: improve virtio devices initialization time ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-13virtio-balloon: include statistics of disk/file cachesTomáš Golembiovský
Signed-off-by: Tomáš Golembiovský <tgolembi@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-02-13hw/pci-bridge: fix pcie root port's IO hints capabilityMarcel Apfelbaum
The gen_pcie_root_port mem-reserve and pref32-reserve properties are defined as size (so uint64_t), but passed as uint32_t when building the 'IO hints' vendor specific capability. Passing 4G (or more) gets truncated and passed as a zero reservation. Is not a huge issue since the guest firmware will always compare the hints with the default value and take the maximum. Fix it by passing the values as uint64_t and failing to init the gen_pcie_root_port id invalid values are used. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-02-13block: maintain persistent disabled bitmapsVladimir Sementsov-Ogievskiy
To maintain load/store disabled bitmap there is new approach: - deprecate @autoload flag of block-dirty-bitmap-add, make it ignored - store enabled bitmaps as "auto" to qcow2 - store disabled bitmaps without "auto" flag to qcow2 - on qcow2 open load "auto" bitmaps as enabled and others as disabled (except in_use bitmaps) Also, adjust iotests 165 and 176 appropriately. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-id: 20180202160752.143796-1-vsementsov@virtuozzo.com Signed-off-by: Max Reitz <mreitz@redhat.com>
2018-02-13memory: hide memory_region_sync_dirty_bitmap behind DirtyBitmapSnapshotPaolo Bonzini
Simplify the users of memory_region_snapshot_and_clear_dirty, so that they do not have to call memory_region_sync_dirty_bitmap explicitly. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13memory: remove memory_region_test_and_clear_dirtyPaolo Bonzini
It is unused after g364fb has been converted to use DirtyBitmapSnapshot. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13sdhci: implement CMD/DAT[] fields in the Present State registerPhilippe Mathieu-Daudé
[based on a patch from Alistair Francis <alistair.francis@xilinx.com> from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-23-f4bug@amsat.org>
2018-02-13sdhci: implement UHS-I voltage switchPhilippe Mathieu-Daudé
[based on a patch from Alistair Francis <alistair.francis@xilinx.com> from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-22-f4bug@amsat.org>
2018-02-13sdhci: implement the Host Control 2 register (tuning sequence)Philippe Mathieu-Daudé
[based on a patch from Alistair Francis <alistair.francis@xilinx.com> from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-20-f4bug@amsat.org>
2018-02-13sdhci: rename the hostctl1 registerPhilippe Mathieu-Daudé
As per the Spec v3.00 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-19-f4bug@amsat.org>
2018-02-13sdhci: add a 'spec_version property' (default to v2)Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-8-f4bug@amsat.org>
2018-02-13net/can: simple messages transport implementation for QEMUPavel Pisa
The CanBusState state structure is created for each emulated CAN channel. Individual clients/emulated CAN interfaces or host interface connection registers to the bus by CanBusClientState structure. The CAN core is prepared to support connection to the real host CAN bus network. The commit with such support for Linux SocketCAN follows. Implementation is as simple as possible. There is no state to be migrated, and messages prioritization and queuing are not considered for now. But it is intended to be extended when need arises. Development repository and more documentation at https://gitlab.fel.cvut.cz/canbus/qemu-canbus The work is based on Jin Yang GSoC 2013 work funded by Google and mentored in frame of RTEMS project GSoC slot donated to QEMU. Rewritten for QEMU-2.0+ versions and architecture cleanup by Pavel Pisa (Czech Technical University in Prague). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13hax: Support guest RAM sizes of 4GB or moreYu Ning
Since HAX_VM_IOCTL_ALLOC_RAM takes a 32-bit size, it cannot handle RAM blocks of 4GB or larger, which is why HAXM can only run guests with less than 4GB of RAM. Solve this problem by utilizing the new HAXM API, HAX_VM_IOCTL_ADD_RAMBLOCK, which takes a 64-bit size, to register RAM blocks with the HAXM kernel module. The new API is first added in HAXM 7.0.0, and its availablility and be confirmed by the presence of the HAX_CAP_64BIT_RAMBLOCK capability flag. When the guest RAM size reaches 7GB, QEMU will ask HAXM to set up a memory mapping that covers a 4GB region, which will fail, because HAX_VM_IOCTL_SET_RAM also takes a 32-bit size. Work around this limitation by splitting the large mapping into small ones and calling HAX_VM_IOCTL_SET_RAM multiple times. Bug: https://bugs.launchpad.net/qemu/+bug/1735576 Signed-off-by: Yu Ning <yu.ning@intel.com> Message-Id: <1515752555-12784-1-git-send-email-yu.ning@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-12Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180212' ↵Peter Maydell
into staging ppc patch queue 2018-02-12 Here's the accumulatead ppc and pseries related patches for the last while. Highlights are: * A number of Macintosh / CUDA cleanups from Mark Cave-Ayland * An important bug fix (missing "break;") for H_GET_CPU_CHARACTERISTICS * Yet another fix for SMT mode handling * Assorted other cleanups and fixes # gpg: Signature made Mon 12 Feb 2018 03:39:30 GMT # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.12-20180212: misc: introduce new mos6522 VIA device and enable it for ppc builds cuda: factor out timebase-derived counter value and load time cuda: set timer 1 frequency property to CUDA_TIMER_FREQ cuda: don't call cuda_update() when writing to ACR register cuda: minor cosmetic tidy-ups to get_next_irq_time() cuda: rename frequency property to tb_frequency cuda: introduce CUDAState parameter to get_counter() spapr: set vsmt to MAX(8, smp_threads) cuda: don't allow writes to port output pins cuda: do not use old_mmio accesses hw/ppc: rename functions in comments spapr: add missing break in h_get_cpu_characteristics() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-14 04:47:26 +0000