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2019-07-04Merge remote-tracking branch ↵Peter Maydell
'remotes/palmer/tags/riscv-for-master-4.1-sf1-v3' into staging RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 This pull request contains a handful of patches that I'd like to target for the 4.1 soft freeze. There are a handful of new features: * Support for the 1.11.0, the latest privileged specification. * Support for reading and writing the PRCI registers. * Better control over the ISA of the target machine. * Support for the cpu-topology device tree node. Additionally, there are a handful of bug fixes including: * Load reservations are now broken by both store conditional and by scheduling, which fixes issues with parallel applications. * Various fixes to the PMP implementation. * Fixes to the 32-bit linux-user syscall ABI. * Various fixes for instruction decodeing. * A fix to the PCI device tree "bus-range" property. This boots 32-bit and 64-bit OpenEmbedded. Changes since v2 [riscv-for-master-4.1-sf1-v2]: * Dropped OpenSBI. Changes since v1 [riscv-for-master-4.1-sf1]: * Contains a fix to the sifive_u OpenSBI integration. # gpg: Signature made Wed 03 Jul 2019 09:39:09 BST # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.1-sf1-v3: (32 commits) hw/riscv: Extend the kernel loading support hw/riscv: Add support for loading a firmware hw/riscv: Split out the boot functions riscv: sifive_u: Update the plic hart config to support multicore riscv: sifive_u: Do not create hard-coded phandles in DT disas/riscv: Fix `rdinstreth` constraint disas/riscv: Disassemble reserved compressed encodings as illegal riscv: virt: Add cpu-topology DT node. RISC-V: Update syscall list for 32-bit support. RISC-V: Clear load reservations on context switch and SC RISC-V: Add support for the Zicsr extension RISC-V: Add support for the Zifencei extension target/riscv: Add support for disabling/enabling Counters target/riscv: Remove user version information target/riscv: Require either I or E base extension qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 target/riscv: Set privledge spec 1.11.0 as default target/riscv: Add the mcountinhibit CSR target/riscv: Add the privledge spec version 1.11.0 target/riscv: Restructure deprecatd CPUs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-03Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190703-pull-request' ↵Peter Maydell
into staging vga: virtio fixes, bitbang i2c asan fix, install ati vgabios. # gpg: Signature made Wed 03 Jul 2019 09:53:44 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20190703-pull-request: Add ati vgabios to INSTALL_BLOBS. hw/i2c/bitbang_i2c: Use in-place rather than malloc'd bitbang_i2c_interface struct virtio-gpu: check if the resource already exists in virtio_gpu_load() virtio-gpu: fix unmap in error path Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-03hw/i2c/bitbang_i2c: Use in-place rather than malloc'd bitbang_i2c_interface ↵Peter Maydell
struct Currently the bitbang_i2c_init() function allocates a bitbang_i2c_interface struct which it returns. This is unfortunate because it means that if the function is used from a DeviceState init method then the memory will be leaked by an "init then delete" cycle, as used by the qmp/hmp commands that list device properties. Since three out of four of the uses of this function are in device init methods, switch the function to do an in-place initialization of a struct that can be embedded in the device state struct of the caller. This fixes LeakSanitizer leak warnings that have appeared in the patchew configuration (which only tries to run the sanitizers for the x86_64-softmmu target) now that we use the bitbang-i2c code in an x86-64 config. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190702163844.20458-1-peter.maydell@linaro.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-07-03Merge remote-tracking branch ↵Peter Maydell
'remotes/armbru/tags/pull-monitor-2019-07-02-v2' into staging Monitor patches for 2019-07-02 # gpg: Signature made Tue 02 Jul 2019 12:37:57 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-monitor-2019-07-02-v2: dump: Move HMP command handlers to dump/ MAINTAINERS: Add Windows dump to section "Dump" dump: Move the code to dump/ qapi: Split dump.json off misc.json qapi: Rename target.json to misc-target.json qapi: Split machine-target.json off target.json and misc.json hw/core: Collect HMP command handlers in hw/core/ hw/core: Collect QMP command handlers in hw/core/ hw/core: Move numa.c to hw/core/ qapi: Split machine.json off misc.json MAINTAINERS: Merge sections CPU, NUMA into Machine core qom: Move HMP command handlers to qom/ qom: Move QMP command handlers to qom/ qapi: Split qom.json and qdev.json off misc.json hmp: Move hmp.h to include/monitor/ Makefile: Don't add monitor/ twice to common-obj-y MAINTAINERS: Make section "QOM" cover qdev as well MAINTAINERS: new maintainers for QOM Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.1-20190702' ↵Peter Maydell
into staging ppc patch queue 2019-07-2 Here's my next pull request for qemu-4.1. I'm not sure if this will squeak in just before the soft freeze, or just after. I don't think it really matters - most of this is bugfixes anyway. There's some cleanups which aren't stictly bugfixes, but which I think are safe enough improvements to go in the soft freeze. There's no true feature work. Unfortunately, I wasn't able to complete a few of my standard battery of pre-pull tests, due to some failures that appear to also be in master. I'm hoping that hasn't missed anything important in here. Highlights are: * A number of fixe and cleanups for the XIVE implementation * Cleanups to the XICS interrupt controller to fit better with the new XIVE code * Numerous fixes and improvements to TCG handling of ppc vector instructions * Remove a number of unnnecessary #ifdef CONFIG_KVM guards * Fix some errors in the PCI hotplug paths * Assorted other fixes # gpg: Signature made Tue 02 Jul 2019 07:07:15 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.1-20190702: (49 commits) spapr/xive: Add proper rollback to kvmppc_xive_connect() ppc/xive: Fix TM_PULL_POOL_CTX special operation ppc/pnv: Rework cache watch model of PnvXIVE ppc/xive: Make the PIPR register readonly ppc/xive: Force the Physical CAM line value to group mode spapr/xive: simplify spapr_irq_init_device() to remove the emulated init spapr/xive: rework the mapping the KVM memory regions spapr_pci: Unregister listeners before destroying the IOMMU address space target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c target/ppc: introduce separate generator and helper for xscvqpdp target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2019-07-02' ↵Peter Maydell
into staging Block patches for 4.1-rc0: - The stream job no longer relies on a fixed base node - The rbd block driver can now accomodate growing formats like qcow2 # gpg: Signature made Tue 02 Jul 2019 02:56:06 BST # gpg: using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40 # gpg: issuer "mreitz@redhat.com" # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/maxreitz/tags/pull-block-2019-07-02: block/stream: introduce a bottom node block/stream: refactor stream_run: drop goto block: include base when checking image chain for block allocation block/rbd: increase dynamically the image size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Tue 02 Jul 2019 03:21:54 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: migration/colo.c: Add missed filter notify for Xen COLO. COLO-compare: Add colo-compare remote notify support COLO-compare: Make the compare_chr_send() can send notification message. COLO-compare: Add remote notification chardev handler frame COLO-compare: Add new parameter to communicate with remote colo-frame net/announce: Expand test for stopping self announce net/announce: Add HMP optional ID net/announce: Add optional ID net/announce: Add HMP optional interface list net/announce: Allow optional list of interfaces net: remove unused get_str_sep() function net: use g_strsplit() for parsing host address and port net: avoid using variable length array in net_client_init() net: fix assertion failure when ipv6-prefixlen is not a number ftgmac100: do not link to netdev qemu-bridge-helper: Document known shortcomings MAINTAINERS: Add qemu-bridge-helper.c to "Network device backends" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20190701' into staging target-arm queue: * hw/arm/boot: fix direct kernel boot with initrd * hw/arm/msf2-som: Exit when the cpu is not the expected one * i.mx7: fix bugs in PCI controller needed to boot recent kernels * aspeed: add RTC device * aspeed: fix some timer device bugs * aspeed: add swift-bmc board * aspeed: vic: Add support for legacy register interface * aspeed: add aspeed-xdma device * Add new sbsa-ref board for aarch64 * target/arm: code refactoring in preparation for support of compilation with TCG disabled # gpg: Signature made Mon 01 Jul 2019 17:38:10 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190701: (46 commits) target/arm: Declare some M-profile functions publicly target/arm: Declare arm_log_exception() function publicly target/arm: Restrict PSCI to TCG target/arm/vfp_helper: Restrict the SoftFloat use to TCG target/arm/vfp_helper: Extract vfp_set_fpscr_from_host() target/arm/vfp_helper: Extract vfp_set_fpscr_to_host() target/arm/vfp_helper: Move code around target/arm: Move TLB related routines to tlb_helper.c target/arm: Declare get_phys_addr() function publicly target/arm: Move CPU state dumping routines to cpu.c target/arm: Move the DC ZVA helper into op_helper target/arm: Fix coding style issues target/arm: Fix multiline comment syntax target/arm/helper: Remove unused include target/arm: Add copyright boilerplate target/arm: Makefile cleanup (softmmu) target/arm: Makefile cleanup (KVM) target/arm: Makefile cleanup (ARM) target/arm: Makefile cleanup (Aarch64) hw/arm: Add arm SBSA reference machine, devices part ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02qapi: Split dump.json off misc.jsonMarkus Armbruster
Move commands dump-guest-memory, query-dump, query-dump-guest-memory-capability with their types from misc.json to new dump.json. Add dump.json to MAINTAINERS section "Dump". Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-15-armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-07-02hw/core: Collect HMP command handlers in hw/core/Markus Armbruster
Move the HMP handlers related to qapi/machine.json to hw/core/machine-hmp-cmds.c, where they are covered by MAINTAINERS section "Machine core", just like qapi/machine.json. Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-12-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-07-02hw/core: Collect QMP command handlers in hw/core/Markus Armbruster
The handlers for qapi/machine.json's QMP commands are spread over cpus.c, hw/core/numa.c, monitor/misc.c, monitor/qmp-cmds.c, and vl.c. Move them all to new hw/core/machine-qmp-cmds.c, where they are covered by MAINTAINERS section "Machine core", just like qapi/machine.json. Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-11-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-07-02qapi: Split machine.json off misc.jsonMarkus Armbruster
Move commands cpu-add, query-cpus, query-cpus-fast, query-current-machine, query-hotpluggable-cpus, query-machines, query-memdev, and set-numa-node with their types from misc.json to new machine.json. Also move types X86CPURegister32 and X86CPUFeatureWordInfo. Add machine.json to MAINTAINERS section "Machine core". Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-9-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-07-02qom: Move HMP command handlers to qom/Markus Armbruster
Move the HMP command handlers related to QOM handlers from monitor/hmp-cmds.c and qdev-monitor.c to new qom/qom-hmp-cmds.c, where they are covered by MAINTAINERS section QOM. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Daniel P. Berrange" <berrange@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-7-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> [Also move hmp_info_qom_tree(), tweak commit message accordingly]
2019-07-02Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190701' into stagingPeter Maydell
- cleanup/refactoring in the cpu feature code - fix for a tcg test case - halt/clear support for vfio-ccw, and use a new helper # gpg: Signature made Mon 01 Jul 2019 12:08:41 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190701: s390x: add cpu feature/model files to KVM section vfio-ccw: support async command subregion vfio-ccw: use vfio_set_irq_signaling s390x/cpumodel: Prepend KDSA features with "KDSA" s390x/cpumodel: Rework CPU feature definition tests/tcg/s390x: Fix alignment of csst parameter list Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02hmp: Move hmp.h to include/monitor/Markus Armbruster
Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-4-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-07-02net/announce: Add optional IDDr. David Alan Gilbert
Previously there was a single instance of the timer used by monitor triggered announces, that's OK, but when combined with the previous change that lets you have announces for subsets of interfaces it's a bit restrictive if you want to do different things to different interfaces. Add an 'id' field to the announce, and maintain a list of the timers based on id. This allows you to for example: a) Start an announce going on interface eth0 for a long time b) Start an announce going on interface eth1 for a long time c) Kill the announce on eth0 while leaving eth1 going. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-07-02net/announce: Allow optional list of interfacesDr. David Alan Gilbert
Allow the caller to restrict the set of interfaces that announces are sent on. The default is still to send on all interfaces. e.g. { "execute": "announce-self", "arguments": { "initial": 50, "max": 550, "rounds": 5, "step": 50, "interfaces": ["vn2", "vn1"] } } This doesn't affect the behaviour of migraiton announcments. Note: There's still only one timer for the qmp command, so that performing an 'announce-self' on one list of interfaces followed by another 'announce-self' on another list will stop the announces on the existing set. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-07-02block: include base when checking image chain for block allocationAndrey Shinkevich
This patch is used in the 'block/stream: introduce a bottom node' that is following. Instead of the base node, the caller may pass the node that has the base as its backing image to the function bdrv_is_allocated_above() with a new parameter include_base = true and get rid of the dependency on the base that may change during commit/stream parallel jobs. Now, if the specified base is not found in the backing image chain, the QEMU will abort. Suggested-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: Andrey Shinkevich <andrey.shinkevich@virtuozzo.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Message-id: 1559152576-281803-2-git-send-email-andrey.shinkevich@virtuozzo.com [mreitz: Squashed in the following as a rebase on conflicting patches:] Message-id: e3cf99ae-62e9-8b6e-5a06-d3c8b9363b85@redhat.com Signed-off-by: Max Reitz <mreitz@redhat.com>
2019-07-02spapr/xive: simplify spapr_irq_init_device() to remove the emulated initCédric Le Goater
The init_emu() handles are now empty. Remove them and rename spapr_irq_init_device() to spapr_irq_init_kvm(). Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190614165920.12670-3-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02spapr/xive: rework the mapping the KVM memory regionsCédric Le Goater
Today, the interrupt device is fully initialized at reset when the CAS negotiation process has completed. Depending on the KVM capabilities, the SpaprXive memory regions (ESB, TIMA) are initialized with a host MMIO backend or a QEMU emulated backend. This results in a complex initialization sequence partially done at realize and later at reset, and some memory region leaks. To simplify this sequence and to remove of the late initialization of the emulated device which is required to be done only once, we introduce new memory regions specific for KVM. These regions are mapped as overlaps on top of the emulated device to make use of the host MMIOs. Also provide proper cleanups of these regions when the XIVE KVM device is destroyed to fix the leaks. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190614165920.12670-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02spapr_pci: Unregister listeners before destroying the IOMMU address spaceGreg Kurz
Hot-unplugging a PHB with a VFIO device connected to it crashes QEMU: -device spapr-pci-host-bridge,index=1,id=phb1 \ -device vfio-pci,host=0034:01:00.3,id=vfio0 (qemu) device_del phb1 [ 357.207183] iommu: Removing device 0001:00:00.0 from group 1 [ 360.375523] rpadlpar_io: slot PHB 1 removed qemu-system-ppc64: memory.c:2742: do_address_space_destroy: Assertion `QTAILQ_EMPTY(&as->listeners)' failed. 'as' is the IOMMU address space, which indeed has a listener registered to by vfio_connect_container() when the VFIO device is realized. This listener is supposed to be unregistered by vfio_disconnect_container() when the VFIO device is finalized. Unfortunately, the VFIO device hasn't reached finalize yet at the time the PHB unrealize function is called, and address_space_destroy() gets called with the VFIO listener still being registered. All regions have just been unmapped from the address space. Listeners aren't needed anymore at this point. Remove them before destroying the address space. The VFIO code will try to remove them _again_ at device finalize, but it is okay since memory_listener_unregister() is idempotent. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <156110925375.92514.11649846071216864570.stgit@bahia.lan> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> [dwg: Correct spelling error pointed out by aik] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02xics/kvm: Add error propagation to ic*_set_kvm_state() functionsGreg Kurz
This allows errors happening there to be propagated up to spapr_irq, just like XIVE already does. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <156077921763.433243.4614327010172954196.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02xics/spapr: Rename xics_kvm_init()Greg Kurz
Switch to using the connect/disconnect terminology like we already do for XIVE. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <156077920102.433243.6605099291134598170.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02xics/spapr: Drop unused function declarationGreg Kurz
Commit 9fb6eb7ca50c added the declaration of xics_spapr_connect(), which has no implementation and no users. This is a leftover from a previous iteration of this patch. Drop it. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <156077919546.433243.8748677531446035746.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02xics/spapr: Detect old KVM XICS on POWER9 hostsGreg Kurz
Older KVMs on POWER9 don't support destroying/recreating a KVM XICS device, which is required by 'dual' interrupt controller mode. This causes QEMU to emit a warning when the guest is rebooted and to fall back on XICS emulation: qemu-system-ppc64: warning: kernel_irqchip allowed but unavailable: Error on KVM_CREATE_DEVICE for XICS: File exists If kernel irqchip is required, QEMU will thus exit when the guest is first rebooted. Failing QEMU this late may be a painful experience for the user. Detect that and exit at machine init instead. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <156044430517.125694.6207865998817342638.stgit@bahia.lab.toulouse-stg.fr.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02xics/spapr: Register RTAS/hypercalls once at machine initGreg Kurz
QEMU may crash when running a spapr machine in 'dual' interrupt controller mode on some older (but not that old, eg. ubuntu 18.04.2) KVMs with partial XIVE support: qemu-system-ppc64: hw/ppc/spapr_rtas.c:411: spapr_rtas_register: Assertion `!name || !rtas_table[token].name' failed. XICS is controlled by the guest thanks to a set of RTAS calls. Depending on whether KVM XICS is used or not, the RTAS calls are handled by KVM or QEMU. In both cases, QEMU needs to expose the RTAS calls to the guest through the "rtas" node of the device tree. The spapr_rtas_register() helper takes care of all of that: it adds the RTAS call token to the "rtas" node and registers a QEMU callback to be invoked when the guest issues the RTAS call. In the KVM XICS case, QEMU registers a dummy callback that just prints an error since it isn't supposed to be invoked, ever. Historically, the XICS controller was setup during machine init and released during final teardown. This changed when the 'dual' interrupt controller mode was added to the spapr machine: in this case we need to tear the XICS down and set it up again during machine reset. The crash happens because we indeed have an incompatibility with older KVMs that forces QEMU to fallback on emulated XICS, which tries to re-registers the same RTAS calls. This could be fixed by adding proper rollback that would unregister RTAS calls on error. But since the emulated RTAS calls in QEMU can now detect when they are mistakenly called while KVM XICS is in use, it seems simpler to register them once and for all at machine init. This fixes the crash and allows to remove some now useless lines of code. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <156044429963.125694.13710679451927268758.stgit@bahia.lab.toulouse-stg.fr.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02ppc/pnv: remove xscom_base field from PnvChipCédric Le Goater
It has now became useless with the previous patch. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190612174345.9799-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02ppc/pnv: fix XSCOM MMIO base address for P9 machines with multiple chipsCédric Le Goater
The PNV_XSCOM_BASE and PNV_XSCOM_SIZE macros are specific to POWER8 and they are used when the device tree is populated and the MMIO region created, even for POWER9 chips. This is not too much of a problem today because we don't have important devices on the second chip, but we might have oneday (PHBs). Fix by using the appropriate macros in case of P9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190612174345.9799-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-01Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190628-pull-request' ↵Peter Maydell
into staging vga: ati fixes, add ati vgabios. # gpg: Signature made Fri 28 Jun 2019 11:39:32 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20190628-pull-request: ati-vga: switch to vgabios-ati.bin seabios: add ati vgabios binary seabios: add config for ati vgabios ati-vga: Fixes to offset and pitch registers ati-vga: Implement DDC and EDID info from monitor i2c: Move bitbang_i2c.h to include/hw/i2c/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01aspeed: Link SCU to the watchdogJoel Stanley
The ast2500 uses the watchdog to reset the SDRAM controller. This operation is usually performed by u-boot's memory training procedure, and it is enabled by setting a bit in the SCU and then causing the watchdog to expire. Therefore, we need the watchdog to be able to access the SCU's register space. This causes the watchdog to not perform a system reset when the bit is set. In the future it could perform a reset of the SDMC model. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190621065242.32535-1-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01hw/misc/aspeed_xdma: New deviceEddie James
The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations between the SOC (acting as a BMC) and a host processor in a server. The XDMA engine exists on the AST2400, AST2500, and AST2600 SOCs, so enable it for all of those. Add trace events on the important register writes in the XDMA engine. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190618165311.27066-21-clg@kaod.org [clg: - changed title ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01aspeed/smc: add a 'sdram_base' propertyCédric Le Goater
The DRAM address of a DMA transaction depends on the DRAM base address of the SoC. Inform the SMC controller model with this value. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190618165311.27066-15-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01aspeed: add support for multiple NICsCédric Le Goater
The Aspeed SoCs have two MACs. Extend the Aspeed model to support a second NIC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190618165311.27066-7-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01aspeed: introduce a configurable number of CPU per machineCédric Le Goater
The current models of the Aspeed SoCs only have one CPU but future ones will support SMP. Introduce a new num_cpus field at the SoC class level to define the number of available CPUs per SoC and also introduce a 'num-cpus' property to activate the CPUs configured for the machine. The max_cpus limit of the machine should depend on the SoC definition but, unfortunately, these values are not available when the machine class is initialized. This is the reason why we add a check on num_cpus in the AspeedSoC realize handler. SMP support will be activated when models for such SoCs are implemented. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190618165311.27066-6-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01hw/arm/aspeed: Add RTC to SoCJoel Stanley
All systems have an RTC. The IRQ is hooked up but the model does not use it at this stage. There is no guest code that uses it, so this limitation is acceptable. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190618165311.27066-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01hw: timer: Add ASPEED RTC deviceJoel Stanley
The RTC is modeled to provide time and date functionality. It is initialised at zero to match the hardware. There is no modelling of the alarm functionality, which includes the IRQ line. As there is no guest code to exercise this function that is acceptable for now. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190618165311.27066-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01aspeed: add a per SoC mapping for the memory spaceCédric Le Goater
This will simplify the definition of new SoCs, like the AST2600 which should use a slightly different address space and have a different set of controllers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190618165311.27066-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01aspeed: add a per SoC mapping for the interrupt spaceCédric Le Goater
This will simplify the definition of new SoCs, like the AST2600 which should use a different CPU and a different IRQ number layout. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190618165311.27066-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01i.mx7d: pci: Update PCI IRQ mapping to match HWAndrey Smirnov
Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches that of i.MX6: * INTD/MSI 122 * INTC 123 * INTB 124 * INTA 125 Fix all of the relevant code to reflect that fact. Needed by latest Linux kernels. (Reference: Linux kernel commit 538d6e9d597584e80 from an NXP employee confirming that the datasheet is incorrect and with a report of a test against hardware.) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added ref to kernel commit confirming the datasheet error] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01i.mx7d: Add no-op/unimplemented PCIE PHY IP blockAndrey Smirnov
Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to use PCIE. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01i.mx7d: Add no-op/unimplemented APBH DMA moduleAndrey Smirnov
Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-28i2c: Move bitbang_i2c.h to include/hw/i2c/BALATON Zoltan
The bitbang i2c implementation is also useful for other device models such as DDC in display controllers. Move the header to include/hw/i2c/ to allow it to be used from other device models and adjust users of this include. This also reverts commit 2b4c1125ac which is no longer needed. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 5d1fe4db846ab9be4b77ddb0d43cc74cd200a003.1561028123.git.balaton@eik.bme.hu Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-06-27hw/riscv: Add support for loading a firmwareAlistair Francis
Add support for loading a firmware file for the virt machine and the SiFive U. This can be run with the following command: qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis
Split the common RISC-V boot functions into a seperate file. This allows us to share the common code. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-24vfio-ccw: support async command subregionCornelia Huck
A vfio-ccw device may provide an async command subregion for issuing halt/clear subchannel requests. If it is present, use it for sending halt/clear request to the device; if not, fall back to emulation (as done today). Reviewed-by: Farhan Ali <alifm@linux.ibm.com> Message-Id: <20190613092542.2834-1-cohuck@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-06-24xen: Import other xen/io/*.hAnthony PERARD
A Xen public header have been imported into QEMU (by f65eadb639 "xen: import ring.h from xen"), but there are other header that depends on ring.h which come from the system when building QEMU. This patch resolves the issue of having headers from the system importing a different copie of ring.h. This patch is prompt by the build issue described in the previous patch: 'Revert xen/io/ring.h of "Clean up a few header guard symbols"' ring.h and the new imported headers are moved to "include/hw/xen/interface" as those describe interfaces with a guest. The imported headers are cleaned up a bit while importing them: some part of the file that QEMU doesn't use are removed (description of how to make hypercall in grant_table.h have been removed). Other cleanup: - xen-mapcache.c and xen-legacy-backend.c don't need grant_table.h. - xenfb.c doesn't need event_channel.h. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Paul Durrant <paul.durrant@citrix.com> Message-Id: <20190621105441.3025-3-anthony.perard@citrix.com>
2019-06-24Revert xen/io/ring.h of "Clean up a few header guard symbols"Anthony PERARD
This reverts changes to include/hw/xen/io/ring.h from commit 37677d7db39a3c250ad661d00fb7c3b59d047b1f. Following 37677d7db3 "Clean up a few header guard symbols", QEMU start to fail to build: In file included from ~/xen/tools/../tools/include/xen/io/blkif.h:31:0, from ~/xen/tools/qemu-xen-dir/hw/block/xen_blkif.h:5, from ~/xen/tools/qemu-xen-dir/hw/block/xen-block.c:22: ~/xen/tools/../tools/include/xen/io/ring.h:68:0: error: "__CONST_RING_SIZE" redefined [-Werror] #define __CONST_RING_SIZE(_s, _sz) \ In file included from ~/xen/tools/qemu-xen-dir/hw/block/xen_blkif.h:4:0, from ~/xen/tools/qemu-xen-dir/hw/block/xen-block.c:22: ~/xen/tools/qemu-xen-dir/include/hw/xen/io/ring.h:66:0: note: this is the location of the previous definition #define __CONST_RING_SIZE(_s, _sz) \ The issue is that some public xen headers have been imported (by f65eadb639 "xen: import ring.h from xen") but not all. With the change in the guards symbole, the ring.h header start to be imported twice. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Paul Durrant <paul.durrant@citrix.com> Message-Id: <20190621105441.3025-2-anthony.perard@citrix.com>
2019-06-24xen-bus / xen-block: add support for event channel pollingPaul Durrant
This patch introduces a poll callback for event channel fd-s and uses this to invoke the channel callback function. To properly support polling, it is necessary for the event channel callback function to return a boolean saying whether it has done any useful work or not. Thus xen_block_dataplane_event() is modified to directly invoke xen_block_handle_requests() and the latter only returns true if it actually processes any requests. This also means that the call to qemu_bh_schedule() is moved into xen_block_complete_aio(), which is more intuitive since the only reason for doing a deferred poll of the shared ring should be because there were previously insufficient resources to fully complete a previous poll. Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20190408151617.13025-4-paul.durrant@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2019-06-24xen-bus: allow AioContext to be specified for each event channelPaul Durrant
This patch adds an AioContext parameter to xen_device_bind_event_channel() and then uses aio_set_fd_handler() to set the callback rather than qemu_set_fd_handler(). Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20190408151617.13025-3-paul.durrant@citrix.com> [Call aio_set_fd_handler() with is_external=true] Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2019-06-24xen-bus: use a separate fd for each event channelPaul Durrant
To better support use of IOThread-s it will be necessary to be able to set the AioContext for each XenEventChannel and hence it is necessary to open a separate handle to libxenevtchan for each channel. This patch stops using NotifierList for event channel callbacks, replacing that construct by a list of complete XenEventChannel structures. Each of these now has a xenevtchn_handle pointer in place of the single pointer previously held in the XenDevice structure. The individual handles are opened/closed in xen_device_bind/unbind_event_channel(), replacing the single open/close in xen_device_realize/unrealize(). NOTE: This patch does not add an AioContext parameter to xen_device_bind_event_channel(). That will be done in a subsequent patch. Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20190408151617.13025-2-paul.durrant@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
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