aboutsummaryrefslogtreecommitdiff
path: root/include/tcg
AgeCommit message (Collapse)Author
2023-03-01tcg: Remove TEMP_NORMALRichard Henderson
TEMP_NORMAL is a subset of TEMP_EBB. Promote single basic block temps to single extended basic block. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01tcg: Rename TEMP_LOCAL to TEMP_TBRichard Henderson
Use TEMP_TB as that is more explicit about the default lifetime of the data. While "global" and "local" used to be contrasting, we have more lifetimes than that now. Do not yet rename tcg_temp_local_new_*, just the enum. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64}Richard Henderson
Normally this is automatically handled by the CF_PARALLEL checks with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special case of !PREFIX_LOCK where it always wants the non-atomic version. Split these out so that x86 does not have to roll its own. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tcg: Add tcg_gen_{non}atomic_cmpxchg_i128Richard Henderson
This will allow targets to avoid rolling their own. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tcg: Add guest load/store primitives for TCGv_i128Richard Henderson
These are not yet considering atomicity of the 16-byte value; this is a direct replacement for the current target code which uses a pair of 8-byte operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tcg: Add basic data movement for TCGv_i128Richard Henderson
Add code generation functions for data movement between TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract). Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tcg: Add temp allocation for TCGv_i128Richard Henderson
This enables allocation of i128. The type is not yet usable, as we have not yet added data movement ops. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tcg: Define TCG_TYPE_I128 and related helper macrosRichard Henderson
Begin staging in support for TCGv_i128 with Int128. Define the type enumerator, the typedef, and the helper-head.h macros. This cannot yet be used, because you can't allocate temporaries of this new type. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-03Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell
common-user: Re-enable ppc32 host tcg: Avoid recursion in tcg_gen_mulu2_i32 tcg: Mark tcg helpers noinline to avoid an issue with LTO tcg/arm: Use register pair allocation for qemu_{ld,st}_i64 disas: Enable loongarch disassembler, and fixes tcg/loongarch64: Improve move immediate tcg/loongarch64: Improve add immediate tcg/loongarch64: Improve setcond tcg/loongarch64: Implement movcond tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst tcg/loongarch64: Reorg goto_tb implementation # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmPPO+0dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV93jwgAhG+H5XHtJqF2isCc # a6pYuUWRbhsOFL23FmWKx2O41tHlJ2Seort8M9eIHOu21L9DUJFd291O/4ckiMQM # 13+KH/Kl5fumM+uEkO9YMyplOddmvygdTd5dCi5y349Gi3CgJH3n4HUl0qnioM/7 # Dy3n8JIvYsBp+8jUsLXo1gSl5P1kLMLwJmP68qgy8z8Xly4bDco1Nb2UKb7qKevO # lMr6L+2/ALbKLZ6OU50erdUrlbgNs0eiQyJAfJ47SQ57RGuqF4pZ09+9yRI2FPZt # UlSn+srsec1ieYyM2e5krVWbNcXaj6FouV7CkbgFXoUZt29xA1HTXsso+8vLgDPu # g8vvuw== # =Up0b # -----END PGP SIGNATURE----- # gpg: Signature made Tue 24 Jan 2023 02:01:17 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu: tcg/loongarch64: Reorg goto_tb implementation tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst tcg/loongarch64: Implement movcond tcg/loongarch64: Improve setcond expansion tcg/loongarch64: Introduce tcg_out_addi tcg/loongarch64: Update tcg-insn-defs.c.inc tcg/loongarch64: Optimize immediate loading target/loongarch: Disassemble pcadd* addresses target/loongarch: Disassemble jirl properly target/loongarch: Enable the disassembler for host tcg tcg: Mark tcg helpers noinline to avoid an issue with LTO linux-user: Implment host/ppc/host-signal.h common-user/host/ppc: Implement safe-syscall.inc.S tcg/arm: Use register pair allocation for qemu_{ld,st}_i64 tcg: Avoid recursion in tcg_gen_mulu2_i32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-02tcg: exclude non-memory effecting helpers from instrumentationEmilio Cota
There are actually a whole bunch of helpers that don't affect memory that we shouldn't instrument. They are helpfully identified by the TCG_CALL_NO_SIDE_EFFECTS flag which marks out lookup_tb_ptr as well as a lot of the maths helpers. To avoid the string compare we introduce a new flag for plugin internals so we skip that too. Related: #1381 Signed-off-by: Emilio Cota <cota@braap.org> Message-Id: <20230108164731.61469-4-cota@braap.org> [AJB: updated to skip all no SE plugins, add flag for plugin helper] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230124180127.1881110-34-alex.bennee@linaro.org>
2023-01-23tcg: Avoid recursion in tcg_gen_mulu2_i32Richard Henderson
We have a test for one of TCG_TARGET_HAS_mulu2_i32 or TCG_TARGET_HAS_muluh_i32 being defined, but the test became non-functional when we changed to always define all of these macros. Replace this with a build-time test in tcg_gen_mulu2_i32. Fixes: 25c4d9cc845 ("tcg: Always define all of the TCGOpcode enum members.") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1435 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Move tb_target_set_jmp_target declaration to tcg.hRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Add gen_tb to TCGContextRichard Henderson
This can replace four other variables that are references into the TranslationBlock structure. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Reorg function callsRichard Henderson
Pre-compute the function call layout for each helper at startup. Drop TCG_CALL_DUMMY_ARG, as we no longer need to leave gaps in the op->args[] array. This allows several places to stop checking for NULL TCGTemp, to which TCG_CALL_DUMMY_ARG mapped. For tcg_gen_callN, loop over the arguments once. Allocate the TCGOp for the call early but delay emitting it, collecting arguments first. This allows the argument processing loop to emit code for extensions and have them sequenced before the call. For tcg_reg_alloc_call, loop over the arguments in reverse order, which allows stack slots to be filled first naturally. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Use output_pref wrapper functionRichard Henderson
We will shortly have the possibility of more that two outputs, though only for calls (for which preferences are moot). Avoid direct references to op->output_pref[] when possible. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Vary the allocation size for TCGOpRichard Henderson
We have been allocating a worst case number of arguments to support calls. Instead, allow the size to vary. By default leave space for 4 args, to maximize reuse, but allow calls to increase the number of args to 32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Split patch in two] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221218211832.73312-3-philmd@linaro.org>
2023-01-05tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*()Philippe Mathieu-Daudé
In order to have variable size allocated TCGOp, pass the number of arguments we use (and would allocate) up to tcg_op_alloc(). This alters tcg_emit_op(), tcg_op_insert_before() and tcg_op_insert_after() prototypes. In tcg_op_alloc() ensure the number of arguments is in range. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Extracted from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221218211832.73312-2-philmd@linaro.org>
2023-01-05tcg: Introduce tcg_type_sizeRichard Henderson
Add a helper function for computing the size of a type. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Move TCG_TYPE_COUNT outside enumRichard Henderson
The count is not itself an enumerator. Move it outside to prevent the compiler from considering it with -Wswitch-enum. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Add temp_subindex to TCGTempRichard Henderson
Record the location of a TCGTemp within a larger object. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Move TCG_{LOW,HIGH} to tcg-internal.hRichard Henderson
Move the error-generating fallback from tcg-op.c, and replace "_link_error" with modern QEMU_ERROR markup. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Introduce paired register allocationRichard Henderson
There are several instances where we need to be able to allocate a pair of registers to related inputs/outputs. Add 'p' and 'm' register constraints for this, in order to be able to allocate the even/odd register first or second. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-04accel/tcg: Introduce tb_pc and log_pcRichard Henderson
The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-02tcg: Add tcg_gen_mov_ptrRichard Henderson
Add an interface to perform moves between TCGv_ptr. Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-11Normalize header guard symbol definitionMarkus Armbruster
We commonly define the header guard symbol without an explicit value. Normalize the exceptions. Done with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-4-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-04tcg: Implement tcg_gen_{h,w}swap_{i32,i64}Richard Henderson
Swap half-words (16-bit) and words (32-bit) within a larger value. Mirrors functions of the same names within include/qemu/bitops.h. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: David Miller <dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-5-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau
G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
2022-04-20tcg: Add tcg_constant_ptrRichard Henderson
Similar to tcg_const_ptr, defer to tcg_constant_{i32,i64}. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-20tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCHRichard Henderson
With TCG_OPF_COND_BRANCH, we extended the lifetimes of globals across extended basic blocks. This means that the liveness computed in pass 1 does not kill globals in the same way as normal temps. Introduce TYPE_EBB to match this lifetime, so that we get correct register allocation for the temps that we introduce during the indirect lowering pass. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Fixes: b4cb76e6208 ("tcg: Do not kill globals at conditional branches") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg: Add opcodes for vector nand, nor, eqvRichard Henderson
We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg: Set MAX_OPC_PARAM_IARGS to 7Ziqiao Kong
The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and thus the MAX_OPC_PARAM_IARGS should be 7. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com> Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-02tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4iMatheus Ferst
Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-34-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-11-03Merge remote-tracking branch ↵Richard Henderson
'remotes/berrange/tags/hmp-x-qmp-620-pull-request' into staging Initial conversion of HMP debugging commands to QMP This introduces a new policy that all HMP commands will be converted to have QMP equivalents, marked unstable if no formal QAPI modelling is intended to be done. New unstable commands are added as follows: - HMP "info roms" => QMP "x-query-roms" - HMP "info profile" => QMP "x-query-profile" - HMP "info numa" => QMP "x-query-numa" - HMP "info usb" => QMP "x-query-usb" - HMP "info rdma" => QMP "x-query-rdma" - HMP "info ramblock" => QMP "x-query-ramblock" - HMP "info irq" => QMP "x-query-irq" - HMP "info jit" => QMP "x-query-jit" - HMP "info opcount" => QMP "x-query-opcount" # gpg: Signature made Tue 02 Nov 2021 01:54:28 PM EDT # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] * remotes/berrange/tags/hmp-x-qmp-620-pull-request: qapi: introduce x-query-opcount QMP command qapi: introduce x-query-jit QMP command qapi: introduce x-query-irq QMP command qapi: introduce x-query-ramblock QMP command qapi: introduce x-query-rdma QMP command qapi: introduce x-query-usb QMP command qapi: introduce x-query-numa QMP command qapi: introduce x-query-profile QMP command qapi: introduce x-query-roms QMP command docs/devel: document expectations for HMP commands in the future docs/devel: add example of command returning unstructured text docs/devel: document expectations for QAPI data modelling for QMP monitor: introduce HumanReadableText and HMP support docs/devel: update error handling guidance for HMP commands docs/devel: tweak headings in monitor command docs docs/devel: rename file for writing monitor commands monitor: make hmp_handle_error return a boolean monitor: remove 'info ioapic' HMP command Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02qapi: introduce x-query-opcount QMP commandDaniel P. Berrangé
This is a counterpart to the HMP "info opcount" command. It is being added with an "x-" prefix because this QMP command is intended as an ad hoc debugging tool and will thus not be modelled in QAPI as fully structured data, nor will it have long term guaranteed stability. The existing HMP command is rewritten to call the QMP command. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2021-11-02qapi: introduce x-query-jit QMP commandDaniel P. Berrangé
This is a counterpart to the HMP "info jit" command. It is being added with an "x-" prefix because this QMP command is intended as an ad hoc debugging tool and will thus not be modelled in QAPI as fully structured data, nor will it have long term guaranteed stability. The existing HMP command is rewritten to call the QMP command. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2021-11-02tcg: Add helper_unaligned_{ld,st} for user-only sigbusRichard Henderson
To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-13tcg: Move helper_*_mmu decls to tcg/tcg-ldst.hRichard Henderson
These functions have been replaced by cpu_*_mmu as the most proper interface to use from target code. Hide these declarations from code that should not use them. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-13accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.hRichard Henderson
The previous placement in tcg/tcg.h was not logical. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-12accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is validAlex Bennée
Coverity doesn't know enough about how we have arranged our plugin TCG ops to know we will always have incremented insn_idx before injecting the callback. Let us assert it for the benefit of Coverity and protect ourselves from accidentally breaking the assumption and triggering harder to grok errors deeper in the code if we attempt a negative indexed array lookup. However to get to this point we re-factor the code and remove the second hand instruction boundary detection in favour of scanning the full set of ops and using the existing INDEX_op_insn_start to cleanly detect when the instruction has started. As we no longer need the plugin specific list of ops we delete that. My initial benchmarks shows no discernible impact of dropping the plugin specific ops list. Fixes: Coverity 1459509 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210917162332.3511179-12-alex.bennee@linaro.org>
2021-10-05tcg: Split out MemOpIdx to exec/memopidx.hRichard Henderson
Move this code from tcg/tcg.h to its own header. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson
We're about to move this out of tcg.h, so rename it as we did when moving MemOp. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg: add dup_const_tl wrapperPhilipp Tomsich
dup_const always generates a uint64_t, which may exceed the size of a target_long (generating warnings with recent-enough compilers). To ensure that we can use dup_const both for 64bit and 32bit targets, this adds dup_const_tl, which either maps back to dup_const (for 64bit targets) or provides a similar implementation using 32bit constants. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Message-Id: <20211003214243.3813425-1-philipp.tomsich@vrull.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg: Remove tcg_global_reg_new definesBin Meng
Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"), these tcg_global_reg_new_ macros are not used anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21tcg: Rename helper_atomic_*_mmu and provide for user-onlyRichard Henderson
Always provide the atomic interface using TCGMemOpIdx oi and uintptr_t retaddr. Rename from helper_* to cpu_* so as to (mostly) match the exec/cpu_ldst.h functions, and to emphasize that they are not callable from TCG directly. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson
Since 6eea04347eb6, all tcg backends support goto_ptr. Remove the conditional, making support mandatory. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Move tb_phys_invalidate_count to tb_ctxRichard Henderson
We can call do_tb_phys_invalidate from an iocontext, which has no per-thread tcg_ctx. Move this to tb_ctx, which is global. The actual update still takes place with a lock held, so only an atomic set is required, not an atomic increment. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/457 Tested-by: Viktor Ashirov <vashirov@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Bake tb_destroy() into tcg_region_treeLiren Wei
The function is called only at tcg_gen_code() when duplicated TBs are translated by different threads, and when the tcg_region_tree is reset. Bake it into the underlying GTree as its value destroy function to unite these situations. Also remove tcg_region_tree_traverse() which now becomes useless. Signed-off-by: Liren Wei <lrwei@bupt.edu.cn> Message-Id: <8dc352f08d038c4e7a1f5f56962398cdc700c3aa.1625404483.git.lrwei@bupt.edu.cn> [rth: Name the new tb_tc_cmp parameter correctly.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-29tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson
Implement the new semantics in the fallback expansion. Change all callers to supply the flags that keep the semantics unchanged locally. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-29tcg: Add flags argument to bswap opcodesRichard Henderson
This will eventually simplify front-end usage, and will allow backends to unset TCG_TARGET_HAS_MEMORY_BSWAP without loss of optimization. The argument is added during expansion, not currently exposed to the front end translators. The backends currently only support a flags value of either TCG_BSWAP_IZ, or (TCG_BSWAP_IZ | TCG_BSWAP_OZ), since they all require zero top bytes and leave them that way. At the existing call sites we pass in (TCG_BSWAP_IZ | TCG_BSWAP_OZ), except for the flags-ignored cases of a 32-bit swap of a 32-bit value and or a 64-bit swap of a 64-bit value, where we pass 0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-08 17:02:17 +0000