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2017-03-14pseries: Don't expose PCIe extended config space on older machine typesDavid Gibson
bb9986452 "spapr_pci: Advertise access to PCIe extended config space" allowed guests to access the extended config space of PCI Express devices via the PAPR interfaces, even though the paravirtualized bus mostly acts like plain PCI. However, that patch enabled access unconditionally, including for existing machine types, which is an unwise change in behaviour. This patch limits the change to pseries-2.9 (and later) machine types. Suggested-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-10i386: Change stepping of Haswell to non-blacklisted valueEduardo Habkost
glibc blacklists TSX on Haswell CPUs with model==60 and stepping < 4. To make the Haswell CPU model more useful, make those guests actually use TSX by changing CPU stepping to 4. References: * glibc commit 2702856bf45c82cf8e69f2064f5aa15c0ceb6359 https://sourceware.org/git/?p=glibc.git;a=commit;h=2702856bf45c82cf8e69f2064f5aa15c0ceb6359 Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170309181212.18864-4-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-03-04Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170303' ↵Peter Maydell
into staging ppc patch queuye for 2017-03-03 This will probably be my last pull request before the hard freeze. It has some new work, but that has all been posted in draft before the soft freeze, so I think it's reasonable to include in qemu-2.9. This batch has: * A substantial amount of POWER9 work * Implements the legacy (hash) MMU for POWER9 * Some more preliminaries for implementing the POWER9 radix MMU * POWER9 has_work * Basic POWER9 compatibility mode handling * Removal of some premature tests * Some cleanups and fixes to the existing MMU code to make the POWER9 work simpler * A bugfix for TCG multiply adds on power * Allow pseries guests to access PCIe extended config space This also includes a code-motion not strictly in ppc code - moving getrampagesize() from ppc code to exec.c. This will make some future VFIO improvements easier, Paolo said it was ok to merge via my tree. # gpg: Signature made Fri 03 Mar 2017 03:20:36 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.9-20170303: target/ppc: rewrite f[n]m[add,sub] using float64_muladd spapr: Small cleanup of PPC MMU enums spapr_pci: Advertise access to PCIe extended config space target/ppc: Rework hash mmu page fault code and add defines for clarity target/ppc: Move no-execute and guarded page checking into new function target/ppc: Add execute permission checking to access authority check target/ppc: Add Instruction Authority Mask Register Check hw/ppc/spapr: Add POWER9 to pseries cpu models target/ppc/POWER9: Add cpu_has_work function for POWER9 target/ppc/POWER9: Add POWER9 pa-features definition target/ppc/POWER9: Add POWER9 mmu fault handler target/ppc: Don't gen an SDR1 on POWER9 and rework register creation target/ppc: Add patb_entry to sPAPRMachineState target/ppc/POWER9: Add POWERPC_MMU_V3 bit powernv: Don't test POWER9 CPU yet exec, kvm, target-ppc: Move getrampagesize() to common code target/ppc: Add POWER9/ISAv3.00 to compat_table Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-04ppc: avoid typedef redefinitionsPaolo Bonzini
These cause compilation failures on CentOS 6 or other operating systems with older GCCs. Cc: David Gibson <dgibson@redhat.com> Cc: qemu-ppc@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1488558530-21016-3-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03x86: Work around SMI migration breakagesDr. David Alan Gilbert
Migration from a 2.3.0 qemu results in a reboot on the receiving QEMU due to a disagreement about SM (System management) interrupts. 2.3.0 didn't have much SMI support, but it did set CPU_INTERRUPT_SMI and this gets into the migration stream, but on 2.3.0 it never got delivered. ~2.4.0 SMI interrupt support was added but was broken - so that when a 2.3.0 stream was received it cleared the CPU_INTERRUPT_SMI but never actually caused an interrupt. The SMI delivery was recently fixed by 68c6efe07a, but the effect now is that an incoming 2.3.0 stream takes the interrupt it had flagged but it's bios can't actually handle it(I think partly due to the original interrupt not being taken during boot?). The consequence is a triple(?) fault and a reboot. Tested from: 2.3.1 -M 2.3.0 2.7.0 -M 2.3.0 2.8.0 -M 2.3.0 2.8.0 -M 2.8.0 This corresponds to RH bugzilla entry 1420679. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170223133441.16010-1-dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio, pc: fixes, features virtio support for region caches broke a bunch of stuff - fixing most of it though it's not ideal. Still pondering the right way to fix it. New: VM gen ID and hotplug for PXB. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Thu 02 Mar 2017 06:19:17 GMT # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: hw/pxb-pcie: fix PCI Express hotplug support tests/acpi: update DSDT after last patch acpi: simplify _OSC virtio: unbreak virtio-pci with IOMMU after caching ring translations virtio: add missing region cache init in virtio_load() virtio: invalidate memory in vring_set_avail_event() virtio: guard vring access when setting notification virtio: check for vring setup in virtio_queue_empty MAINTAINERS: Add VM Generation ID entries tests: Move reusable ACPI code into a utility file qmp/hmp: add query-vm-generation-id and 'info vm-generation-id' commands ACPI: Add Virtual Machine Generation ID support ACPI: Add vmgenid blob storage to the build tables docs: VM Generation ID device description linker-loader: Add new 'write pointer' command Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03target/ppc: Add patb_entry to sPAPRMachineStateSuraj Jitindar Singh
ISA v3.00 adds the idea of a partition table which is used to store the address translation details for all partitions on the system. The partition table consists of double word entries indexed by partition id where the second double word contains the location of the process table in guest memory. The process table is registered by the guest via a h-call. We need somewhere to store the address of the process table so we add an entry to the sPAPRMachineState struct called patb_entry to represent the second doubleword of a single partition table entry corresponding to the current guest. We need to store this value so we know if the guest is using radix or hash translation and the location of the corresponding process table in guest memory. Since we only have a single guest per qemu instance, we only need one entry. Since the partition table is technically a hypervisor resource we require that access to it is abstracted by the virtual hypervisor through the get_patbe() call. Currently the value of the entry is never set (and thus defaults to 0 indicating hash), but it will be required to both implement POWER9 kvm support and tcg radix support. We also add this field to be migrated as part of the sPAPRMachineState as we will need it on the receiving side as the guest will never tell us this information again and we need it to perform translation. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-02Merge remote-tracking branch 'remotes/elmarco/tags/leak-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Wed 01 Mar 2017 09:02:53 GMT # gpg: using RSA key 0xDAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/leak-pull-request: (28 commits) tests: fix virtio-blk-test leaks tests: add specialized device_find function tests: fix usb-test leaks tests: allows to run single test in usb-hcd-ehci-test usb: release the created buses bus: do not unref hotplug handler tests: fix virtio-9p-test leaks tests: fix virtio-scsi-test leak tests: fix e1000e leaks tests: fix i440fx-test leaks tests: fix e1000-test leak tests: fix tco-test leaks tests: fix eepro100-test leak pc: pcihp: avoid adding ACPI_PCIHP_PROP_BSEL twice tests: fix ipmi-bt-test leak tests: fix ipmi-kcs-test leak tests: fix bios-tables-test leak tests: fix hd-geo-test leaks tests: fix ide-test leaks tests: fix vhost-user-test leaks ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-02Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170301' ↵Peter Maydell
into staging ppc patch queue for 2017-03-01 I was hoping to get this pull request squeezed in before the soft freeze, but I ran into some difficulties during testing. Everything here was at least posted before the soft freeze, so I'm hoping we can still merge it for 2.9. The biggest things here are: * Cleanups to handling of hashed page tables, that will make adding support for the POWER9 MMU easier * Cleanups to the XICS interrupt controller that will make implementing the powernv machine easier * TCG implementation of extended overflow and carry handling for POWER9 It also includes: * Increasing the CPU limit for pseries to 1024 vCPUs * Generating proper OF node names in qemu (making hotplug and coldplug logic closer together) # gpg: Signature made Wed 01 Mar 2017 04:43:06 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.9-20170301: (50 commits) Add PowerPC 32-bit guest memory dump support ppc/xics: rename 'ICPState *' variables to 'icp' ppc/xics: move InterruptStatsProvider to the sPAPR machine ppc/xics: move ics-simple post_load under the machine ppc/xics: remove the XICSState classes ppc/xics: export the XICS init routines ppc/xics: move the ICP array under the sPAPR machine ppc/xics: register the reset handler of ICP objects ppc/xics: simplify spapr_dt_xics() interface ppc/xics: use the QOM interface to grab an ICP ppc/xics: move the cpu_setup() handler under the ICPState class ppc/xics: simplify the cpu_setup() handler ppc/xics: move kernel_xics_fd out of KVMXICSState ppc/xics: extend the QOM interface to handle ICPs ppc/xics: remove the XICS list of ICS ppc/xics: register the reset handler of ICS objects ppc/xics: remove xics_find_source() ppc/xics: use the QOM interface to resend irqs ppc/xics: use the QOM interface to get irqs ppc/xics: use the QOM interface under the sPAPR machine ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-02ACPI: Add Virtual Machine Generation ID supportBen Warren
This implements the VM Generation ID feature by passing a 128-bit GUID to the guest via a fw_cfg blob. Any time the GUID changes, an ACPI notify event is sent to the guest The user interface is a simple device with one parameter: - guid (string, must be "auto" or in UUID format xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx) Signed-off-by: Ben Warren <ben@skyportsystems.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-03-02ACPI: Add vmgenid blob storage to the build tablesBen Warren
This allows them to be centrally initialized and destroyed The "AcpiBuildTables.vmgenid" array will be used to construct the "etc/vmgenid_guid" fw_cfg blob. Its contents will be linked into fw_cfg after being built on the pc_machine_done() -> acpi_setup() -> acpi_build() call path, and dropped without use on the subsequent, guest triggered, acpi_build_update() -> acpi_build() call path. Signed-off-by: Ben Warren <ben@skyportsystems.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-03-02linker-loader: Add new 'write pointer' commandBen Warren
This is similar to the existing 'add pointer' functionality, but instead of instructing the guest (BIOS or UEFI) to patch memory, it instructs the guest to write the pointer back to QEMU via a writeable fw_cfg file. Signed-off-by: Ben Warren <ben@skyportsystems.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-03-01Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block layer patches # gpg: Signature made Tue 28 Feb 2017 20:35:32 GMT # gpg: using RSA key 0x7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (46 commits) block: Add Error parameter to bdrv_append() block: Add Error parameter to bdrv_set_backing_hd() block: Assertions for resize permission block: Assertions for write permissions block: Pass BdrvChild to bdrv_aligned_preadv/pwritev and copy-on-read tests: Remove FIXME comments nbd/server: Use real permissions for NBD exports migration/block: Use real permissions hmp: Request permissions in qemu-io commit: Add filter-node-name to block-commit mirror: Add filter-node-name to blockdev-mirror stream: Use real permissions in streaming block job mirror: Use real permissions in mirror/active commit block job blockjob: Factor out block_job_remove_all_bdrv() block: Allow backing file links in change_parent_backing_link() block: BdrvChildRole.attach/detach() callbacks block: Fix pending requests check in bdrv_append() backup: Use real permissions in backup block job commit: Use real permissions for HMP 'commit' commit: Use real permissions in commit block job ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-01Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20170228-1' into staging target-arm queue: * raspi2: add gpio controller and sdhost controller, with the wiring so the guest can switch which controller the SD card is attached to (this is sufficient to get raspbian kernels to boot) * GICv3: support state save/restore from KVM * update Linux headers to 4.11 * refactor and QOMify the ARMv7M container object # gpg: Signature made Tue 28 Feb 2017 17:11:49 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170228-1: (21 commits) bcm2835: add sdhost and gpio controllers bcm2835_gpio: add bcm2835 gpio controller hw/sd: add card-reparenting function qdev: Have qdev_set_parent_bus() handle devices already on a bus hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers target-arm: Add GICv3CPUState in CPUARMState struct hw/intc/arm_gicv3_kvm: Implement get/put functions hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate update Linux headers to 4.11 update-linux-headers: update for 4.11 stm32f205: Rename 'nvic' local to 'armv7m' stm32f205: Create armv7m object without using armv7m_init() armv7m: Split systick out from NVIC armv7m: Don't put core v7M devices under CONFIG_STELLARIS armv7m: Make bitband device take the address space to access armv7m: Make NVIC expose a memory region rather than mapping itself armv7m: Make ARMv7M object take memory region link armv7m: Use QOMified armv7m object in armv7m_init() armv7m: QOMify the armv7m container armv7m: Move NVICState struct definition into header ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-01ppc/xics: move InterruptStatsProvider to the sPAPR machineCédric Le Goater
It provides a better monitor output of the ICP and ICS objects, else the objects are printed out of order. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: move ics-simple post_load under the machineCédric Le Goater
The ICS object uses a post_load() handler which is implicitly relying on the fact that the internal state of the ICS and ICP objects has been restored but this is not guaranteed. So, let's move the code under the post_load() handler of the machine where we know the objects have been fully restored. The icp_resend() handler of the XICSFabric QOM interface is also removed as it is now obsolete. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: remove the XICSState classesCédric Le Goater
The XICSState classes are not used anymore. They have now been fully deprecated by the XICSFabric QOM interface. Do the cleanups. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: export the XICS init routinesCédric Le Goater
There is nothing left related to the XICS object in the realize functions of the KVMXICSState and XICSState class. So adapt the interfaces to call these routines directly from the sPAPR machine init sequence. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: move the ICP array under the sPAPR machineCédric Le Goater
This is the last step to remove the XICSState abstraction and have the machine hold all the objects related to interrupts : ICSs and ICPs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: simplify spapr_dt_xics() interfaceCédric Le Goater
spapr_dt_xics() only needs the number of servers to build the device tree nodes. Let's change the routine interface to reflect that. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: use the QOM interface to grab an ICPCédric Le Goater
Also introduce a xics_icp_get() helper to simplify the changes. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: move the cpu_setup() handler under the ICPState classCédric Le Goater
The cpu_setup() handler is currently under the XICSState class but it really belongs under ICPState as it is setting up an individual vCPU. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: simplify the cpu_setup() handlerCédric Le Goater
The cpu_setup() handler currently takes a 'XICSState *' argument to grab the kernel ICP file descriptor. This interface can be simplified by using the 'xics' backlink of the ICP object. This change is also required by subsequent patches which makes use of the QOM interface for XICS. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: extend the QOM interface to handle ICPsCédric Le Goater
Let's add two new handlers for ICPs. One is to get an ICP object from a server number and a second is to resend the irqs when needed. The icp_resend() handler is a temporary workaround needed by the ics-simple post_load() handler. It will be removed when the post_load portion can be done at the machine level. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: remove the XICS list of ICSCédric Le Goater
This is not used anymore. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: remove xics_find_source()Cédric Le Goater
It is not used anymore now that we have the QOM interface for XICS. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: use the QOM interface to resend irqsCédric Le Goater
Also change the ICPState 'xics' backlink to be a XICSFabric, this removes the need of using qdev_get_machine() to get the QOM interface in some of the routines. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: use the QOM interface to get irqsCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: use the QOM interface under the sPAPR machineCédric Le Goater
Add 'ics_get' and 'ics_resend' handlers to the sPAPR machine. These are relatively simple for a single ICS. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: introduce a XICSFabric QOM interface to handle ICSsCédric Le Goater
This interface provides two simple handlers. One is to get an ICS (Interrupt Source Controller) object from an irq number and a second to resend the irqs when needed. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: store the ICS object under the sPAPR machineCédric Le Goater
A list of ICS objects was introduced under the XICS object for the PowerNV machine but, for the sPAPR machine, it brings extra complexity as there is only a single ICS. To simplify the code, let's add the ICS pointer under the sPAPR machine and try to reduce the use of this list where possible. Also, change the xics_spapr_*() routines to use an ICS object instead of an XICSState and change their name to reflect that these are specific to the sPAPR ICS object. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: remove set_nr_servers() handler from XICSStateClassCédric Le Goater
Today, the ICP (Interrupt Controller Presenter) objects are created by the 'nr_servers' property handler of the XICS object and a class handler. They are realized in the XICS object realize routine. Let's simplify the process by creating the ICP objects along with the XICS object at the machine level. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01ppc/xics: remove set_nr_irqs() handler from XICSStateClassCédric Le Goater
Today, the ICS (Interrupt Controller Source) object is created and realized by the init and realize routines of the XICS object, but some of the parameters are only known at the machine level. These parameters are passed from the sPAPR machine to the ICS object in a rather convoluted way using property handlers and a class handler of the XICS object. The number of irqs required to allocate the IRQ state objects in the ICS realize routine is one of them. Let's simplify the process by creating the ICS object along with the XICS object at the machine level and link the ICS into the XICS list of ICSs at this level also. In the sPAPR machine, there is only a single ICS but that will change with the PowerNV machine. Also, QOMify the creation of the objects and get rid of the superfluous code. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01xics: XICS should not be a SysBusDeviceDavid Gibson
Currently xics - the component of the IBM POWER interrupt controller representing the overall interrupt fabric / architecture is represented as a descendent of SysBusDevice. However, this is not really correct - the xics presents nothing in MMIO space so it should be an "unattached" device in the current QOM model. Since this device will always be created by the machine type, not created specifically from the command line, and because it has no migrated state it should be safe to move it around the device composition tree. Therefore this patch changes it to a descendent of TYPE_DEVICE, and makes it an unattached device. So that its reset handler still gets called correctly, we add a qdev_set_parent_bus() to attach it to sysbus. It's not really clear that's correct (instead of using register_reset()) but it appears to a common technique. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [clg corrected problems with reset] Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg folded together and updated commit message] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01spapr/pci: populate PCI DT in reverse orderGreg Kurz
Since commit 1d2d974244c6 "spapr_pci: enumerate and add PCI device tree", QEMU populates the PCI device tree in the opposite order compared to SLOF. Before 1d2d974244c6: Populating /pci@800000020000000 00 0000 (D) : 1af4 1000 virtio [ net ] 00 0800 (D) : 1af4 1001 virtio [ block ] 00 1000 (D) : 1af4 1009 virtio [ network ] Populating /pci@800000020000000/unknown-legacy-device@2 7e5294b8 : /pci@800000020000000 7e52b998 : |-- ethernet@0 7e52c0c8 : |-- scsi@1 7e52c7e8 : +-- unknown-legacy-device@2 ok Since 1d2d974244c6: Populating /pci@800000020000000 00 1000 (D) : 1af4 1009 virtio [ network ] Populating /pci@800000020000000/unknown-legacy-device@2 00 0800 (D) : 1af4 1001 virtio [ block ] 00 0000 (D) : 1af4 1000 virtio [ net ] 7e5e8118 : /pci@800000020000000 7e5ea6a0 : |-- unknown-legacy-device@2 7e5eadb8 : |-- scsi@1 7e5eb4d8 : +-- ethernet@0 ok This behaviour change is not actually a bug since no assumptions should be made on DT ordering. But it has no real justification either, other than being the consequence of the way fdt_add_subnode() inserts new elements to the front of the FDT rather than adding them to the tail. This patch reverts to the historical SLOF ordering by walking PCI devices in reverse order. This reconciles pseries with x86 machine types behavior. It is expected to make things easier when porting existing applications to power. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> (slight update to the changelog) Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01PCI: add missing classes in pci_ids.h to build device treeLaurent Vivier
To allow QEMU to add PCI entries in device tree, we must have a more exhaustive list of PCI class IDs. This patch synchronizes as much as possible with pci_ids.h and add some missing IDs from SLOF. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01tests: fix ptimer leaksMarc-André Lureau
Spotted by ASAN. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-28Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170228' into stagingPeter Maydell
Network boot for s390x. More information (and instructions for building a s390-netboot.img) can be found at http://wiki.qemu-project.org/Features/S390xNetworkBoot # gpg: Signature made Tue 28 Feb 2017 11:27:18 GMT # gpg: using RSA key 0xDECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20170228: pc-bios/s390-ccw.img: rebuild image pc-bios/s390-ccw: Use the ccw bios to start the network boot s390x/ipl: Load network boot image s390x/ipl: Extend S390IPLState to support network boot elf-loader: Allow late loading of elf Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28hw/block: Introduce share-rw qdev propertyKevin Wolf
By default, don't allow another writer for block devices that are attached to a guest device. For the cases where this setup is intended (e.g. using a cluster filesystem on the disk), the new option can be used to allow it. This change affects only devices using DEFINE_BLOCK_PROPERTIES(). Devices directly using DEFINE_PROP_DRIVE() still accept writers unconditionally. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Acked-by: Fam Zheng <famz@redhat.com>
2017-02-28hw/block: Request permissionsKevin Wolf
This makes all device emulations with a qdev drive property request permissions on their BlockBackend. The only thing we block at this point is resizing images for some devices that can't support it. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Acked-by: Fam Zheng <famz@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
2017-02-28bcm2835: add sdhost and gpio controllersClement Deschamps
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform. For supporting the SD controller selection (alternate function of GPIOs 48-53), the bcm2835_gpio now exposes an sdbus. It also has a link to both the sdbus of sdhci and sdhost controllers, and the card is reparented from one bus to another when the alternate function of GPIOs 48-53 is modified. Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1488293711-14195-5-git-send-email-peter.maydell@linaro.org Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28bcm2835_gpio: add bcm2835 gpio controllerClement Deschamps
This adds the BCM2835 GPIO controller. It currently implements: - The 54 GPIOs as outputs (qemu_irq) - The SD controller selection via alternate function of GPIOs 48-53 Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1488293711-14195-4-git-send-email-peter.maydell@linaro.org Message-id: 20170224164021.9066-4-clement.deschamps@antfield.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28hw/sd: add card-reparenting functionClement Deschamps
Provide a new function sdbus_reparent_card() in sd core for reparenting a card from a SDBus to another one. This function is required by the raspi platform, where the two SD controllers can be dynamically switched. Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1488293711-14195-3-git-send-email-peter.maydell@linaro.org Message-id: 20170224164021.9066-3-clement.deschamps@antfield.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added a doc comment to the header file; changed to use new behaviour of qdev_set_parent_bus()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstateVijaya Kumar K
To Save and Restore ICC_SRE_EL1 register introduce vmstate subsection and load only if non-zero. Also initialize icc_sre_el1 with to 0x7 in pre_load function. Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 1487850673-26455-3-git-send-email-vijay.kilari@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28stm32f205: Create armv7m object without using armv7m_init()Peter Maydell
Switch the stm32f205 SoC to create the armv7m object directly rather than via the armv7m_init() wrapper. This fits better with the SoC model's very QOMified design. In particular this means we can push loading the guest image out to the top level board code where it belongs, rather than the SoC object having a QOM property for the filename to load. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-11-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Split systick out from NVICPeter Maydell
The SysTick timer isn't really part of the NVIC proper; we just modelled it that way back when we couldn't easily have devices that only occupied a small chunk of a memory region. Split it out into its own device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Make bitband device take the address space to accessPeter Maydell
Instead of the bitband device doing a cpu_physical_memory_read/write, make it take a MemoryRegion which specifies where it should be accessing, and use address_space_read/write to access the corresponding AddressSpace. Since this entails pretty much a rewrite, convert away from old_mmio in the process. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Make ARMv7M object take memory region linkPeter Maydell
Make the ARMv7M object take a memory region link which it uses to wire up the bitband rather than having them always put themselves in the system address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-6-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: QOMify the armv7m containerPeter Maydell
Create a proper QOM object for the armv7m container, which holds the CPU, the NVIC and the bitband regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Move NVICState struct definition into headerPeter Maydell
Move the NVICState struct definition into a header, so we can embed it into other QOM objects like SoCs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
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