aboutsummaryrefslogtreecommitdiff
path: root/include/hw
AgeCommit message (Collapse)Author
2024-02-22hw/ide: Stop exposing internal.h to non-IDE filesThomas Huth
include/hw/ide/internal.h is currently included by include/hw/ide/pci.h and thus exposed to a lot of files that are not part of the IDE subsystem. Stop including internal.h there and use the appropriate new headers ide-bus.h and ide-dma.h instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20240220085505.30255-8-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Remove the include/hw/ide.h legacy fileThomas Huth
There was only one prototype left in this legacy file. Move it to ide-dev.h to finally get rid of it. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20240220085505.30255-7-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Move IDE bus related definitions to a new header ide-bus.hThomas Huth
Let's consolidate the public IDE bus related functions in a separate header. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240220085505.30255-6-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Move IDE device related definitions to ide-dev.hThomas Huth
Untangle internal.h by moving public IDE device related definitions to ide-dev.h. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240220085505.30255-5-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Move IDE DMA related definitions to a separate header ide-dma.hThomas Huth
These definitions are required outside of the hw/ide/ code, too, so lets's move them from internal.h to a new header called ide-dma.h. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240220085505.30255-4-thuth@redhat.com> [PMD: Use IDEDMAOps typedef in struct IDEDMA] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Add the possibility to disable the CompactFlash device in the buildThomas Huth
For distros like downstream RHEL, it would be helpful to allow to disable the CompactFlash device. For making this possible, we need a separate Kconfig switch for this device, and the code should reside in a separate file. Let's also introduce a new header ide-dev.h which can be used to collect definitions related to IDE devices. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20240220085505.30255-2-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/acpi/ich9_tco: Include missing 'migration/vmstate.h' headerPhilippe Mathieu-Daudé
We need the VMStateDescription structure definition from "migration/vmstate.h" in order to declare vmstate_tco_io_sts. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240219141412.71418-4-philmd@linaro.org>
2024-02-22hw/acpi/cpu: Use CPUState typedefPhilippe Mathieu-Daudé
QEMU coding style recommend using structure typedefs: https://www.qemu.org/docs/master/devel/style.html#typedefs Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240126220407.95022-2-philmd@linaro.org>
2024-02-22hw/acpi: Include missing 'qapi/qapi-types-acpi.h' generated headerPhilippe Mathieu-Daudé
ACPIOSTInfo is a QAPI generated structure: $ git grep -w ACPIOSTInfo qapi/acpi.json:81:# @ACPIOSTInfo: qapi/acpi.json:99:{ 'struct': 'ACPIOSTInfo', qapi/acpi.json:109:# Return a list of ACPIOSTInfo for devices that support status Include the "qapi/qapi-types-acpi.h" header to avoid the following errors when including "hw/acpi/cpu.h" or "hw/acpi/memory_hotplug.h" elsewhere: include/hw/acpi/cpu.h:67:52: error: unknown type name 'ACPIOSTInfoList' void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list); ^ include/hw/acpi/memory_hotplug.h:51:55: error: unknown type name 'ACPIOSTInfoList' void acpi_memory_ospm_status(MemHotplugState *mem_st, ACPIOSTInfoList ***list); ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240219141412.71418-2-philmd@linaro.org>
2024-02-22hw/i386/pc: Confine system flash handling to pc_sysfwBernhard Beschow
Rather than distributing PC system flash handling across three files, let's confine it to one. Now, pc_system_firmware_init() creates, configures and cleans up the system flash which makes the code easier to understand. It also avoids the extra call to pc_system_flash_cleanup_unused() in the Xen case. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240208220349.4948-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/i386/pc: Defer smbios_set_defaults() to machine_doneBernhard Beschow
Handling most of smbios data generation in the machine_done notifier is similar to how the ARM virt machine handles it which also calls smbios_set_defaults() there. The result is that all pc machines are freed from explicitly worrying about smbios setup. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240208220349.4948-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/i386/pc: Merge pc_guest_info_init() into pc_machine_initfn()Bernhard Beschow
Resolves redundant code in the piix and q35 machines. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240208220349.4948-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/i386/x86: Turn apic_xrupt_override into class attributeBernhard Beschow
The attribute isn't user-changeable and only true for pc-based machines. Turn it into a class attribute which allows for inlining pc_guest_info_init() into pc_machine_initfn(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240208220349.4948-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/i386/pc: Store pointers to IDE buses in PCMachineStatePeter Maydell
Add the two IDE bus BusState pointers to the set we keep in PCMachineState. This allows us to avoid passing them to pc_cmos_init(), and also will allow a refactoring of how we call pc_cmos_init_late(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMD: Do not zero-init pcms->idebus[] again] Message-ID: <20240220160622.114437-2-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/tricore/testboard: Use qdev_new() instead of QOM basic APIPhilippe Mathieu-Daudé
Prefer QDev API for QDev objects, avoid the underlying QOM layer. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20240216110313.17039-5-philmd@linaro.org>
2024-02-22hw/ppc/ppc4xx_pci: Extract PCI host definitions to hw/pci-host/ppc4xx.hPhilippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240215105017.57748-3-philmd@linaro.org>
2024-02-22hw/sysbus: Inline and remove sysbus_add_io()Philippe Mathieu-Daudé
sysbus_add_io(...) is a simple wrapper to memory_region_add_subregion(get_system_io(), ...). It is used in 3 places; inline it directly. Rationale: we want to move to an explicit I/O bus, rather that an implicit one. Besides in heterogeneous setup we can have more than one I/O bus. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20240216150441.45681-1-philmd@linaro.org> [PMD: Include missing "exec/address-spaces.h" header] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/input/pckbd: Open-code i8042_setup_a20_line() wrapperPhilippe Mathieu-Daudé
Since the named GPIO lines are a "public" interface to the device, we can directly call qdev_connect_gpio_out_named(), making it consistent with how the other A20 input source (port92) is wired. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Message-Id: <20211218130437.1516929-6-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-21hw/riscv/virt.h: correct typosManos Pitsidianakis
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-21hw/net/npcm_gmac.h: correct typosManos Pitsidianakis
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-21hw/cxl/cxl_device.h: correct typosManos Pitsidianakis
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-21hw/arm/omap.h: correct typosManos Pitsidianakis
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> (mjt: fix comment style as suggested by Philippe) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-20hw/i386/acpi: Declare pc_madt_cpu_entry() in 'acpi-common.h'Philippe Mathieu-Daudé
Since pc_madt_cpu_entry() is only used by: - hw/i386/acpi-build.c // single call - hw/i386/acpi-common.c // definition there is no need to expose it outside of hw/i386/. Declare it in "acpi-common.h". acpi-build.c doesn't need "hw/i386/pc.h" anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-20hw/timer: Move HPET_INTCAP definition to "hpet.h"Philippe Mathieu-Daudé
HPET_INTCAP is specific to TYPE_HPET, so define it there. hpet.c doesn't need to include "hw/i386/pc.h" anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-20Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
* Some hw/isa cleanups * Fixes for x86 CPUID * Cleanups for configure, hw/isa and x86 # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmXPW5sUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroO1Mgf/USSqZxAyS1tyutpVslKmQjCyUiNW # xEuHhAqoTz4Xg/8Q1J9aCcs2hdpBx2ULEQryUiTlH3LPLy3j9lGxMfg9Ma65mPVg # KOSm/vfnw2VPXav8MJVNbm0gSI5fPmprRYgFi4TrkknmKnDo2TElrCG6Oe6LN/X+ # kiJD9K8PE+OE7xVhNDf7JAxUHt531oX7iM8p6JGGBYQdPOZ8rGf4K5PDrDxnHckG # dbKHhqkbrSHaX/gu4q0ukgfIprs40ChYQ10vZ95mYyuWgIHOi51PciPmQ/qLPof0 # b/au08F0SpTE5cxx1Rk4cAuhP/PtzVln5lsSl9r9KzJ3Hcv6qnwXUU1nUg== # =U+N2 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 16 Feb 2024 12:56:59 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: ci: Fix again build-previous-qemu usb: inline device creation functions target/i386: Generate an illegal opcode exception on cmp instructions with lock prefix i386: xen: fix compilation --without-default-devices configure: put all symlink creation together configure: do not create legacy symlinks smc37c669: remove useless is_enabled functions isa-superio: validate floppy.count value mips: remove unnecessary "select PTIMER" i386/cpuid: Move leaf 7 to correct group i386/cpuid: Remove subleaf constraint on CPUID leaf 1F i386/cpuid: Decrease cpuid_i when skipping CPUID leaf 1F physmem: replace function name with __func__ in ram_block_discard_range() i386/pc: Drop pc_machine_kvm_type() target/i386: Add support of KVM_FEATURE_ASYNC_PF_VMEXIT for guest i386/cpu: Mask with XCR0/XSS mask for FEAT_XSAVE_XCR0_HI and FEAT_XSAVE_XSS_HI leafs i386/cpu: Clear FEAT_XSAVE_XSS_LO/HI leafs when CPUID_EXT_XSAVE is not available Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-16usb: inline device creation functionsPaolo Bonzini
Allow boards to use the device creation functions even if USB itself is not available; of course the functions will fail inexorably, but this can be okay if the calls are conditional on the existence of some USB host controller device. This is for example the case for hw/mips/loongson3_virt.c. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-02-16i386/pc: Drop pc_machine_kvm_type()Xiaoyao Li
pc_machine_kvm_type() was introduced by commit e21be724eaf5 ("i386/xen: add pc_machine_kvm_type to initialize XEN_EMULATE mode") to do Xen specific initialization by utilizing kvm_type method. commit eeedfe6c6316 ("hw/xen: Simplify emulated Xen platform init") moves the Xen specific initialization to pc_basic_device_init(). There is no need to keep the PC specific kvm_type() implementation anymore. So we'll fallback to kvm_arch_get_default_type(), which simply returns 0. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Isaku Yamahata <isaku.yamahata@intel.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: David Woodhouse <dwmw@amazon.co.uk> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231007065819.27498-1-xiaoyao.li@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-02-16Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into stagingPeter Maydell
Misc HW patch queue - Remove unused MIPS SAAR* registers (Phil) - Remove warning when testing the TC58128 NAND EEPROM (Peter) - KConfig cleanups around ISA SuperI/O and MIPS (Paolo) - QDev API uses sanitization (Philippe) - Split AHCI model as PCI / SysBus (Philippe) - Add SMP support to SPARC Leon3 board (Clément) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXOUD4ACgkQ4+MsLN6t # wN6gWRAAjf+6Z9VUvvHqZoaSJW49k+GRUelTI2tyN+eGfetAx9dk8aIbpbV1X12d # pc56jsSi6ICT7baCegtxHszhYJr2e9A2QLCAOJt+Oz87kEGes3ONVVKAk7pwjKxt # m8pmU3uXWgFvU6PoFBhGBa6LiZBulgLNXBUwzmEhc9PpPkR49ULdDp/qxtWvxOV5 # xYBktFlkiT+AvHq3QWCnDIaw+pH5ghEq9BI4xFOvvvqSqdHEqsGAaiKPa9Po0Gfz # Ap9qsm4FxKxhGoeQWtAIP8TvN3pFFSXMysziP6Xt1rffKsvF9ioghGKRM6BgQfqD # ZetjcFbcf7dQu3zZVy8ljYcymMxfZcWWVVq4CMC68lPQE97hz1CT3PJjgd77dKfi # z60uRkOGaiPW5iIGT9+vdQxZ5K3HivKyjuHOdV8V4HnWO3oqgfDtNHn5RKed0qUg # g1FoWriJGsDixdx1vd0EoH2/oTxy4HIsFv7a1OjiZyBLjO+EeEZ3+H9pqUHqBxva # +Dv70z9F1sv5dzcUXH+oCgTbnKlJ90Q+e3vj0wGdlBncVsgIwbtgqYelhUEl+xJX # Mu6KNUo5ANVP38ZKG0GSMCZHfcUjc5s+5rG55NbTN0HiF56a6D2KlQAuXdUsGE1J # 7i4cwipJmfxzbdPDlSb3kBxm5pFexEk6nROF9kTHQj3ZBMMvIls= # =nOX+ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 Feb 2024 17:56:14 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20240215' of https://github.com/philmd/qemu: (56 commits) hw/ide/ich9: Use AHCIPCIState typedef hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h' hw/ide/ahci: Remove SysbusAHCIState::num_ports field hw/ide/ahci: Do not pass 'ports' argument to ahci_realize() hw/ide/ahci: Convert AHCIState::ports to unsigned hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs() hw/ide/ahci: Inline ahci_get_num_ports() hw/ide/ahci: Rename AHCI PCI function as 'pdev' hw/ide/ahci: Expose AHCIPCIState structure hw/i386/q35: Use DEVICE() cast macro with PCIDevice object hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled MAINTAINERS: Add myself as reviewer for TCG Plugins MAINTAINERS: replace Fabien by myself as Leon3 maintainer hw/sparc/leon3: Initialize GPIO before realizing CPU devices hw/sparc/leon3: Pass DeviceState opaque argument to leon3_start_cpu() hw/sparc/leon3: Pass DeviceState opaque argument to leon3_set_pil_in() hw/sparc/leon3: check cpu_id in the tiny bootloader hw/sparc/leon3: implement multiprocessor hw/sparc/leon3: remove SP initialization target/sparc: implement asr17 feature for smp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-15hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h'Philippe Mathieu-Daudé
Keep "hw/ide/ahci.h" AHCI-generic. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20240213081201.78951-10-philmd@linaro.org>
2024-02-15hw/ide/ahci: Remove SysbusAHCIState::num_ports fieldPhilippe Mathieu-Daudé
No need to duplicate AHCIState::ports, directly access it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213081201.78951-9-philmd@linaro.org>
2024-02-15hw/ide/ahci: Convert AHCIState::ports to unsignedPhilippe Mathieu-Daudé
AHCIState::ports should be unsigned. Besides, we never check it for negative value. It is unlikely it was ever used with more than INT32_MAX ports, so it is safe to convert it to unsigned. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213081201.78951-7-philmd@linaro.org>
2024-02-15hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs()Philippe Mathieu-Daudé
Since ahci_ide_create_devs() is not PCI specific, pass it an AHCIState argument instead of PCIDevice. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213081201.78951-6-philmd@linaro.org>
2024-02-15hw/ide/ahci: Inline ahci_get_num_ports()Philippe Mathieu-Daudé
Introduce the 'ich9' variable and inline ahci_get_num_ports(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213081201.78951-5-philmd@linaro.org>
2024-02-15hw/ide/ahci: Expose AHCIPCIState structurePhilippe Mathieu-Daudé
In order to be able to QOM-embed a structure, we need its full definition. Move it from "ahci_internal.h" to the new "hw/ide/ahci-pci.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213081201.78951-3-philmd@linaro.org>
2024-02-15hw/intc/grlib_irqmp: implements multicore irqClément Chigot
Now there is an ncpus property, use it in order to deliver the IRQ to multiple CPU. Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr> Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240131085047.18458-5-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-15hw/sparc/grlib: split out the headers for each peripheralsClément Chigot
Split out the headers for each peripherals and move them in their right hardware directory. Update Copyright and add SPDX-License-Identifier at the same time. Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr> Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240131085047.18458-2-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-15hw/dma: Pass parent object to i8257_dma_init()Philippe Mathieu-Daudé
Set I8257 instances parent (migration isn't affected). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213114426.87836-1-philmd@linaro.org>
2024-02-15hw/rx/rx62n: Only call qdev_get_gpio_in() when necessaryPhilippe Mathieu-Daudé
Instead of filling an array of all the possible IRQs, only call qdev_get_gpio_in() when an IRQ is used. Remove the array from RX62NState. Doing so we avoid calling qdev_get_gpio_in() on an unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213130341.1793-4-philmd@linaro.org>
2024-02-15hw/rx/rx62n: Reduce inclusion of 'qemu/units.h'Philippe Mathieu-Daudé
"qemu/units.h" is not used in the "hw/rx/rx62n.h" header, include it in the source where it is. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213130341.1793-3-philmd@linaro.org>
2024-02-15hw/misc/mips_itu: Remove MIPSITUState::saar fieldPhilippe Mathieu-Daudé
This field is not set. Remove it along with the dead code it was guarding. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-7-philmd@linaro.org>
2024-02-15hw/misc/mips_itu: Remove MIPSITUState::cpu0 fieldPhilippe Mathieu-Daudé
Since previous commit the MIPSITUState::cpu0 field is not used anymore. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-6-philmd@linaro.org>
2024-02-15hw/misc/mips: Reduce itc_reconfigure() scopePhilippe Mathieu-Daudé
Previous commit removed the MT*C0(SAAR) helpers which were the only calls to itc_reconfigure() out of hw/, we can reduce its scope and declare it statically. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-3-philmd@linaro.org>
2024-02-15hw/misc/mps2-scc: Make changes needed for AN536 FPGA imagePeter Maydell
The MPS2 SCC device is broadly the same for all FPGA images, but has minor differences in the behaviour of the CFG registers depending on the image. In many cases we don't really care about the functionality controlled by these registers and a reads-as-written or similar behaviour is sufficient for the moment. For the AN536 the required behaviour is: * A_CFG0 has CPU reset and halt bits - implement as reads-as-written for the moment * A_CFG1 has flash or ATCM address 0 remap handling - QEMU doesn't model this; implement as reads-as-written * A_CFG2 has QSPI select (like AN524) - implemented (no behaviour, as with AN524) * A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits" - QEMU doesn't care about these, so use the existing RAZ behaviour for convenience * A_CFG4 is board rev (like all other images) - no change needed * A_CFG5 is ACLK frq in hz (like AN524) - implemented as reads-as-written, as for other boards * A_CFG6 is core 0 vector table base address - implemented as reads-as-written for the moment * A_CFG7 is core 1 vector table base address - implemented as reads-as-written for the moment Make the changes necessary for this; leave TODO comments where appropriate to indicate where we might want to come back and implement things like CPU reset. The other aspects of the device specific to this FPGA image (like the values of the board ID and similar registers) will be set via the device's qdev properties. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
2024-02-15hw/arm/smmuv3: add support for stage 1 access faultLuc Michel
An access fault is raised when the Access Flag is not set in the looked-up PTE and the AFFD field is not set in the corresponding context descriptor. This was already implemented for stage 2. Implement it for stage 1 as well. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Mostafa Saleh <smostafa@google.com> Message-id: 20240213082211.3330400-1-luc.michel@amd.com [PMM: tweaked comment text] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-15hw/arm/virt: Wire up non-secure EL2 virtual timer IRQPeter Maydell
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a non-secure EL2 virtual timer. We implemented the timer itself in the CPU model, but never wired up its IRQ line to the GIC. Wire up the IRQ line (this is always safe whether the CPU has the interrupt or not, since it always creates the outbound IRQ line). Report it to the guest via dtb and ACPI if the CPU has the feature. The DTB binding is documented in the kernel's Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml and the ACPI table entries are documented in the ACPI specification version 6.3 or later. Because the IRQ line ACPI binding is new in 6.3, we need to bump the FADT table rev to show that we might be using 6.3 features. Note that exposing this IRQ in the DTB will trigger a bug in EDK2 versions prior to edk2-stable202311, for users who use the virt board with 'virtualization=on' to enable EL2 emulation and are booting an EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is that EDK2 will assert on bootup: ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48 If you see that assertion you should do one of: * update your EDK2 binaries to edk2-stable202311 or newer * use the 'virt-8.2' versioned machine type * not use 'virtualization=on' (The versions shipped with QEMU itself have the fix.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
2024-02-14Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell
into staging virtio,pc,pci: features, cleanups, fixes vhost-user-snd support x2APIC mode with TCG support CXL update to r3.1 fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmXMoXUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpFtMIAKUKD0hzJrwOyPo4xsRUMbsB3ehIsJsMKfOK # w+JWzTaojAG8ENPelWBdL2sEIs5U73VOchjLqHbH2m5sz6GJ13214amvdU/fYc8+ # /dU2ZKoAmaR5L1ovKO/fq07y/J6DrITZ5tosy2i84Xa8EnsL4j3wEPNVWsDi7dna # mvXUICSOOoJQ4O2YhSruKCQ8qIgF1/0Oi3u/rcrW3alSs8VQlrtQXxl6k+LbYqek # +Fytco3jMRHPvQ+GYUIwGuHjN15ghArcvbsV0GIa+24BPY5h7YbDYGbfasePT5OK # zDz51jitkoyDrQr+OzwOEe/X5+dVGhayRXfMtU5Qm53IE3y61qc= # =K4b1 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Feb 2024 11:18:13 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (60 commits) MAINTAINERS: Switch to my Enfabrica email virtio-gpu-rutabaga.c: override resource_destroy method virtio-gpu.c: add resource_destroy class method hw/display/virtio-gpu.c: use reset_bh class method hw/smbios: Fix port connector option validation hw/smbios: Fix OEM strings table option validation virtio-gpu: Correct virgl_renderer_resource_get_info() error check hw/cxl: Standardize all references on CXL r3.1 and minor updates hw/cxl: Update mailbox status registers. hw/cxl: Update RAS Capability Definitions for version 3. hw/cxl: Update link register definitions. hw/cxl: Update HDM Decoder capability to version 3 tests/acpi: Update DSDT.cxl to reflect change _STA return value. hw/i386: Fix _STA return value for ACPI0017 tests/acpi: Allow update of DSDT.cxl hw/mem/cxl_type3: Fix potential divide by zero reported by coverity hw/cxl: Pass NULL for a NULL MemoryRegionOps hw/cxl: Pass CXLComponentState to cache_mem_ops hw/cxl/device: read from register values in mdev_reg_read() hw/cxl/mbox: Remove dead code ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-14virtio-gpu.c: add resource_destroy class methodManos Pitsidianakis
When destroying/unrefing resources, devices such as virtio-gpu-rutabaga need to do their own bookkeeping (free rutabaga resources that are associated with the virtio_gpu_simple_resource). This commit adds a class method so that virtio-gpu-rutabaga can override it in the next commit. Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-Id: <b0a86630c4d601f3a269fd7e08cfefc13bd4e219.1706626470.git.manos.pitsidianakis@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-14hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron
Previously not all references mentioned any spec version at all. Given r3.1 is the current specification available for evaluation at www.computeexpresslink.org update references to refer to that. Hopefully this won't become a never ending job. A few structure definitions have been updated to add new fields. Defaults of 0 and read only are valid choices for these new DVSEC registers so go with that for now. There are additional error codes and some of the 'questions' in the comments are resolved now. Update documentation reference to point to the CXL r3.1 specification with naming closer to what is on the cover. For cases where there are structure version numbers, add defines so they can be found next to the register definitions. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126121636.24611-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-14hw/cxl: Update mailbox status registers.Jonathan Cameron
Whilst the reported version was 1 so there should be no changes, a couple of fields (where the value 0 was valid) were not defined. Make those explicit and update references to be based on CXL r3.1. Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126121636.24611-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-14hw/cxl: Update RAS Capability Definitions for version 3.Jonathan Cameron
Part of bringing all of CXL emulation inline with CXL r3.1. No functional changes. Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126121636.24611-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 09:57:36 +0000