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2024-02-27hw/arm: Introduce Raspberry PI 4 machineSergey Kambalin
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-11-sergey.kambalin@auriga.com [PMM: Change name to 'raspi4b', not 'raspi4b-2g'] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/arm: Add GPIO and SD to BCM2838 periphSergey Kambalin
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-10-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/gpio: Connect SD controller to BCM2838 GPIOSergey Kambalin
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-9-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/gpio: Add BCM2838 GPIO stubSergey Kambalin
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-7-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/arm/bcm2838: Add GIC-400 to BCM2838 SoCSergey Kambalin
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-6-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/arm: Introduce BCM2838 SoCSergey Kambalin
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-5-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/arm/raspi: Split out raspi machine common partSergey Kambalin
Pre-setup for raspberry pi 4 introduction Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-4-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/arm/bcm2853_peripherals: Split out common part of peripheralsSergey Kambalin
Pre-setup for BCM2838 introduction Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-3-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/arm/bcm2836: Split out common part of BCM283X classesSergey Kambalin
Pre setup for BCM2838 introduction Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240226000259.2752893-2-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/core: Add ResetContainer which holds objects implementing ResettablePeter Maydell
Implement a ResetContainer. This is a subclass of Object, and it implements the Resettable interface. The container holds a list of arbitrary other objects which implement Resettable, and when the container is reset, all the objects it contains are also reset. This will allow us to have a 3-phase-reset equivalent of the old qemu_register_reset() API: we will have a single "simulation reset" top level ResetContainer, and objects in it are the equivalent of the old QEMUResetHandler functions. The qemu_register_reset() API manages its list of callbacks using a QTAILQ, but here we use a GPtrArray for our list of Resettable children: we expect the "remove" operation (which will need to do an iteration through the list) to be fairly uncommon, and we get simpler code with fewer memory allocations. Since there is currently no listed owner in MAINTAINERS for the existing reset-related source files, create a new section for them, and add these new files there also. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20240220160622.114437-7-peter.maydell@linaro.org Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
2024-02-27hw/arm: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQsInès Varhol
Fixes: 52671f69f7a4 ("[PATCH v8 0/3] Add device STM32L4x5 EXTI") Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240220184145.106107-2-ines.varhol@telecom-paris.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27aspeed: fix hardcode boot address 0Jamin Lin
In the previous design of ASPEED SOCs QEMU model, it set the boot address at "0" which was the hardcode setting for ast10x0, ast2600, ast2500 and ast2400. According to the design of ast2700, it has a bootmcu(riscv-32) which is used for executing SPL and initialize DRAM and copy u-boot image from SPI/Flash to DRAM at address 0x400000000 at SPL boot stage. Then, CPUs(cortex-a35) execute u-boot, kernel and rofs. Currently, qemu not support emulate two CPU architectures at the same machine. Therefore, qemu will only support to emulate CPU(cortex-a35) side for ast2700 and the boot address is "0x4 00000000". Fixed hardcode boot address "0" for future models using a different mapping address. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-27aspeed: introduce a new UART0 device nameJamin Lin
The Aspeed datasheet refers to the UART controllers as UART1 - UART13 for the ast10x0, ast2600, ast2500 and ast2400 SoCs and the Aspeed ast2700 introduces an UART0 and the UART controllers as UART0 - UART12. To keep the naming in the QEMU models in sync with the datasheet, let's introduce a new UART0 device name and do the required adjustements. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - Kept original assert() in aspeed_soc_uart_set_chr() - Fixed 'i' range in connect_serial_hds_to_uarts() loop ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-27hw/ide: Remove last two uses of ide/internal.h outside of hw/ide/BALATON Zoltan
Remove last two includes of hw/ide/intarnal.h outside of hw/ide and replace them with newly added public header to allow moving internal.h into hw/ide to really stop exposing it. Fixes: a11f439a0e (hw/ide: Stop exposing internal.h to non-IDE files) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240223142633.933694E6004@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-27hw/i386/pc: Remove unneeded class attribute "kvmclock_enabled"Bernhard Beschow
PCMachineClass introduces the attribute into the class hierarchy and sets it to true. There is no sub class overriding the attribute. Commit 30d2a17b46e9 "hw/i386: Remove the deprecated machines 0.12 up to 0.15" removed the last overrides of this attribute. The attribute is now unneeded and can be removed. Fixes: 30d2a17b46e9 "hw/i386: Remove the deprecated machines 0.12 up to 0.15" Cc: Thomas Huth <thuth@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20240224135851.100361-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-27hw/i386/pc: Rename "bus" attribute to "pcibus"Bernhard Beschow
The attribute is of type PCIBus; reflect that in the name. It will also make the next change more intuitive. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20240224135851.100361-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-27hw/i386/x86: Let ioapic_init_gsi() take parent as pointerBernhard Beschow
Rather than taking a QOM name which has to be resolved, let's pass the parent directly as pointer. This simplifies the code. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20240224135851.100361-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-27hw/usb: remove usb_bus_findPaolo Bonzini
Inline the sole remaining use, which is for the -usbdevice command line. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240223124406.234509-9-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-27hw/nubus: add nubus-virtio-mmio deviceMark Cave-Ayland
The nubus-virtio-mmio device is a Nubus card that contains a set of 32 virtio-mmio devices and a goldfish PIC similar to the m68k virt machine that can be plugged into the m68k q800 machine. There are currently a number of drivers under development that can be used in conjunction with this device to provide accelerated and/or additional hypervisor services to 68k Classic MacOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240111102954.449462-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-27hw/nubus: increase maximum Declaration ROM size from 128k to 1MbMark Cave-Ayland
Whilst 128k is more than enough for a typical Declaration ROM, a C compiler configured to produce an unstripped debug binary can generate a ROM image that exceeds this limit. Increase the maximum size to 1Mb to help make life easier for developers. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240111102954.449462-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-26hw/sysbus: Remove now unused sysbus_address_space()Philippe Mathieu-Daudé
sysbus_address_space() is not more used, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240216153517.49422-7-philmd@linaro.org>
2024-02-23ppc/pnv: Implement the ChipTOD to Core transferNicholas Piggin
One of the functions of the ChipTOD is to transfer TOD to the Core (aka PC - Pervasive Core) timebase facility. The ChipTOD can be programmed with a target address to send the TOD value to. The hardware implementation seems to perform this by sending the TOD value to a SCOM address. This implementation grabs the core directly and manipulates the timebase facility state in the core. This is a hack, but it works enough for now. A better implementation would implement the transfer to the PnvCore xscom register and drive the timebase state machine from there. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machinesNicholas Piggin
Wire the ChipTOD model to powernv9 and powernv10 machines. Suggested-by-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Add POWER9/10 chiptod modelNicholas Piggin
The ChipTOD (for Time-Of-Day) is a chip pervasive facility in IBM POWER (powernv) processors that keeps a time of day clock. In particular for this model are facilities that initialise and start the time of day clock, and that synchronise that clock to cores on the chip, and to other chips. In this way, all cores on all chips can synchronise timebase (TB). This model implements functionality sufficient to run the skiboot chiptod synchronisation procedure (with the following core timebase state machine implementation). It does not modify the TB in the cores where the real hardware would, because the QEMU ppc timebase implementation is always synchronised acros all cores. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc: N1 chiplet wiringChalapathi V
This part of the patchset connects the nest1 chiplet model to p10 chip. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc: Add N1 chiplet modelChalapathi V
The N1 chiplet handle the high speed i/o traffic over PCIe and others. The N1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a N1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented. This commit also implement the read/write method for the powerbus scom registers Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc: Add pnv nest pervasive common chiplet modelChalapathi V
A POWER10 chip is divided into logical units called chiplets. Chiplets are broadly divided into "core chiplets" (with the processor cores) and "nest chiplets" (with everything else). Each chiplet has an attachment to the pervasive bus (PIB) and with chiplet-specific registers. All nest chiplets have a common basic set of registers and This model will provide the registers functionality for common registers of nest chiplet (Pervasive Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets) This commit implement the read/write functions of chiplet control registers. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Test pnv i2c master and connected devicesGlenn Miles
Tests the following for both P9 and P10: - I2C master POR status - I2C master status after immediate reset Tests the following for powernv10-ranier only: - Config pca9552 hotplug device pins as inputs then Read the INPUT0/1 registers to verify all pins are high - Connected GPIO pin tests of P10 PCA9552 device. Tests output of pins 0-4 affect input of pins 5-9 respectively. - PCA9554 GPIO pins test. Tests input and ouput functionality. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23misc: Add a pca9554 GPIO device modelGlenn Miles
Specs are available here: https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf This is a simple model supporting the basic registers for GPIO mode. The device also supports an interrupt output line but the model does not yet support this. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power controlGlenn Miles
The Power Hypervisor code expects to see a pca9552 device connected to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left- justified address of 0xC6). This is used by hypervisor code to control PCIe slot power during hotplug events. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23misc/pca9552: Let external devices set pca9552 inputsGlenn Miles
Allow external devices to drive pca9552 input pins by adding input GPIO's to the model. This allows a device to connect its output GPIO's to the pca9552 input GPIO's. In order for an external device to set the state of a pca9552 pin, the pin must first be configured for high impedance (LED is off). If the pca9552 pin is configured to drive the pin low (LED is on), then external input will be ignored. Here is a table describing the logical state of a pca9552 pin given the state being driven by the pca9552 and an external device: PCA9552 Configured State | Hi-Z | Low | ------+------+-----+ External Hi-Z | Hi | Low | Device ------+------+-----+ State Low | Low | Low | ------+------+-----+ Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs.Harsh Prateek Bora
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to the range of CPU IPIs during initialization of nr-irqs property. It is more appropriate to have its own define which can be further reused as appropriate for correct interpretation. Suggested-by: Cedric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Kowshik Jois <kowsjois@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_prPhilippe Mathieu-Daudé
Since 'softmmu' is quite a loaded term in QEMU, rename the vhyp MMU facilities to use the vhyp_mmu_ prefix rather than softmmu_. vhyp_mmu_ is chosen because the code that manipulates the hash table via guest software hypercalls is QEMU's implementation of the PAPR hypervisor interface, called vhyp. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> [npiggin: Pick a different name, explain it in changelog.] Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-22Merge tag 'hw-misc-20240222' of https://github.com/philmd/qemu into stagingPeter Maydell
Misc HW patch queue - Remove sysbus_add_io (Phil) - Build PPC 4xx PCI host bridges once (Phil) - Display QOM path while debugging SMBus targets (Joe) - Simplify x86 PC code (Bernhard) - Remove qemu_[un]register_reset() calls in x86 PC CMOS (Peter) - Fix wiring of ICH9 LPC interrupts (Bernhard) - Split core IDE as device / bus / dma (Thomas) - Prefer QDev API over QOM for devices (Phil) - Fix invalid use of DO_UPCAST() in Leon3 (Thomas) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXXQ1IACgkQ4+MsLN6t # wN4e2xAAig55EJh/JwpdGx55rFUab3Ay22jgXrExmBir8hzhyzssY+RUj2ALRa5e # T26kxCEqiuT549FtWm/ci6kVax0QD6bqz/6/j451XB9469Z/3BDOV5rhsqF6zlr5 # BMbyC8PKnMUluG8v1ZuRjC3m2lK3ZvkVnZtj7SZUR50ssEnR32fVIziN14/OYkts # 2B24sLrnLBfvyatMRsuFqGWrcbtMdnwNpjenGfDPOTF33W1sxTQ8GSvx1RV32l69 # Yr/iCVoCl+rGxbLLP1TwqtOwzk32p8RsbIt6rWMqVMv/p5F6ezFeiOk7VHnnEJRH # e7TPxt4XeLGPARMQLT3gQh0MGIIodanSHePRBkczuNmKYTJrz+5jMu2Qg4MmMUE/ # TV0fKgdjh/edhAOHzJgZqLmNV71icl8WBjfsw2qT4ZwgJzWq7YM2/XZKkeWhk2nQ # whLxfgiU4PNJ6vHhebJNjOovCYQTK2FbXR+PvVn5FEbH4CuFr8mqkYc+vNYM9dLA # b7uMk1H8kcb5+kqfPPU2lVd1wO7uqhxYOYU2O9nYq8aw7ioLoLeEdj2IicLtrA/H # GMtyA5cYeabeRzSXF30tM2AR1uQ/e4Z7oNxW6z3GVK1NrQtKilqPgMKut8uWYvva # crJLpRQhGiY3sDrIkkCcAHzv256dZaJNLR1KPViaHOyVPZV+x2s= # =+h2O # -----END PGP SIGNATURE----- # gpg: Signature made Thu 22 Feb 2024 12:51:30 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20240222' of https://github.com/philmd/qemu: (32 commits) hw/sparc/leon3: Fix wrong usage of DO_UPCAST macro hw/ide: Stop exposing internal.h to non-IDE files hw/ide: Remove the include/hw/ide.h legacy file hw/ide: Move IDE bus related definitions to a new header ide-bus.h hw/ide: Move IDE device related definitions to ide-dev.h hw/ide: Move IDE DMA related definitions to a separate header ide-dma.h hw/ide: Split qdev.c into ide-bus.c and ide-dev.c hw/ide: Add the possibility to disable the CompactFlash device in the build hw/acpi/ich9_tco: Include missing 'migration/vmstate.h' header hw/acpi/cpu: Use CPUState typedef hw/acpi: Include missing 'qapi/qapi-types-acpi.h' generated header hw/isa/meson.build: Sort alphabetically hw/i386/pc_q35: Populate interrupt handlers before realizing LPC PCI function hw/i386/pc_sysfw: Use qdev_is_realized() instead of QOM API hw/i386/pc_sysfw: Inline pc_system_flash_create() and remove it hw/i386/pc: Confine system flash handling to pc_sysfw hw/i386/pc: Defer smbios_set_defaults() to machine_done hw/i386/pc: Merge pc_guest_info_init() into pc_machine_initfn() hw/i386/x86: Turn apic_xrupt_override into class attribute hw/i386/pc: Do pc_cmos_init_late() from pc_machine_done() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # include/hw/i386/pc.h
2024-02-22hw/ide: Stop exposing internal.h to non-IDE filesThomas Huth
include/hw/ide/internal.h is currently included by include/hw/ide/pci.h and thus exposed to a lot of files that are not part of the IDE subsystem. Stop including internal.h there and use the appropriate new headers ide-bus.h and ide-dma.h instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20240220085505.30255-8-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Remove the include/hw/ide.h legacy fileThomas Huth
There was only one prototype left in this legacy file. Move it to ide-dev.h to finally get rid of it. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20240220085505.30255-7-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Move IDE bus related definitions to a new header ide-bus.hThomas Huth
Let's consolidate the public IDE bus related functions in a separate header. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240220085505.30255-6-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Move IDE device related definitions to ide-dev.hThomas Huth
Untangle internal.h by moving public IDE device related definitions to ide-dev.h. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240220085505.30255-5-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Move IDE DMA related definitions to a separate header ide-dma.hThomas Huth
These definitions are required outside of the hw/ide/ code, too, so lets's move them from internal.h to a new header called ide-dma.h. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240220085505.30255-4-thuth@redhat.com> [PMD: Use IDEDMAOps typedef in struct IDEDMA] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/ide: Add the possibility to disable the CompactFlash device in the buildThomas Huth
For distros like downstream RHEL, it would be helpful to allow to disable the CompactFlash device. For making this possible, we need a separate Kconfig switch for this device, and the code should reside in a separate file. Let's also introduce a new header ide-dev.h which can be used to collect definitions related to IDE devices. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20240220085505.30255-2-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/acpi/ich9_tco: Include missing 'migration/vmstate.h' headerPhilippe Mathieu-Daudé
We need the VMStateDescription structure definition from "migration/vmstate.h" in order to declare vmstate_tco_io_sts. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240219141412.71418-4-philmd@linaro.org>
2024-02-22hw/acpi/cpu: Use CPUState typedefPhilippe Mathieu-Daudé
QEMU coding style recommend using structure typedefs: https://www.qemu.org/docs/master/devel/style.html#typedefs Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240126220407.95022-2-philmd@linaro.org>
2024-02-22hw/acpi: Include missing 'qapi/qapi-types-acpi.h' generated headerPhilippe Mathieu-Daudé
ACPIOSTInfo is a QAPI generated structure: $ git grep -w ACPIOSTInfo qapi/acpi.json:81:# @ACPIOSTInfo: qapi/acpi.json:99:{ 'struct': 'ACPIOSTInfo', qapi/acpi.json:109:# Return a list of ACPIOSTInfo for devices that support status Include the "qapi/qapi-types-acpi.h" header to avoid the following errors when including "hw/acpi/cpu.h" or "hw/acpi/memory_hotplug.h" elsewhere: include/hw/acpi/cpu.h:67:52: error: unknown type name 'ACPIOSTInfoList' void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list); ^ include/hw/acpi/memory_hotplug.h:51:55: error: unknown type name 'ACPIOSTInfoList' void acpi_memory_ospm_status(MemHotplugState *mem_st, ACPIOSTInfoList ***list); ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240219141412.71418-2-philmd@linaro.org>
2024-02-22hw/i386/pc: Confine system flash handling to pc_sysfwBernhard Beschow
Rather than distributing PC system flash handling across three files, let's confine it to one. Now, pc_system_firmware_init() creates, configures and cleans up the system flash which makes the code easier to understand. It also avoids the extra call to pc_system_flash_cleanup_unused() in the Xen case. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240208220349.4948-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/i386/pc: Defer smbios_set_defaults() to machine_doneBernhard Beschow
Handling most of smbios data generation in the machine_done notifier is similar to how the ARM virt machine handles it which also calls smbios_set_defaults() there. The result is that all pc machines are freed from explicitly worrying about smbios setup. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240208220349.4948-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/i386/pc: Merge pc_guest_info_init() into pc_machine_initfn()Bernhard Beschow
Resolves redundant code in the piix and q35 machines. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240208220349.4948-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/i386/x86: Turn apic_xrupt_override into class attributeBernhard Beschow
The attribute isn't user-changeable and only true for pc-based machines. Turn it into a class attribute which allows for inlining pc_guest_info_init() into pc_machine_initfn(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240208220349.4948-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/i386/pc: Store pointers to IDE buses in PCMachineStatePeter Maydell
Add the two IDE bus BusState pointers to the set we keep in PCMachineState. This allows us to avoid passing them to pc_cmos_init(), and also will allow a refactoring of how we call pc_cmos_init_late(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMD: Do not zero-init pcms->idebus[] again] Message-ID: <20240220160622.114437-2-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-22hw/tricore/testboard: Use qdev_new() instead of QOM basic APIPhilippe Mathieu-Daudé
Prefer QDev API for QDev objects, avoid the underlying QOM layer. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20240216110313.17039-5-philmd@linaro.org>
2024-02-22hw/ppc/ppc4xx_pci: Extract PCI host definitions to hw/pci-host/ppc4xx.hPhilippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240215105017.57748-3-philmd@linaro.org>