aboutsummaryrefslogtreecommitdiff
path: root/include/hw
AgeCommit message (Collapse)Author
2023-11-21Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingStefan Hajnoczi
Block layer patches - Fix graph lock related deadlocks with the stream job - ahci: Fix legacy software reset - ide/via: Fix switch between compatibility and native mode # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmVcmYoRHGt3b2xmQHJl # ZGhhdC5jb20ACgkQfwmycsiPL9YDzw/7BD6wZpyCsDbFu9Jbt0L894tYQls7otnR # yeAIaZVqSkDcMK8VBD/xAjV8UgX194oKPi42CDgS73avd0cSHLIM5cNgGkwCrMWS # ry5uuOP6EWVMPPR/129cpH8uGvkl+qwCQf5gB13/8NvMbeN2mHOTC6WW+VA20vb0 # V0DJXhYszVzXa3L1a/m6f4Jwj54tTeZ56JcBblL3wi/soklb45gsnPJaHeGb3rzK # yjPkw+kpVXTVbpacobGmzmjlD3Yqk69NexP2kyU1w2lqPnemYPH+9sa+7RxMspkj # InQvqq6TFtMOrC/65/527p2ENRUOxn7Xwsa1+Hnar2i3BoyGugWE8GPxJDBxAWW4 # INJtpxIpiA7Scd26VBCNVstVe5EuyxkP97T85cgNUMgeE58y3i51i6eHd4GUIR7v # PNc5TsSbnVV8sQ7RsXka4hRyjndIPRB0CBePydDoBz6zaGmcVU6ep0Oppah9gVu9 # CU0dBz2jV0r1dFhU1eZkCbd1ufdR93R/iD3gBD4vj1xSL3l+9OE/FKdrVE66uElL # iAsHp3cimkPuWAx/jZaeAC7BDI0XS6s1TimddqJx90f2mZjkq8cmVp+HoVNP0jRQ # VP6AIQy6is+P4QtDSekgXVJE8K95ngBzsr+ittR8jF4q67QzHVjLmJ9ZBXyrowlz # gtZTy2WPxbM= # =8dXj # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Nov 2023 06:50:34 EST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: hw/ide/via: implement legacy/native mode switching ide/via: don't attempt to set default BAR addresses ide/pci: introduce pci_ide_update_mode() function ide/ioport: move ide_portio_list[] and ide_portio_list2[] definitions to IDE core iotests: Test two stream jobs in a single iothread stream: Fix AioContext locking during bdrv_graph_wrlock() block: Fix deadlocks in bdrv_graph_wrunlock() block: Fix bdrv_graph_wrlock() call in blk_remove_bs() hw/ide/ahci: fix legacy software reset Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-21ide/pci: introduce pci_ide_update_mode() functionMark Cave-Ayland
This function reads the value of the PCI_CLASS_PROG register for PCI IDE controllers and configures the PCI BARs and/or IDE ioports accordingly. In the case where we switch to legacy mode, the PCI BARs are set to return zero (as suggested in the "PCI IDE Controller" specification), the legacy IDE ioports are enabled, and the PCI interrupt pin cleared to indicate legacy IRQ routing. Conversely when we switch to native mode, the legacy IDE ioports are disabled and the PCI interrupt pin set to indicate native IRQ routing. The contents of the PCI BARs are unspecified, but this is not an issue since if a PCI IDE controller has been switched to native mode then its BARs will need to be programmed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20231116103355.588580-3-mark.cave-ayland@ilande.co.uk> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-21ide/ioport: move ide_portio_list[] and ide_portio_list2[] definitions to IDE ↵Mark Cave-Ayland
core These definitions are present in ioport.c which is currently only available when CONFIG_IDE_ISA is enabled. Move them to the IDE core so that they can be made available to PCI IDE controllers that support switching to legacy mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20231116103355.588580-2-mark.cave-ayland@ilande.co.uk> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-20hw/arm/stm32f100: Report error when incorrect CPU is usedPhilippe Mathieu-Daudé
The 'stm32vldiscovery' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231117071704.35040-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/arm/stm32f205: Report error when incorrect CPU is usedPhilippe Mathieu-Daudé
The 'netduino2' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-arm -M netduino2 -cpu cortex-a9 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-arm -M netduino2 -cpu cortex-a9 qemu-system-arm: Invalid CPU type: cortex-a9-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231117071704.35040-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/arm/stm32f405: Report error when incorrect CPU is usedPhilippe Mathieu-Daudé
Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M4 CPU: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu The valid types are: cortex-m4-arm-cpu Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231117071704.35040-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/core/machine: Constify MachineClass::valid_cpu_types[]Gavin Shan
Constify MachineClass::valid_cpu_types[i], as suggested by Richard Henderson. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231117071704.35040-2-philmd@linaro.org [PMD: Constify HPPA machines, restrict valid_cpu_types to machine_class_init() handlers] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-15include/hw/virtio/vhost.h: spelling fix: sateMichael Tokarev
Fixes: 4a00d5d7f4b6 "vhost: Add high-level state save/load functions" Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-15include/hw/hyperv/dynmem-proto.h: spelling fix: nunber, atleastMichael Tokarev
Fixes: 4f80cd2f033e "Add Hyper-V Dynamic Memory Protocol definitions" Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-15hw/cxl: spelling fixes: limitaions, potentialy, intializedMichael Tokarev
Fixes: 388d6b574e28 "hw/cxl: Use switch statements for read and write of cachemem registers" Fixes: 3314efd276ad "hw/cxl/mbox: Add Physical Switch Identify command." Fixes: 004e3a93b814 "hw/cxl: Add tunneled command support to mailbox for switch cci." Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-10qdev: Rework array properties based on list visitorKevin Wolf
Until now, array properties are actually implemented with a hack that uses multiple properties on the QOM level: a static "foo-len" property and after it is set, dynamically created "foo[i]" properties. In external interfaces (-device on the command line and device_add in QMP), this interface was broken by commit f3558b1b ('qdev: Base object creation on QDict rather than QemuOpts') because QDicts are unordered and therefore it could happen that QEMU tried to set the indexed properties before setting the length, which fails and effectively makes array properties inaccessible. In particular, this affects the 'ports' property of the 'rocker' device, which used to be configured like this: -device rocker,len-ports=2,ports[0]=dev0,ports[1]=dev1 This patch reworks the external interface so that instead of using a separate top-level property for the length and for each element, we use a single true array property that accepts a list value. In the external interfaces, this is naturally expressed as a JSON list and makes array properties accessible again. The new syntax looks like this: -device '{"driver":"rocker","ports":["dev0","dev1"]}' Creating an array property on the command line without using JSON format is currently not possible. This could be fixed by switching from QemuOpts to a keyval parser, which however requires consideration of the compatibility implications. All internal users of devices with array properties go through qdev_prop_set_array() at this point, so updating it takes care of all of them. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1090 Fixes: f3558b1b763683bb877f7dd5b282469cdadc65c3 Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20231109174240.72376-12-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-10Merge tag 'xen-virtio-fix-1-tag' of https://gitlab.com/sstabellini/qemu into ↵Stefan Hajnoczi
staging xen-virtio-fix-1 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEE0E4zq6UfZ7oH0wrqiU+PSHDhrpAFAmVKp0cACgkQiU+PSHDh # rpA0Wg//RUJeBg/Ohjw/ETMjr7+zpsxm0JEjqE5uDYF9+wbX5uAcPOjYLpCbWdKY # Q9nXmJCbnoqPYzjUrPpx0i8iiVnjbKY28sIqKzPDl4b2s8iPuGrjyPBbcZO1qvx9 # j3UOxiFqcIOIV/Ypf6rdo8hiIwZlHSYR3ZzWLFh2sFGmMee9TjDHiCwRXqZiIzE3 # ks39nV6+Ob1xVTLNZpHjSAsafd/SAusQv66OiGWPixM3DEMKCXUNWtFIfXd5tnVW # P/4uyRFHzDH+hBZZx2NMiWalTNpcWb4LYhgv/zFiSlnUuw7g0fUBWM1qHWaLcTfY # BEzm6578BVunFDJe5PEtc5bC1vSZarv6ndRKo7e/t5S/1bzyWzuI8nWCrUKscBSu # ZgFeJyO9bLRae5QDIiDG6id2dafP9x4zIrn07enuMQVYkjQynA6oS49KL1I+RP38 # Cae+dfadqBksxDbFkh0t02tWjVNeR5MzmkcktlWEn8h136VzZ+fPn93TSTewPxsf # 3ii6dhiu8+P7A5tfXuRhqlgS8QgaJt6EXDkttjIsC5tWuBo28jZQKw77cZ4DWq1a # eTy6hn9F0vX+8rNb1dq5Ct6BT6i2svmAloXKBvkaSPLwGLn2lKiUA3ky+9n0ZWEe # GiyTwkvdaZndrjup+B3MbtQWmJhN+niJZveTJgCdG6or4tvGOuI= # =1At5 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Nov 2023 05:08:23 HKT # gpg: using RSA key D04E33ABA51F67BA07D30AEA894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <sstabellini@kernel.org>" [expired] # gpg: aka "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" [expired] # gpg: Note: This key has expired! # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * tag 'xen-virtio-fix-1-tag' of https://gitlab.com/sstabellini/qemu: Xen: Fix xen_set_irq() and xendevicemodel_set_irq_level() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-08Merge tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu into stagingStefan Hajnoczi
ppc patch queue for 2023-11-07: This queue, the last one before the 8.2 feature freeze, has miscellanous changes that includes new PowerNV features and the new AmigaONE XE board. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZUqiORYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFkBSUA/2qm8CyrRqY5+tsjtWQqZmPZ3L1F # CgnXFNqtY2tzbTe5AQCi6FeQBEmXbZYVfryZyA+CQ4DUERc+18pe6hV3bBR9Cg== # =cnHS # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Nov 2023 04:46:49 HKT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu: ppc: qtest already exports qtest_rtas_call() hw/pci-host: Update PHB5 XSCOM registers ppc/pnv: Fix number of I2C engines and ports for power9/10 ppc/pnv: Connect PNV I2C controller to powernv10 ppc/pnv: Connect I2C controller model to powernv9 chip ppc/pnv: Add an I2C controller model tests/avocado: Add test for amigaone board hw/ppc: Add emulation of AmigaOne XE board hw/pci-host: Add emulation of Mai Logic Articia S Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-08Merge tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi
staging * Fix s390x CPU reconfiguration information in the SCLP facility map * Fix condition code problem in the CLC and LAALG instruction * Fix ordering of the new s390x topology list entries * Add some more files to the MAINTAINERS file * Allow newer versions of Tesseract in the m68k nextcube test # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVKgksRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWIHg//TM3JOpsMEqHKlUKqOJH02mFQrK6H7LG0 # BC56FG7T+/mpYs1NTG92t8nCK03C2ZCweQWD7ZulRJAjPhZv+TF5bJEForivU7+k # PKEshz9xKCWn2YGyNnf2LA06J1JkF215+KlReOoxwSgj1cPlHfBLQ0DtxmpJJZ1G # h5p4d26BbSlwR58HrFWTlhgJMPenl59BETUGIK1FklBxunmZeeijddfniAhOT44y # i0u9/H9KCg3tkwBROUy+42QV+ef32kz/yvi5RmYQI5W7PixO4sxH6MYduOjshsu9 # wK70f8EOwiZV6lFxqmbV7vxFeNnp5IuaVU7PMBoAkwZqLw99mSFy1+1BabCuL5b+ # 3iUTiD4UW48MYwE2Ua6Lit4kpfjhwcp/UYz6pIk6TCBQX6LfzO+nj+rod0GdIpyZ # 4Lwm7jBtpTlYkGrsMvpA/qcidOtqPA1lmBTNlY1hFodQF6KWtyObn0w5AM80xeeU # /mGxQDz97Bpz7LKZvhu+k38jaWvnJFnl3jF1zet88CYL9YL+YI/k1KjhFafCXb0V # 38Xpt5JTWxyLSh2B3gx0OpokX5bftvW9GlLix0HqL7c23uYwR2Bq+Rd6I8SAlk4C # uJq6gqP8IFBFHfgbmyqf/fyd/eHxm7J1voIdy9PZyxZ1JYT9A7yu56qV6SJYwCpr # aARwui/Dm4o= # =y+cC # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Nov 2023 02:30:35 HKT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu: target/s390x/cpu topology: Fix ordering and creation of TLEs tests/tcg/s390x: Test ADD LOGICAL WITH CARRY tests/tcg/s390x: Test LAALG with negative cc_src target/s390x: Fix LAALG not updating cc_src tests/tcg/s390x: Test CLC with inaccessible second operand target/s390x: Fix CLC corrupting cc_src target/s390x/cpu_models: Use 'first_cpu' in s390_get_feat_block() s390/sclp: fix SCLP facility map tests/avocado: Allow newer versions of tesseract in the nextcube test MAINTAINERS: Add artist.c to the hppa machine section MAINTAINERS: Add the virtio-gpu documentation to the corresponding section Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-08Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into stagingStefan Hajnoczi
Misc hardware patch queue HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe) Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu) Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang) QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe) UI: - Use correct key names in titles on MacOS / SDL2 (Adrian) MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe) Nios2: - Create IRQs *after* vCPU is realized (Philippe) PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe) S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe) X86: - HVF & KVM cleanups (Philippe) Various targets: - Use env_archcpu() to optimize (Philippe) Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t # wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S # vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q # jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi # zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh # ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan # DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM # L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu # DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z # HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY # Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp # 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= # =OVdQ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits) dump: Add close fd on error return to avoid resource leak ui/sdl2: use correct key names in win title on mac MAINTAINERS: Add more guest-agent related files to the corresponding section MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section MAINTAINERS: update libvirt devel mailing list address MAINTAINERS: Add the CAN documentation file to the CAN section MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section hw/sd: Declare QOM types using DEFINE_TYPES() macro hw/i2c: pmbus: reset page register for out of range reads hw/i2c: pmbus: immediately clear faults on request tests/qtest: add tests for ADM1266 hw/sensor: add ADM1266 device model hw/i2c: pmbus: add VCAP register hw/i2c: pmbus: add fan support hw/i2c: pmbus: add vout mode bitfields hw/i2c: pmbus add support for block receive tests/qtest: ahci-test: add test exposing reset issue with pending callback hw/ide: reset: cancel async DMA operation before resetting state hw/cpu: Update the comments of nr_cores and nr_dies system/cpus: Fix CPUState.nr_cores' calculation ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07Xen: Fix xen_set_irq() and xendevicemodel_set_irq_level()Vikram Garhwal
Remove '=' from 'if CONFIG_XEN_CTRL_INTERFACE_VERSION <= 41500'. Because xendevicemodel_set_irq_level() was introduced in 4.15 version. Also, update xendevicemodel_set_irq_level() to return -1 for older versions. Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2023-11-07ppc: qtest already exports qtest_rtas_call()Juan Quintela
Having two functions with the same name is a bad idea. As spapr only uses the function locally, made it static. When you compile with clang, you get this compilation error: /usr/bin/ld: tests/qtest/libqos/libqos.fa.p/.._libqtest.c.o: in function `qtest_rtas_call': /scratch/qemu/clang/full/all/../../../../../mnt/code/qemu/full/tests/qtest/libqtest.c:1195: multiple definition of `qtest_rtas_call'; libqemu-ppc64-softmmu.fa.p/hw_ppc_spapr_rtas.c.o:/scratch/qemu/clang/full/all/../../../../../mnt/code/qemu/full/hw/ppc/spapr_rtas.c:536: first defined here clang-16: error: linker command failed with exit code 1 (use -v to see invocation) ninja: build stopped: subcommand failed. make: *** [Makefile:162: run-ninja] Error 1 Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20231030163834.4638-1-quintela@redhat.com> [dhb: remove 'spapr_rtas.h' include from spapr_rtas.c] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07hw/pci-host: Update PHB5 XSCOM registersSaif Abrar
Add new XSCOM registers introduced in PHB5. Apply bit-masks within xscom-write methods. Bit-masks specified using PPC_BITMASK macro. Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20231016175948.10869-1-saif.abrar@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07ppc/pnv: Fix number of I2C engines and ports for power9/10Glenn Miles
Power9 is supposed to have 4 PIB-connected I2C engines with the following number of ports on each engine: 0: 2 1: 13 2: 2 3: 2 Power10 also has 4 engines but has the following number of ports on each engine: 0: 14 1: 14 2: 2 3: 16 Current code assumes that they all have the same (maximum) number. This can be a problem if software expects to see a certain number of ports present (Power Hypervisor seems to care). Fixed this by adding separate tables for power9 and power10 that map the I2C controller number to the number of I2C buses that should be attached for that engine. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Message-ID: <20231025152714.956664-1-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07ppc/pnv: Connect PNV I2C controller to powernv10Glenn Miles
Wires up four I2C controller instances to the powernv10 chip XSCOM address space. Each controller instance is wired up to two I2C buses of its own. No other I2C devices are connected to the buses at this time. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20231017221434.810363-1-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07ppc/pnv: Connect I2C controller model to powernv9 chipCédric Le Goater
Wires up three I2C controller instances to the powernv9 chip XSCOM address space. Each controller instance is wired up to a single I2C bus of its own. No other I2C devices are connected to the buses at this time. Signed-off-by: Cédric Le Goater <clg@kaod.org> [milesg: Split wiring from addition of model itself] [milesg: Added new commit message] [milesg: Moved hardcoded attributes into PnvChipClass] [milesg: Removed TODO comment for I2C] Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <20231016222013.3739530-3-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07ppc/pnv: Add an I2C controller modelCédric Le Goater
The more recent IBM power processors have an embedded I2C controller that is accessible by software via the XSCOM address space. Each instance of the I2C controller is capable of controlling multiple I2C buses (one at a time). Prior to beginning a transaction on an I2C bus, the bus must be selected by writing the port number associated with the bus into the PORT_NUM field of the MODE register. Once an I2C bus is selected, the status of the bus can be determined by reading the Status and Extended Status registers. I2C bus transactions can be started by writing a command to the Command register and reading/writing data from/to the FIFO register. Not supported : . 10 bit I2C addresses . Multimaster . Slave Signed-off-by: Cédric Le Goater <clg@kaod.org> [milesg: Split wiring to powernv9 into its own commit] [milesg: Added more detail to commit message] [milesg: Added SPDX Licensed Identifier to new files] [milesg: updated copyright dates] [milesg: Added use of g_autofree] [milesg: Added NULL check after pnv_i2c_get_bus] Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <20231016222013.3739530-2-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07s390/sclp: fix SCLP facility mapHeiko Carstens
Qemu's SCLP implementation incorrectly reports that it supports CPU reconfiguration. If a guest issues a CPU reconfiguration request it is rejected as invalid command. Fix the SCLP_HAS_CPU_INFO mask, and remove the unused SCLP_CMDW_CONFIGURE_CPU and SCLP_CMDW_DECONFIGURE_CPU defines. Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Message-ID: <20231024100703.929679-1-hca@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-07hw/pci-host: Add emulation of Mai Logic Articia SBALATON Zoltan
The Articia S is a generic chipset supporting several different CPUs that were among others used on some PPC boards. This is a minimal emulation of the parts needed for emulating the AmigaOne board. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Rene Engel <ReneEngel80@emailn.de> Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <83822787431701cf4d460298d3e3845f362e5da1.1698406922.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07hw/i2c: pmbus: add VCAP registerTitus Rwantare
VCAP is a register for devices with energy storage capacitors. Reviewed-by: Benjamin Streb <bstreb@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-4-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07hw/i2c: pmbus: add fan supportTitus Rwantare
PMBus devices may integrate fans whose operation is configurable over PMBus. This commit allows the driver to read and write the fan control registers but does not model the operation of fans. Reviewed-by: Stephen Longfield <slongfield@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-3-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07hw/i2c: pmbus: add vout mode bitfieldsTitus Rwantare
The VOUT_MODE command is described in the PMBus Specification, Part II, Ver 1.3 Section 8.3 VOUT_MODE has a three bit mode and 4 bit parameter, the three bit mode determines whether voltages are formatted as uint16, uint16, VID, and Direct modes. VID and Direct modes use the remaining 5 bits to scale the voltage readings. Reviewed-by: Hao Wu <wuhaotsh@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-2-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07hw/i2c: pmbus add support for block receiveTitus Rwantare
PMBus devices can send and receive variable length data using the block read and write format, with the first byte in the payload denoting the length. This is mostly used for strings and on-device logs. Devices can respond to a block read with an empty string. Reviewed-by: Hao Wu <wuhaotsh@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-1-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07hw/cpu: Update the comments of nr_cores and nr_diesZhao Liu
In the nr_threads' comment, specify it represents the number of threads in the "core" to avoid confusion. Also add comment for nr_dies in CPUX86State. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Babu Moger <babu.moger@amd.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231024090323.1859210-5-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07hw/i386: Fix comment style in topology.hZhao Liu
For function comments in this file, keep the comment style consistent with other files in the directory. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@Intel.com> Reviewed-by: Babu Moger <babu.moger@amd.com> Tested-by: Babu Moger <babu.moger@amd.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231024090323.1859210-2-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07hw/loader: Clean up global variable shadowing in rom_add_file()Philippe Mathieu-Daudé
Fix: hw/core/loader.c:1073:27: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] bool option_rom, MemoryRegion *mr, ^ include/sysemu/sysemu.h:57:22: note: previous declaration is here extern QEMUOptionRom option_rom[MAX_OPTION_ROMS]; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20231010115048.11856-3-philmd@linaro.org>
2023-11-07hw/cpu: Clean up global variable shadowingPhilippe Mathieu-Daudé
Fix: hw/core/machine.c:1302:22: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const CPUArchId *cpus = possible_cpus->cpus; ^ hw/core/numa.c:69:17: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] uint16List *cpus = NULL; ^ hw/acpi/aml-build.c:2005:20: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] CPUArchIdList *cpus = ms->possible_cpus; ^ hw/core/machine-smp.c:77:14: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] unsigned cpus = config->has_cpus ? config->cpus : 0; ^ include/hw/core/cpu.h:589:17: note: previous declaration is here extern CPUTailQ cpus; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20231010115048.11856-2-philmd@linaro.org>
2023-11-07exec/cpu: Have cpu_exec_realize() return a booleanPhilippe Mathieu-Daudé
Following the example documented since commit e3fe3988d7 ("error: Document Error API usage rules"), have cpu_exec_realizefn() return a boolean indicating whether an error is set or not. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230918160257.30127-22-philmd@linaro.org>
2023-11-07hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()Philippe Mathieu-Daudé
Let CPUClass::class_by_name() handlers to return abstract classes, and filter them once in the public cpu_class_by_name() method. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908112235.75914-3-philmd@linaro.org>
2023-11-07hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU*Philippe Mathieu-Daudé
"hw/s390x/sclp.h" is a header used by target-agnostic objects (such hw/char/sclpconsole[-lm].c), thus can not use target-specific types, such CPUS390XState. Have sclp_service_call[_protected]() take a S390CPU pointer, which is target-agnostic. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231106114500.5269-3-philmd@linaro.org>
2023-11-07hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XStatePhilippe Mathieu-Daudé
"hw/s390x/css.h" is a header used by target-agnostic objects (such hw/s390x/virtio-ccw-gpu.c), thus can not use target-specific types, such CPUS390XState. Have css_do_sic() take S390CPU a pointer, which is target-agnostic. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231106114500.5269-2-philmd@linaro.org>
2023-11-07target/ppc: Move PowerPCCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares the PowerPCCPUClass type. This forward declaration is sufficient for code in hw/ to use the QOM definitions. No need to expose the structure definition. Keep it local to target/ppc/ by moving it to target/ppc/cpu.h. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013125630.95116-5-philmd@linaro.org>
2023-11-07accel: Introduce cpu_exec_reset_hold()Philippe Mathieu-Daudé
Introduce cpu_exec_reset_hold() which call an accelerator specific AccelOpsClass::cpu_reset_hold() handler. Define a stub on TCG user emulation, because CPU reset is irrelevant there. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230918104153.24433-3-philmd@linaro.org>
2023-11-07Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi
into staging virtio,pc,pci: features, fixes virtio sound card support vhost-user: back-end state migration cxl: line length reduction enabling fabric management vhost-vdpa: shadow virtqueue hash calculation Support shadow virtqueue RSS Support tests: CPU topology related smbios test cases Fixes, cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmVKDDoPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpF08H/0Zts8uvkHbgiOEJw4JMHU6/VaCipfIYsp01 # GSfwYOyEsXJ7GIxKWaCiMnWXEm7tebNCPKf3DoUtcAojQj3vuF9XbWBKw/bfRn83 # nGO/iiwbYViSKxkwqUI+Up5YiN9o0M8gBFrY0kScPezbnYmo5u2bcADdEEq6gH68 # D0Ea8i+WmszL891ypvgCDBL2ObDk3qX3vA5Q6J2I+HKX2ofJM59BwaKwS5ghw+IG # BmbKXUZJNjUQfN9dQ7vJuiuqdknJ2xUzwW2Vn612ffarbOZB1DZ6ruWlrHty5TjX # 0w4IXEJPBgZYbX9oc6zvTQnbLDBJbDU89mnme0TcmNMKWmQKTtc= # =vEv+ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 18:06:50 HKT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (63 commits) acpi/tests/avocado/bits: enable console logging from bits VM acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point hw/cxl: Add tunneled command support to mailbox for switch cci. hw/cxl: Add dummy security state get hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions hw/cxl/mbox: Add Get Background Operation Status Command hw/cxl: Add support for device sanitation hw/cxl/mbox: Wire up interrupts for background completion hw/cxl/mbox: Add support for background operations hw/cxl: Implement Physical Ports status retrieval hw/pci-bridge/cxl_downstream: Set default link width and link speed hw/cxl/mbox: Add Physical Switch Identify command. hw/cxl/mbox: Add Information and Status / Identify command hw/cxl: Add a switch mailbox CCI function hw/pci-bridge/cxl_upstream: Move defintion of device to header. hw/cxl/mbox: Generalize the CCI command processing hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState hw/cxl/mbox: Split mailbox command payload into separate input and output hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue. ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07Merge tag 'pull-xenfv.for-upstream-20231107' of ↵Stefan Hajnoczi
git://git.infradead.org/users/dwmw2/qemu into staging Xen PV guest support for 8.2 Add Xen PV console and network support, the former of which enables the Xen "PV shim" to be used to support PV guests. Also clean up the block support and make it work when the user passes just 'drive file=IMAGE,if=xen' on the command line. Update the documentation to reflect all of these, taking the opportunity to simplify what it says about q35 by making unplug work for AHCI. Ignore the VCPU_SSHOTTMR_future timer flag, and advertise the 'fixed' per-vCPU upcall vector support, as newer upstream Xen do. # -----BEGIN PGP SIGNATURE----- # # iQJIBAABCAAyFiEEvgfZ/VSAmrLEsP9fY3Ys2mfi81kFAmVJ/7EUHGR3bXcyQGlu # ZnJhZGVhZC5vcmcACgkQY3Ys2mfi81k+/xAAswivVR4+nwz3wTSN7EboGogS3hy+ # ZsTpvbJnfprGQJAK8vv8OP4eunaCJkO/dy3M/33Dh270msmV6I/1ki0E1RIPG45D # n5wKM1Zxk0ABvjIgdp3xiLwITTdruJ+k9aqV8U9quhjgNFdOa7yjBOG8MD32GEPZ # KHbavJ++huOu7+DZHJRNRq4gI/fREIULoPGHVg7WuEiRDYokOOmMROXqmTHTaUkV # yFhkofzWxlpYhh7qRQx6/A80CSf7xwCof8krjdMCOYj3XGzYVZND0z5ZfHQYEwqt # fowhargA8gH4V3d21S/MWCaZ+QrswFXZhcnl5wuGgWakV4ChvFETKs+fz2mODWUx # 2T13trqeFJ5ElTrSpH1iWCoSEy6KCeLecvx7c/6HPSkDYQ3w5q8dXPpqgEtXY24S # Wcmw4PkQ+HrLX7wbSU7QLyTZjvCQLFZ3Sb0uTf2zwsJZyeCCiT2lqAaogoMm6Kg0 # m/jG1JzE+9AC3j0Upp1lS3EK1qdxIuLdBuIcaEBEjy7Am+Y14PlZYoU2c751KbRF # kqnIOYMoijX0PJDomPqCQtYNE0mrtogo0AbcFFIu+4k25vGbkl7xS5p2du9qw2Rd # ++IdqQYzdzrUcIwmxocFQqFBJQ2dcbOGB1d7+VJ+A1Uj3yY2/DnFG5WqSaqS0KJi # ZhBdFs3OTlPnRoM= # =Dg79 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 17:13:21 HKT # gpg: using RSA key BE07D9FD54809AB2C4B0FF5F63762CDA67E2F359 # gpg: issuer "dwmw2@infradead.org" # gpg: Good signature from "David Woodhouse <dwmw2@infradead.org>" [unknown] # gpg: aka "David Woodhouse <dwmw2@exim.org>" [unknown] # gpg: aka "David Woodhouse <david@woodhou.se>" [unknown] # gpg: aka "David Woodhouse <dwmw2@kernel.org>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: BE07 D9FD 5480 9AB2 C4B0 FF5F 6376 2CDA 67E2 F359 * tag 'pull-xenfv.for-upstream-20231107' of git://git.infradead.org/users/dwmw2/qemu: docs: update Xen-on-KVM documentation xen-platform: unplug AHCI disks hw/i386/pc: support '-nic' for xen-net-device hw/xen: update Xen PV NIC to XenDevice model hw/xen: only remove peers of PCI NICs on unplug hw/xen: add support for Xen primary console in emulated mode hw/xen: update Xen console to XenDevice model hw/xen: do not repeatedly try to create a failing backend device hw/xen: add get_frontend_path() method to XenDeviceClass hw/xen: automatically assign device index to block devices hw/xen: populate store frontend nodes with XenStore PFN/port i386/xen: advertise XEN_HVM_CPUID_UPCALL_VECTOR in CPUID include: update Xen public headers to Xen 4.17.2 release hw/xen: Clean up event channel 'type_val' handling to use union i386/xen: Ignore VCPU_SSHOTTMR_future flag in set_singleshot_timer() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07hw/i386/pc: support '-nic' for xen-net-deviceDavid Woodhouse
The default NIC creation seems a bit hackish to me. I don't understand why each platform has to call pci_nic_init_nofail() from a point in the code where it actually has a pointer to the PCI bus, and then we have the special cases for things like ne2k_isa. If qmp_device_add() can *find* the appropriate bus and instantiate the device on it, why can't we just do that from generic code for creating the default NICs too? But that isn't a yak I want to shave today. Add a xenbus field to the PCMachineState so that it can make its way from pc_basic_device_init() to pc_nic_init() and be handled as a special case like ne2k_isa is. Now we can launch emulated Xen guests with '-nic user'. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-07hw/xen: add support for Xen primary console in emulated modeDavid Woodhouse
The primary console is special because the toolstack maps a page into the guest for its ring, and also allocates the guest-side event channel. The guest's grant table is even primed to export that page using a known grant ref#. Add support for all that in emulated mode, so that we can have a primary console. For reasons unclear, the backends running under real Xen don't just use a mapping of the well-known GNTTAB_RESERVED_CONSOLE grant ref (which would also be in the ring-ref node in XenStore). Instead, the toolstack sets the ring-ref node of the primary console to the GFN of the guest page. The backend is expected to handle that special case and map it with foreignmem operations instead. We don't have an implementation of foreignmem ops for emulated Xen mode, so just make it map GNTTAB_RESERVED_CONSOLE instead. This would probably work for real Xen too, but we can't work out how to make real Xen create a primary console of type "ioemu" to make QEMU drive it, so we can't test that; might as well leave it as it is for now under Xen. Now at last we can boot the Xen PV shim and run PV kernels in QEMU. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-07hw/xen: do not repeatedly try to create a failing backend deviceDavid Woodhouse
If xen_backend_device_create() fails to instantiate a device, the XenBus code will just keep trying over and over again each time the bus is re-enumerated, as long as the backend appears online and in XenbusStateInitialising. The only thing which prevents the XenBus code from recreating duplicates of devices which already exist, is the fact that xen_device_realize() sets the backend state to XenbusStateInitWait. If the attempt to create the device doesn't get *that* far, that's when it will keep getting retried. My first thought was to handle errors by setting the backend state to XenbusStateClosed, but that doesn't work for XenConsole which wants to *ignore* any device of type != "ioemu" completely. So, make xen_backend_device_create() *keep* the XenBackendInstance for a failed device, and provide a new xen_backend_exists() function to allow xen_bus_type_enumerate() to check whether one already exists before creating a new one. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-07hw/xen: add get_frontend_path() method to XenDeviceClassDavid Woodhouse
The primary Xen console is special. The guest's side is set up for it by the toolstack automatically and not by the standard PV init sequence. Accordingly, its *frontend* doesn't appear in …/device/console/0 either; instead it appears under …/console in the guest's XenStore node. To allow the Xen console driver to override the frontend path for the primary console, add a method to the XenDeviceClass which can be used instead of the standard xen_device_get_frontend_path() Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-07hw/xen: automatically assign device index to block devicesDavid Woodhouse
There's no need to force the user to assign a vdev. We can automatically assign one, starting at xvda and searching until we find the first disk name that's unused. This means we can now allow '-drive if=xen,file=xxx' to work without an explicit separate -driver argument, just like if=virtio. Rip out the legacy handling from the xenpv machine, which was scribbling over any disks configured by the toolstack, and didn't work with anything but raw images. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Acked-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-07include: update Xen public headers to Xen 4.17.2 releaseDavid Woodhouse
... in order to advertise the XEN_HVM_CPUID_UPCALL_VECTOR feature, which will come in a subsequent commit. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Acked-by: Paul Durrant <paul@xen.org>
2023-11-07hw/cxl: Add tunneled command support to mailbox for switch cci.Jonathan Cameron
This implementation of tunneling makes the choice that our Type 3 device is a Logical Device (LD) of a Multi-Logical Device (MLD) that just happens to only have one LD for now. Tunneling is supported from a Switch Mailbox CCI (and shortly via MCTP over I2C connected to the switch MCTP CCI) via an outer level to the FM owned LD in the MLD Type 3 device. From there an inner tunnel may be used to access particular LDs. Protocol wise, the following is what happens in a real system but we don't emulate the transports - just the destinations and the payloads. ( Host -> Switch Mailbox CCI - in band FM-API mailbox command or Host -> Switch MCTP CCI - MCTP over I2C using the CXL FM-API MCTP Binding. ) then (if a tunnel command) Switch -> Type 3 FM Owned LD - MCTP over PCI VDM using the CXL FM-API binding (addressed by switch port) then (if unwrapped command also a tunnel command) Type 3 FM Owned LD to LD0 via internal transport (addressed by LD number) or (added shortly) Host to Type 3 FM Owned MCTP CCI - MCTP over I2C using the CXL FM-API MCTP Binding. then (if unwrapped comand is a tunnel comamnd) Type 3 FM Owned LD to LD0 via internal transport. (addressed by LD number) It is worth noting that the tunneling commands over PCI VDM presumably use the appropriate MCTP binding depending on opcode. This may be the CXL FMAPI binding or the CXL Memory Device Binding. Additional commands will need to be added to make this useful beyond testing the tunneling works. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023160806.13206-18-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07hw/cxl: Add support for device sanitationDavidlohr Bueso
Make use of the background operations through the sanitize command, per CXL 3.0 specs. Traditionally run times can be rather long, depending on the size of the media. Estimate times based on: https://pmem.io/documents/NVDIMM_DSM_Interface-V1.8.pdf Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023160806.13206-14-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07hw/cxl/mbox: Wire up interrupts for background completionDavidlohr Bueso
Notify when the background operation is done. Note that for now background commands are only supported on the main Type 3 mailbox. Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023160806.13206-13-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07hw/cxl/mbox: Add support for background operationsDavidlohr Bueso
Support background commands in the mailbox, and update cmd_infostat_bg_op_sts() accordingly. This patch does not implement mbox interrupts upon completion, so the kernel driver must rely on polling to know when the operation is done. Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023160806.13206-12-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-13 05:04:23 +0000