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2017-11-05pci-assign: RemovePaolo Bonzini
Legacy PCI device assignment has been removed from Linux in 4.12, and had been deprecated 2 years ago there. We can remove it from QEMU as well. The ROM loading code was shared with Xen PCI passthrough, so move it to hw/xen. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-10-31sun4m: change TYPE_SUN4M_IOMMU macro from "iommu" to "sun4m-iommu"Mark Cave-Ayland
This is a legacy artifact from when the sun4m IOMMU implementation was the only IOMMU available within QEMU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-10-31sun4m_iommu: remove legacy sparc_iommu_memory_rw() functionMark Cave-Ayland
With the switch to the IOMMU memory region and DMA API, this is no longer required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-10-31sun4m: implement IOMMU translation using IOMMU memory regionMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-10-31sparc32_dma: remove is_ledma hack and replace with memory region aliasMark Cave-Ayland
This hack originated from before the memory region API was introduced, and increased the size of the ledma DMA device to capture incorrect accesses beyond the end of the ledma device. A full analysis can be found on Artyom's blog at http://tyom.blogspot.co.uk/2010/10/bug-in-all-solaris-versions-after-57.html. With the memory API we can now simply alias the incorrect access onto its intended destination allowing us to remove the hack. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-31sparc32_dma: introduce new SPARC32_DMA type container objectMark Cave-Ayland
Create a new SPARC32_DMA container object (including an appropriate container memory region) and add instances of the SPARC32_ESPDMA_DEVICE and SPARC32_LEDMA_DEVICE as child objects. The benefit is that most of the gpio wiring complexity between esp/espdma and lance/ledma is now hidden within the SPARC32_DMA realize function. Since the sun4m IOMMU is already QOMified we can find a reference to it using object_resolve_path_type() allowing us to completely remove all external references to the iommu pointer. Finally we rework sun4m's sparc32_dma_init() to invoke the new SPARC32_DMA object and wire up the remaining board memory regions/IRQs. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-31sparc32_dma: make lance device child of ledma deviceMark Cave-Ayland
This makes it possible to reference the lance device from the ledma device as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-31lance: move TYPE_LANCE and SysBusPCNetState from lance.c to lance.hMark Cave-Ayland
This enables them to be used outside of lance.c. We also update the comment to refer to the SPARC32 lance device rather than the AMD PCNet-II device (of which lance is a register-compatible subset). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> CC: Jason Wang <jasowang@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-31sparc32_dma: make esp device child of espdma deviceMark Cave-Ayland
This makes it possible to reference the esp device from the espdma device as required, and by wiring up the device ourselves in sun4m.c we can drop use of the esp_init() function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-31esp: move TYPE_ESP and SysBusESPState from esp.c to esp.hMark Cave-Ayland
This enables them to be used outside of esp.c. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> CC: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-31sun4m_iommu: move TYPE_SUN4M_IOMMU declaration to sun4m.hMark Cave-Ayland
This is in preparation to allow the type to be used elsewhere. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-31sparc32_dma: move type declarations from sparc32_dma.c to sparc32_dma.hMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-30Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20171030' into ↵Peter Maydell
staging s390x: fixups for 2.11 - missing \r in the BIOS console output - CPU type name is now "s390x-cpu" - fixup for the host-model on z14 and older machine versions # gpg: Signature made Mon 30 Oct 2017 08:34:15 GMT # gpg: using RSA key 0x117BBC80B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" # Primary key fingerprint: F922 9381 A334 08F9 DBAB FBCA 117B BC80 B5A6 1C7C * remotes/borntraeger/tags/s390x-20171030: s390-*.img: update s390 bios with latest fixes s390-ccw: print carriage return with new lines s390x/kvm: use cpu model for gscb on compat machines target/s390x: change CPU type name to "s390x-cpu" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-30Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86/cpu/numa queue, 2017-10-27 # gpg: Signature made Fri 27 Oct 2017 15:17:12 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: (39 commits) x86: Skip check apic_id_limit for Xen numa: fixup parsed NumaNodeOptions earlier mips: r4k: replace cpu_model with cpu_type mips: mipssim: replace cpu_model with cpu_type mips: Magnum/Acer Pica 61: replace cpu_model with cpu_type mips: fulong2e: replace cpu_model with cpu_type mips: malta/boston: replace cpu_model with cpu_type mips: use object_new() instead of gnew()+object_initialize() sparc: leon3: use generic cpu_model parsing sparc: sparc: use generic cpu_model parsing sparc: sun4u/sun4v/niagara: use generic cpu_model parsing sparc: cleanup cpu type name composition tricore: use generic cpu_model parsing tricore: cleanup cpu type name composition unicore32: use generic cpu_model parsing unicore32: cleanup cpu type name composition xtensa: lx60/lx200/ml605/kc705: use generic cpu_model parsing xtensa: sim: use generic cpu_model parsing xtensa: cleanup cpu type name composition sh4: remove SuperHCPUClass::name field ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-30s390x/kvm: use cpu model for gscb on compat machinesChristian Borntraeger
Starting a guest with <os> <type arch='s390x' machine='s390-ccw-virtio-2.9'>hvm</type> </os> <cpu mode='host-model'/> on an IBM z14 results in "qemu-system-s390x: Some features requested in the CPU model are not available in the configuration: gs" This is because guarded storage is fenced for compat machines that did not have guarded storage support. While this prevents future migration abort (by not starting the guest at all), not being able to start a "host-model" guest is very much unexpected. As it turns out, even if we would modify libvirt to not expand the cpu model to contain "gs" for compat machines, it cannot guarantee that a migration will succeed. For example if the kernel changes its features (or the user has nested=1 on one host but not on the other) the migration will fail nevertheless. So instead of fencing "gs" for machines <= 2.9 lets allow it for all machine types that support the CPU model. This will make "host-model" runnable all the time, while relying on the CPU model to reject invalid migration attempts. We also need to change the migration for guarded storage. Additional discussions about host-model are still pending but are out of scope of this patch. Suggested-by: David Hildenbrand <david@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: David Hildenbrand <david@redhat.com> Acked-by: Cornelia Huck <Cornelia Huck <cohuck@redhat.com> Acked-by: Halil Pasic <pasic@linux.vnet.ibm.com>
2017-10-27mips: malta/boston: replace cpu_model with cpu_typeIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1507211474-188400-37-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-27sparc: sun4u/sun4v/niagara: use generic cpu_model parsingIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1507211474-188400-33-git-send-email-imammedo@redhat.com> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-26xen: add a global indicator for grant copy being availableJuergen Gross
The Xen qdisk backend needs to test whether grant copy operations is available in the kernel. Unfortunately this collides with using xengnttab_set_max_grants() on some kernels as this operation has to be the first one after opening the gnttab device. In order to solve this problem test for the availability of grant copy in xen_be_init() opening the gnttab device just for that purpose and closing it again afterwards. Advertise the availability via a global flag and use that flag in the qdisk backend. Signed-off-by: Juergen Gross <jgross@suse.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-10-20s390x: refactor error handling for MSCH handlerHalil Pasic
Simplify the error handling of the MSCH. Let the code detecting the condition tell (in a less ambiguous way) how it's to be handled. No changes in behavior. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-8-pasic@linux.vnet.ibm.com> [CH: fix return code for fctl != 0] Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: refactor error handling for HSCH handlerHalil Pasic
Simplify the error handling of the HSCH. Let the code detecting the condition tell (in a less ambiguous way) how it's to be handled. No changes in behavior. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-7-pasic@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: refactor error handling for CSCH handlerHalil Pasic
Simplify the error handling of the CSCH. Let the code detecting the condition tell (in a less ambiguous way) how it's to be handled. No changes in behavior. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-6-pasic@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: refactor error handling for XSCH handlerHalil Pasic
Simplify the error handling of the XSCH. Let the code detecting the condition tell (in a less ambiguous way) how it's to be handled. No changes in behavior. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-5-pasic@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: improve error handling for SSCH and RSCHHalil Pasic
Simplify the error handling of the SSCH and RSCH handler avoiding arbitrary and cryptic error codes being used to tell how the instruction is supposed to end. Let the code detecting the condition tell how it's to be handled in a less ambiguous way. It's best to handle SSCH and RSCH in one go as the emulation of the two shares a lot of code. For passthrough this change isn't pure refactoring, but changes the way kernel reported EFAULT is handled. After clarifying the kernel interface we decided that EFAULT shall be mapped to unit exception. Same goes for unexpected error codes and absence of required ORB flags. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-4-pasic@linux.vnet.ibm.com> Tested-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> [CH: cosmetic changes] Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/css: IO instr handler ending controlHalil Pasic
CSS code needs to tell the IO instruction handlers located in ioinst.c how the emulated instruction should be ended. Currently this is done by returning generic (POSIX) error codes, and mapping them to outcomes like condition codes. This makes bugs easy to create and hard to recognize. As a preparation for moving away from (mis)using generic error codes for flow control let us introduce a type which tells the instruction handler function how to end the instruction, in a more straight-forward and less ambiguous way. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-3-pasic@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> [CH: cosmetic changes] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/event-facility: variable-length event masksCornelia Huck
The architecture supports masks of variable length for sclp write event mask. We currently only support 4 byte event masks, as that is what Linux uses. Let's extend this to the maximum mask length supported by the architecture and return 0 to the guest for the mask bits we don't support in core. Initial patch by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Message-Id: <1507729193-9747-1-git-send-email-jjherne@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-19Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* TCG 8-byte atomic accesses bugfix (Andrew) * Report disk rotation rate (Daniel) * Report invalid scsi-disk block size configuration (Mark) * KVM and memory API MemoryListener fixes (David, Maxime, Peter Xu) * x86 CPU hotplug crash fix (Igor) * Load/store API documentation (Peter Maydell) * Small fixes by myself and Thomas * qdev DEVICE_DELETED deferral (Michael) # gpg: Signature made Wed 18 Oct 2017 10:56:24 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (29 commits) scsi: reject configurations with logical block size > physical block size qdev: defer DEVICE_DEL event until instance_finalize() Revert "qdev: Free QemuOpts when the QOM path goes away" qdev: store DeviceState's canonical path to use when unparenting qemu-pr-helper: use new libmultipath API watch_mem_write: implement 8-byte accesses notdirty_mem_write: implement 8-byte accesses memory: reuse section_from_flat_range() kvm: simplify kvm_align_section() kvm: region_add and region_del is not called on updates kvm: fix error message when failing to unregister slot kvm: tolerate non-existing slot for log_start/log_stop/log_sync kvm: fix alignment of ram address memory: call log_start after region_add target/i386: trap on instructions longer than >15 bytes target/i386: introduce x86_ld*_code tco: add trace events docs/devel/loads-stores.rst: Document our various load and store APIs nios2: define tcg_env build: remove CONFIG_LIBDECNUMBER ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-18qdev: store DeviceState's canonical path to use when unparentingMichael Roth
device_unparent(dev, ...) is called when a device is unparented, either directly, or as a result of a parent device being finalized, and handles some final cleanup for the device. Part of this includes emiting a DEVICE_DELETED QMP event to notify management, which includes the device's path in the composition tree as provided by object_get_canonical_path(). object_get_canonical_path() assumes the device is still connected to the machine/root container, and will assert otherwise, but in some situations this isn't the case: If the parent is finalized as a result of object_unparent(), it will still be attached to the composition tree at the time any children are unparented as a result of that same call to object_unparent(). However, in some cases, object_unparent() will complete without finalizing the parent device, due to lingering references that won't be released till some time later. One such example is if the parent has MemoryRegion children (which take a ref on their parent), who in turn have AddressSpace's (which take a ref on their regions), since those AddressSpaces get cleaned up asynchronously by the RCU thread. In this case qdev:device_unparent() may be called for a child Device that no longer has a path to the root/machine container, causing object_get_canonical_path() to assert. Fix this by storing the canonical path during realize() so the information will still be available for device_unparent() in such cases. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20171016222315.407-2-mdroth@linux.vnet.ibm.com> [Clear dev->canonical_path at the post_realize_fail label, which is cleaner. Suggested by David Gibson. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-10-17Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.11-20171017' ↵Peter Maydell
into staging ppc patch queue 2017-10-17 Here's the currently accumulated set of ppc patches for qemu. * The biggest set here is the ppc parts of Igor Mammedov's cleanups to cpu model handling * The above also includes a generic patches which are required as prerequisites for the ppc parts. They don't seem to have been merged by Eduardo yet, so I hope they're ok to include here. * Apart from that it's basically just assorted bug fixes and cleanups # gpg: Signature made Tue 17 Oct 2017 05:20:03 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.11-20171017: (34 commits) spapr_cpu_core: rewrite machine type sanity check spapr_pci: fail gracefully with non-pseries machine types spapr: Correct RAM size calculation for HPT resizing ppc: pnv: consolidate type definitions and batch register them ppc: pnv: drop PnvChipClass::cpu_model field ppc: pnv: define core types statically ppc: pnv: drop PnvCoreClass::cpu_oc field ppc: pnv: normalize core/chip type names ppc: pnv: use generic cpu_model parsing ppc: spapr: use generic cpu_model parsing ppc: move ppc_cpu_lookup_alias() before its first user ppc: spapr: use cpu model names as tcg defaults instead of aliases ppc: spapr: register 'host' core type along with the rest of core types ppc: spapr: use cpu type name directly ppc: spapr: define core types statically ppc: move '-cpu foo,compat=xxx' parsing into ppc_cpu_parse_featurestr() ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model() ppc: 40p/prep: replace cpu_model with cpu_type ppc: virtex-ml507: replace cpu_model with cpu_type ppc: replace cpu_model with cpu_type on ref405ep,taihu boards ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-17ppc: pnv: drop PnvChipClass::cpu_model fieldIgor Mammedov
deduce core type directly from chip type instead of maintaining type mapping in PnvChipClass::cpu_model. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: pnv: drop PnvCoreClass::cpu_oc fieldIgor Mammedov
deduce cpu type directly from core type instead of maintaining type mapping in PnvCoreClass::cpu_oc and doing extra cpu_model parsing in pnv_core_class_init() Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: pnv: normalize core/chip type namesIgor Mammedov
typically for cpus/core type names following convention is used new_type_prefix-superclass_typename make PNV core/chip to follow common convention. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: pnv: use generic cpu_model parsingIgor Mammedov
use common cpu_model prasing in vl.c and set default cpu_model using generic MachineClass::default_cpu_type. Beside of switching to generic infrastructure it solves several issues. * ppc_cpu_class_by_name() is used to deal with lower/upper case and alias translations into actual cpu type, which fixes '-M powernv -cpu power8' and '-M powernv -cpu power9_v1.0' usecases which error out with: 'invalid CPU model 'FOO' for powernv machine' * allows to switch to lower-case typenames in pnv chip/core name (by convention typnames should be lower-case) * replace aliased names /power8, power9, .../ with exact cpu model names (i.e. typenames should be stable but aliases might decide to point to other cpu model withi family or changed by kvm). It will also help to simplify pnv_chip/core code and get rid of dependency on cpu_model parsing. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [dwg: Updated to make DD2.0 as default POWER9 chip] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: use generic cpu_model parsingIgor Mammedov
use generic cpu_model parsing introduced by (6063d4c0f vl.c: convert cpu_model to cpu type and set of global properties before machine_init()) it allows to: * replace sPAPRMachineClass::tcg_default_cpu with MachineClass::default_cpu_type * drop cpu_parse_cpu_model() from hw/ppc/spapr.c and reuse one in vl.c * simplify spapr_get_cpu_core_type() by removing not needed anymore recurrsion since alias look up happens earlier at vl.c and spapr_get_cpu_core_type() works only with resulted from that cpu type. * spapr no more needs to parse/depend on being phased out MachineState::cpu_model, all tha parsing done by generic code and target specific callback. Signed-off-by: Igor Mammedov <imammedo@redhat.com> [dwg: Correct minor compile error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: register 'host' core type along with the rest of core typesIgor Mammedov
consolidate 'host' core type registration by moving it from KVM specific code into spapr_cpu_core.c, similar like it's done in x86 target. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: use cpu type name directlyIgor Mammedov
replace sPAPRCPUCoreClass::cpu_class with cpu type name since it were needed just to get that at points it were accessed. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: define core types staticallyIgor Mammedov
spapr core type definition doesn't have any fields that require it to be defined at runtime. So replace code that fills in TypeInfo at runtime with static TypeInfo array that does the same at complie time. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: move '-cpu foo,compat=xxx' parsing into ppc_cpu_parse_featurestr()Igor Mammedov
there is a dedicated callback CPUClass::parse_features which purpose is to convert -cpu features into a set of global properties AND deal with compat/legacy features that couldn't be directly translated into CPU's properties. Create ppc variant of it (ppc_cpu_parse_featurestr) and move 'compat=val' handling from spapr_cpu_core.c into it. That removes a dependency of board/core code on cpu_model parsing and would let to reuse common -cpu parsing introduced by 6063d4c0 Set "max-cpu-compat" property only if it exists, in practice it should limit 'compat' hack to spapr machine and allow to avoid including machine/spapr headers in target/ppc/cpu.c Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model()Igor Mammedov
ppc_cpu_parse_features() is doing practically the same thing as generic cpu_parse_cpu_model(). So remove duplicated impl. and reuse generic one. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-16include/hw/or-irq.h: Drop unused in_irqs fieldPeter Maydell
The struct OrIRQState has an unused member field in_irqs. This is a legacy of earlier versions of the patch; the code that used it was dropped from the final version of the code that went into master, but we forgot to delete the no-longer-used struct field. Do so now. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-10-15pci: conventional-pci-device and pci-express-device interfacesEduardo Habkost
Those two interfaces will be used to indicate which device types support Conventional PCI or PCI Express buses. Management software will be able to use the qom-list-types QMP command to query that information. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15hw/misc: add vmcoreinfo deviceMarc-André Lureau
See docs/specs/vmcoreinfo.txt for details. "etc/vmcoreinfo" fw_cfg entry is added when using "-device vmcoreinfo". Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15fw_cfg: add write callbackMarc-André Lureau
Reintroduce the write callback that was removed when write support was removed in commit 023e3148567ac898c7258138f8e86c3c2bb40d07. Contrary to the previous callback implementation, the write_cb callback is called whenever a write happened, so handlers must be ready to handle partial write as necessary. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-12arm: fix armv7m_init() declaration to match definitionIgor Mammedov
s/cpu_model/cpu_type/ that has been forgotten during conversion (ba1ba5cc), while touching the line also fixup alignment. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1507710805-221721-1-git-send-email-imammedo@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-12ide: support reporting of rotation rateDaniel P. Berrange
The Linux kernel will query the ATA IDENTITY DEVICE data, word 217 to determine the rotations per minute of the disk. If this has the value 1, it is taken to be an SSD and so Linux sets the 'rotational' flag to 0 for the I/O queue and will stop using that disk as a source of random entropy. Other operating systems may also take into account rotation rate when setting up default behaviour. Mgmt apps should be able to set the rotation rate for virtualized block devices, based on characteristics of the host storage in use, so that the guest OS gets sensible behaviour out of the box. This patch thus adds a 'rotation-rate' parameter for 'ide-hd' device types. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <20171004114008.14849-3-berrange@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-10-09machine: Add a valid_cpu_types propertyAlistair Francis
This patch add a MachineClass element that can be set in the machine C code to specify a list of supported CPU types. If the supported CPU types are specified the user enter CPU (by -cpu at runtime) is checked against the supported types and QEMU exits if they aren't supported. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <b8474e9d2e0a219d9bac901342f983b13d009301.1507059418.git.alistair.francis@xilinx.com> [ehabkost: removed assert(), rewrote comment] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-06s390x/3270: IDA support for 3270 via CcwDataStreamHalil Pasic
Let us convert the 3270 code so it uses the recently introduced CcwDataStream abstraction instead of blindly assuming direct data access. This patch does not change behavior beyond introducing IDA support: for direct data access CCWs everything stays as-is. (If there are bugs, they are also preserved). Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Message-Id: <20170920172314.102710-2-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06390x/css: introduce maximum data address checkingHalil Pasic
The architecture mandates the addresses to be accessed on the first indirection level (that is, the data addresses without IDA, and the (M)IDAW addresses with (M)IDA) to be checked against an CCW format dependent limit maximum address. If a violation is detected, the storage access is not to be performed and a channel program check needs to be generated. As of today, we fail to do this check. Let us stick even closer to the architecture specification. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20170921180841.24490-5-pasic@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/css: introduce css data streamHalil Pasic
This is a preparation for introducing handling for indirect data addressing and modified indirect data addressing (CCW). Here we introduce an interface which should make the addressing scheme transparent for the client code. Here we implement only the basic scheme (no IDA or MIDA). Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Message-Id: <20170921180841.24490-2-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-29virtio-input: send rel-wheel events for wheel buttonsGerd Hoffmann
qemu uses wheel-up/down button events for mouse wheel input, however linux applications typically want REL_WHEEL events. This fixes wheel with linux guests. Tested with X11/wayland, and windows virtio-input driver. Based on a patch from Marc. Added property to enable/disable wheel axis. Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20170926113243.26081-1-kraxel@redhat.com
2017-09-27Merge remote-tracking branch ↵Peter Maydell
'remotes/dgilbert/tags/pull-migration-20170927a' into staging Migration pull 2017-09-27 # gpg: Signature made Wed 27 Sep 2017 14:56:23 BST # gpg: using RSA key 0x0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-migration-20170927a: migration: Route more error paths migration: Route errors up through vmstate_save migration: wire vmstate_save_state errors up to vmstate_subsection_save migration: Check field save returns migration: check pre_save return in vmstate_save_state migration: pre_save return int migration: disable auto-converge during bulk block migration Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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