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AgeCommit message (Expand)Author
2021-09-30spapr_numa.c: parametrize FORM1 macrosDaniel Henrique Barboza
2021-09-29ppc/pnv: Rename "id" to "quad-id" in PnvQuadCédric Le Goater
2021-09-29ppc/xive: Export xive_tctx_word2() helperCédric Le Goater
2021-09-29ppc/xive: Export priority_to_ipb() helperCédric Le Goater
2021-09-29nubus: add support for slot IRQsMark Cave-Ayland
2021-09-29nubus-bridge: embed the NubusBus object directly within nubus-bridgeMark Cave-Ayland
2021-09-29nubus: move NubusBus from mac-nubus-bridge to nubus-bridgeMark Cave-Ayland
2021-09-29mac-nubus-bridge: rename MacNubusState to MacNubusBridgeMark Cave-Ayland
2021-09-29nubus-bridge: introduce separate NubusBridge structureMark Cave-Ayland
2021-09-29nubus: move nubus to its own 32-bit address spaceMark Cave-Ayland
2021-09-29nubus-device: add romfile property for loading declaration ROMsMark Cave-Ayland
2021-09-29nubus-device: remove nubus_register_rom() and nubus_register_format_block()Mark Cave-Ayland
2021-09-29nubus: use bitmap to manage available slotsMark Cave-Ayland
2021-09-29nubus-device: expose separate super slot memory regionMark Cave-Ayland
2021-09-29nubus-device: rename slot_nb variable to slotMark Cave-Ayland
2021-09-27hw/loader: Restrict PC_ROM_* definitions to hw/i386/pcPhilippe Mathieu-Daudé
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson
2021-09-21Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis
2021-09-21hw/timer: Add SiFive PWM supportAlistair Francis
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: sifive_clint: Use RISC-V CPU GPIO linesAlistair Francis
2021-09-20hw/arm/aspeed: Allow machine to set UART defaultPeter Delevoryas
2021-09-20aspeed: Emulate the AST2600A3Joel Stanley
2021-09-20watchdog: aspeed: Sanitize control register valuesAndrew Jeffery
2021-09-16Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.2-pul...Peter Maydell
2021-09-15qdev: Complete qdev_init_gpio_out() documentationPhilippe Mathieu-Daudé
2021-09-14accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemuPhilippe Mathieu-Daudé
2021-09-14accel/tcg: Rename user-mode do_interrupt hack as fake_user_interruptPhilippe Mathieu-Daudé
2021-09-13qdev: Support marking individual buses as 'full'Peter Maydell
2021-09-13hw/arm/virt: add ITS support in virt GICShashi Mallela
2021-09-13hw/intc: GICv3 redistributor ITS processingShashi Mallela
2021-09-13hw/intc: GICv3 ITS Feature enablementShashi Mallela
2021-09-13hw/intc: GICv3 ITS Command processingShashi Mallela
2021-09-13hw/intc: GICv3 ITS register definitions addedShashi Mallela
2021-09-13hw/intc: GICv3 ITS initial frameworkShashi Mallela
2021-09-08mac_via: add qdev gpios for nubus slot interrupts to VIA2Mark Cave-Ayland
2021-09-08mac_via: rename VIA2_IRQ_SLOT_BIT to VIA2_IRQ_NUBUS_BITMark Cave-Ayland
2021-09-08mac_via: remove mac_via deviceMark Cave-Ayland
2021-09-08mac_via: move ADB variables to MOS6522Q800VIA1StateMark Cave-Ayland
2021-09-08mac_via: move PRAM/RTC variables to MOS6522Q800VIA1StateMark Cave-Ayland
2021-09-08mac_via: move PRAM contents and block backend to MOS6522Q800VIA1StateMark Cave-Ayland
2021-09-06s390x: Replace PAGE_SIZE, PAGE_SHIFT and PAGE_MASKThomas Huth
2021-09-06hw/s390x/s390-skeys: lazy storage key enablement under TCGDavid Hildenbrand
2021-09-06hw/s390x/s390-skeys: rename skeys_enabled to skeys_are_enabledDavid Hildenbrand
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