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2020-06-23Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200623' into staging target-arm queue: * util/oslib-posix : qemu_init_exec_dir implementation for Mac * target/arm: Last parts of neon decodetree conversion * hw/arm/virt: Add 5.0 HW compat props * hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status * mps2: Add CMSDK APB watchdog, FPGAIO block, S2I devices and I2C devices * mps2: Add some unimplemented-device stubs for audio and GPIO * mps2-tz: Use the ARM SBCon two-wire serial bus interface * target/arm: Check supported KVM features globally (not per vCPU) * tests/qtest/arm-cpu-features: Add feature setting tests * arm/virt: Add memory hot remove support # gpg: Signature made Tue 23 Jun 2020 12:38:31 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200623: (42 commits) arm/virt: Add memory hot remove support tests/qtest/arm-cpu-features: Add feature setting tests target/arm: Check supported KVM features globally (not per vCPU) hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface hw/arm/mps2: Add audio I2S interface as unimplemented device hw/arm/mps2: Add I2C devices hw/arm/mps2: Add SPI devices hw/arm/mps2: Map the FPGA I/O block hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices hw/arm/mps2: Add CMSDK APB watchdog device hw/arm/mps2: Rename CMSDK AHB peripheral region hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string hw/i2c: Add header for ARM SBCon two-wire serial bus interface hw/i2c/versatile_i2c: Add SCL/SDA definitions hw/i2c/versatile_i2c: Add definitions for register addresses hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status target/arm: Remove dead code relating to SABA and UABA target/arm: Remove unnecessary gen_io_end() calls target/arm: Move some functions used only in translate-neon.inc.c to that file ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23qdev: Make qdev_prop_set_drive() match the other helpersMarkus Armbruster
qdev_prop_set_drive() can fail. None of the other qdev_prop_set_FOO() can; they abort on error. To clean up this inconsistency, rename qdev_prop_set_drive() to qdev_prop_set_drive_err(), and create a qdev_prop_set_drive() that aborts on error. Coccinelle script to update callers: @ depends on !(file in "hw/core/qdev-properties-system.c")@ expression dev, name, value; symbol error_abort; @@ - qdev_prop_set_drive(dev, name, value, &error_abort); + qdev_prop_set_drive(dev, name, value); @@ expression dev, name, value, errp; @@ - qdev_prop_set_drive(dev, name, value, errp); + qdev_prop_set_drive_err(dev, name, value, errp); Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200622094227.1271650-14-armbru@redhat.com>
2020-06-23qdev: Improve netdev property override error a bitMarkus Armbruster
qdev_prop_set_netdev() fails when the property already has a non-null value. Seems to go back to commit 30c367ed44 "qdev-properties-system.c: Allow vlan or netdev for -device, not both", v1.7.0. Board code doesn't expect failure, and crashes: $ qemu-system-x86_64 --nodefaults -nic user -netdev user,id=nic0 -global e1000.netdev=nic0 Unexpected error in error_set_from_qdev_prop_error() at /work/armbru/qemu/hw/core/qdev-properties.c:1101: qemu-system-x86_64: Property 'e1000.netdev' doesn't take value '__org.qemu.nic0 ' Aborted (core dumped) -device and device_add handle the failure: $ qemu-system-x86_64 -nodefaults -netdev user,id=net0 -netdev user,id=net1 -device e1000,netdev=net0,netdev=net1 qemu-system-x86_64: -device e1000,netdev=net0,netdev=net1: Property 'e1000.netdev' doesn't take value 'net1' $ qemu-system-x86_64 -nodefaults -S -display none -monitor stdio -netdev user,id=net0 -netdev user,id=net1 -global e1000.netdev=net0 QEMU 5.0.50 monitor - type 'help' for more information (qemu) qemu-system-x86_64: warning: netdev net0 has no peer qemu-system-x86_64: warning: netdev net1 has no peer device_add e1000,netdev=net1 Error: Property 'e1000.netdev' doesn't take value 'net1' Perhaps netdev property override could be made to work. Perhaps it should. I'm not the right guy to figure this out. What I can do is improve the error message a bit: (qemu) device_add e1000,netdev=net1 Error: -global e1000.netdev=... conflicts with netdev=net1 Cc: Jason Wang <jasowang@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200622094227.1271650-11-armbru@redhat.com>
2020-06-23fdc: Open-code fdctrl_init_isa()Markus Armbruster
Helper function fdctrl_init_isa() is less than helpful: one of three places creating "isa-fdc" devices use it. Open-code it there, and drop the function. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200622094227.1271650-6-armbru@redhat.com>
2020-06-23fdc: Reject clash between -drive if=floppy and -global isa-fdcMarkus Armbruster
The floppy controller devices desugar their drive properties into floppy devices (since commit a92bd191a4 "fdc: Move qdev properties to FloppyDrive", v2.8.0). This involves some bad magic in fdctrl_connect_drives(), and exists for backward compatibility. The functions for boards to create floppy controller devices fdctrl_init_isa(), fdctrl_init_sysbus(), and sun4m_fdctrl_init() desugar -drive if=floppy to these floppy controller drive properties. If you use both -drive if=floppy (or its -fda / -fdb sugar) and -global isa-fdc for the same floppy device, -global silently loses the conflict, and both backends involved end up with the floppy device frontend attached, as demonstrated by iotest 172 (see commit before previous). This is wrong. Desugar -drive if=floppy straight to floppy devices instead, with helper fdctrl_init_drives(). The conflict now gets rejected cleanly: first, fdctrl_connect_drives() creates the floppy for the controller's property, then fdctrl_init_drives() attempts to create the floppy for -drive if=floppy, but fails because the unit is already in use. Output of iotest 172 changes in three ways: 1. The clash gets rejected. 2. In one test case, "info qtree" has the floppy devices swapped, and "info block" has their QOM paths swapped. This is because the floppy device for -fda now gets created after the one for -global isa-fdc.driveB. 3. The error message for -global floppy.drive=floppy0 changes. Before the patch, we set isa-fdc.driveA to -fda's block backend, then create the floppy device for it, then move the backend from isa-fdc.driveA to floppy.drive. Floppy creation fails when applying -global floppy.drive=floppy0, because floppy0 is still attached to isa-fdc. After the patch, we create the floppy for -fda, then set its drive property to floppy0. Now floppy creation succeeds, but setting the drive property fails, because -global already set it. Yes, this is exasperatingly complicated. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200622094227.1271650-5-armbru@redhat.com>
2020-06-23hw/i2c: Add header for ARM SBCon two-wire serial bus interfacePhilippe Mathieu-Daudé
'ARM SBCon two-wire serial bus interface' is the official name describing the pair of registers used to bitbanging I2C in the Versatile boards. Make the private VersatileI2CState structure as public ArmSbconI2CState. Add the TYPE_ARM_SBCON_I2C, alias to our current TYPE_VERSATILE_I2C model. Rename the memory region description as 'arm_sbcon_i2c'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200617072539.32686-5-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-22hw/rx: Add RX GDB simulatorYoshinori Sato
Add the RX machine internally simulated in GDB. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI, renamed CPU -> MCU, device -> microcontroller] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200224141923.82118-18-ysato@users.sourceforge.jp> [PMD: Split of MCU, rename gdbsim, Add gdbsim-r5f562n7/r5f562n8] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-22hw/rx: Register R5F562N7 and R5F562N8 MCUsPhilippe Mathieu-Daudé
Make the current TYPE_RX62N_MCU an abstract class, and generate TYPE_R5F562N7_MCU and TYPE_R5F562N8_MCU models. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-22hw/rx: RX62N microcontroller (MCU)Yoshinori Sato
rx62n - RX62N cpu. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI, renamed CPU -> MCU, device -> microcontroller] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200224141923.82118-18-ysato@users.sourceforge.jp> [PMD: Rebased on b77b5b3dc7, split of machine, use &error_abort] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-22hw/char: RX62N serial communication interface (SCI)Yoshinori Sato
This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-17-ysato@users.sourceforge.jp> [PMD: Filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-22hw/timer: RX62N compare match timer (CMT)Yoshinori Sato
renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp> [PMD: Split from TMR, filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-22hw/timer: RX62N 8-Bit timer (TMR)Yoshinori Sato
renesas_tmr: 8bit timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp> [PMD: Split from CMT, filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-22hw/intc: RX62N interrupt controller (ICUa)Yoshinori Sato
This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-15-ysato@users.sourceforge.jp> [PMD: Fill VMStateField for migration, cover files in MAINTAINERS] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-22hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h'Philippe Mathieu-Daudé
Extract timer definitions to 'hw/timer/tmu012.h'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-22hw/sh4: Use MemoryRegion typedefPhilippe Mathieu-Daudé
Use the MemoryRegion type defined in "qemu/typedefs.h", to keep the repository style consistent. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng
It is enough to simply map the SiFive FU540 DDR memory controller into the MMIO space using create_unimplemented_device(), to make the upstream U-Boot v2020.07 DDR memory initialization codes happy. Note we do not generate device tree fragment for the DDR memory controller. Since the controller data in device tree consumes a very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the U-Boot source), and it is only needed by U-Boot SPL but not any operating system, we choose not to generate the fragment here. This also means when testing with U-Boot SPL, the device tree has to come from U-Boot SPL itself, but not the one generated by QEMU on the fly. The memory has to be set to 8GiB to match the real HiFive Unleashed board when invoking QEMU (-m 8G). With this commit, QEMU can boot U-Boot SPL built for SiFive FU540 all the way up to loading U-Boot proper from MMC: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800) Trying to boot from MMC1 Unhandled exception: Load access fault EPC: 0000000008009be6 TVAL: 0000000010050014 The above exception is expected because QSPI is unsupported yet. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-6-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng
SiFive FU540 SoC supports booting from several sources, which are controlled using the Mode Select (MSEL[3:0]) pins on the chip. Typically, the boot process runs through several stages before it begins execution of user-provided programs. The SoC supports booting from memory-mapped QSPI flash, which is how start_in_flash property is used for at present. This matches MSEL = 1 configuration (QSPI0). Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL). It's not necessary for QEMU to implement the full ZSBL ROM codes, because we know ZSBL downloads the next stage program into the L2 LIM at address 0x8000000 and executes from there. We can bypass the whole ZSBL execution and use "-bios" to load the next stage program directly if MSEL indicates a ZSBL booting flow. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-4-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng
On SiFive FU540 SoC, the value stored at physical address 0x1000 stores the MSEL pin state that is used to control the next boot location that ROM codes jump to. Add a new property msel to sifive_u machine for this. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-12-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-12-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng
SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines. This hooks the exsiting SiFive GPIO model to the SoC, and adds its device tree data as well. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-8-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng
Add a new property to represent the number of GPIO pins supported by the GPIO controller. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-7-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng
Do various minor clean-ups to the exisiting codes for: - coding convention conformance - remove unnecessary blank lines - spell SiFive correctly Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-6-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-19hw/intc: Initial commit of lowRISC Ibex PLICAlistair Francis
The Ibex core contains a PLIC that although similar to the RISC-V spec is not RISC-V spec compliant. This patch implements a Ibex PLIC in a somewhat generic way. As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex PLIC move towards spec compliance this PLIC implementation can be updated until it can replace the current PLIC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis
This is the initial commit of the Ibex UART device. Serial TX is working, while RX has been implemeneted but untested. This is based on the documentation from: https://docs.opentitan.org/hw/ip/uart/doc/ Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
2020-06-19sifive_e: Support the revB machineAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into stagingPeter Maydell
s390x update: - update Linux headers to 5.8-rc1 (for vfio-ccw path handling) - vfio-ccw: add support for path handling - documentation fix # gpg: Signature made Thu 18 Jun 2020 16:36:04 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [marginal] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [marginal] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [marginal] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20200618: docs/s390x: fix vfio-ap device_del description vfio-ccw: Add support for the CRW region and IRQ s390x/css: Refactor the css_queue_crw() routine vfio-ccw: Refactor ccw irq handler vfio-ccw: Add support for the schib region vfio-ccw: Refactor cleanup of regions Linux headers: update Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-18Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Thu 18 Jun 2020 14:16:22 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: (33 commits) net: Drop the NetLegacy structure, always use Netdev instead net: Drop the legacy "name" parameter from the -net option hw/net/e1000e: Do not abort() on invalid PSRCTL register value colo-compare: Fix memory leak in packet_enqueue() net/colo-compare.c: Correct ordering in complete and finalize net/colo-compare.c: Check that colo-compare is active net/colo-compare.c: Only hexdump packets if tracing is enabled net/colo-compare.c: Fix deadlock in compare_chr_send chardev/char.c: Use qemu_co_sleep_ns if in coroutine net/colo-compare.c: Create event_bh with the right AioContext net: use peer when purging queue in qemu_flush_or_purge_queue_packets() net: cadence_gem: Fix RX address filtering net: cadence_gem: TX_LAST bit should be set by guest net: cadence_gem: Update the reset value for interrupt mask register net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg net: cadence_gem: Add support for jumbo frames net: cadence_gem: Fix up code style net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState net: cadence_gem: Set ISR according to queue in use net: cadence_gem: Define access permission for interrupt registers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-18net: cadence_gem: Add support for jumbo framesSai Pavan Boddu
Add a property "jumbo-max-len", which sets default value of jumbo frames up to 16,383 bytes. Add Frame length checks for standard and jumbo frames. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2020-06-18net: cadence_gem: Move tx/rx packet buffert to CadenceGEMStateSai Pavan Boddu
Moving this buffers to CadenceGEMState, as their size will be increased more when JUMBO frames support is added. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2020-06-18virtio-net: reference implementation of hash reportYuri Benditovich
Suggest VIRTIO_NET_F_HASH_REPORT if specified in device parameters. If the VIRTIO_NET_F_HASH_REPORT is set, the device extends configuration space. If the feature is negotiated, the packet layout is extended to accomodate the hash information. In this case deliver packet's hash value and report type in virtio header extension. Use for configuration the same procedure as already used for RSS. We add two fields in rss_data that controls what the device does with the calculated hash if rss_data.enabled is set. If field 'populate' is set the hash is set in the packet, if field 'redirect' is set the hash is used to decide the queue to place the packet to. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2020-06-18virtio-net: implement RX RSS processingYuri Benditovich
If VIRTIO_NET_F_RSS negotiated and RSS is enabled, process incoming packets, calculate packet's hash and place the packet into respective RX virtqueue. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2020-06-18virtio-net: implement RSS configuration commandYuri Benditovich
Optionally report RSS feature. Handle RSS configuration command and keep RSS parameters in virtio-net device context. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2020-06-18Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block layer patches: - enhance handling of size-related BlockConf properties - nvme: small fixes, refactoring and cleanups - virtio-blk: On restart, process queued requests in the proper context - icount: make dma reads deterministic - iotests: Some fixes for rarely run cases - .gitignore: Ignore storage-daemon files - Minor code cleanups # gpg: Signature made Wed 17 Jun 2020 15:47:19 BST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (43 commits) iotests: Add copyright line in qcow2.py iotests/{190,291}: compat=0.10 is unsupported iotests/229: data_file is unsupported iotests/292: data_file is unsupported iotests/041: Skip test_small_target for qed iotests.py: Add skip_for_formats() decorator block: lift blocksize property limit to 2 MiB qdev-properties: add getter for size32 and blocksize block: make BlockConf size props 32bit and accept size suffixes qdev-properties: make blocksize accept size suffixes qdev-properties: add size32 property type qdev-properties: blocksize: use same limits in code and description block: consolidate blocksize properties consistency checks virtio-blk: store opt_io_size with correct size .gitignore: Ignore storage-daemon files hw/block/nvme: verify msix_init_exclusive_bar() return value hw/block/nvme: add msix_qsize parameter hw/block/nvme: Verify msix_vector_use() returned value hw/block/nvme: factor out controller identify setup hw/block/nvme: do cmb/pmr init as part of pci init ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-18s390x/css: Refactor the css_queue_crw() routineEric Farman
We have a use case (vfio-ccw) where a CRW is already built and ready to use. Rather than teasing out the components just to reassemble it later, let's rework this code so we can queue a fully-qualified CRW directly. Signed-off-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200505125757.98209-6-farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-18vfio-ccw: Add support for the schib regionFarhan Ali
The schib region can be used to obtain the latest SCHIB from the host passthrough subchannel. Since the guest SCHIB is virtualized, we currently only update the path related information so that the guest is aware of any path related changes when it issues the 'stsch' instruction. Signed-off-by: Farhan Ali <alifm@linux.ibm.com> Signed-off-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200505125757.98209-4-farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-17block: make BlockConf size props 32bit and accept size suffixesRoman Kagan
Convert all size-related properties in BlockConf to 32bit. This will accommodate bigger block sizes (in a followup patch). This also allows to make them all accept size suffixes, either via DEFINE_PROP_BLOCKSIZE or via DEFINE_PROP_SIZE32. Also, since min_io_size is exposed to the guest by scsi and virtio-blk devices as an uint16_t in units of logical blocks, introduce an additional check in blkconf_blocksizes to prevent its silent truncation. Signed-off-by: Roman Kagan <rvkagan@yandex-team.ru> Message-Id: <20200528225516.1676602-7-rvkagan@yandex-team.ru> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2020-06-17qdev-properties: add size32 property typeRoman Kagan
Introduce size32 property type which handles size suffixes (k, m, g) just like size property, but is uint32_t rather than uint64_t. It's going to be useful for properties that are byte sizes but are inherently 32bit, like BlkConf.opt_io_size or .discard_granularity (they are switched to this new property type in a followup commit). The getter for size32 is left out for a separate patch as its benefit is less obvious, and it affects test output; for now the regular uint32 getter is used. Signed-off-by: Roman Kagan <rvkagan@yandex-team.ru> Message-Id: <20200528225516.1676602-5-rvkagan@yandex-team.ru> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2020-06-17block: consolidate blocksize properties consistency checksRoman Kagan
Several block device properties related to blocksize configuration must be in certain relationship WRT each other: physical block must be no smaller than logical block; min_io_size, opt_io_size, and discard_granularity must be a multiple of a logical block. To ensure these requirements are met, add corresponding consistency checks to blkconf_blocksizes, adjusting its signature to communicate possible error to the caller. Also remove the now redundant consistency checks from the specific devices. Signed-off-by: Roman Kagan <rvkagan@yandex-team.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Message-Id: <20200528225516.1676602-3-rvkagan@yandex-team.ru> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2020-06-17virtio-blk: On restart, process queued requests in the proper contextSergio Lopez
On restart, we were scheduling a BH to process queued requests, which would run before starting up the data plane, leading to those requests being assigned and started on coroutines on the main context. This could cause requests to be wrongly processed in parallel from different threads (the main thread and the iothread managing the data plane), potentially leading to multiple issues. For example, stopping and resuming a VM multiple times while the guest is generating I/O on a virtio_blk device can trigger a crash with a stack tracing looking like this one: <------> Thread 2 (Thread 0x7ff736765700 (LWP 1062503)): #0 0x00005567a13b99d6 in iov_memset (iov=0x6563617073206f4e, iov_cnt=1717922848, offset=516096, fillc=0, bytes=7018105756081554803) at util/iov.c:69 #1 0x00005567a13bab73 in qemu_iovec_memset (qiov=0x7ff73ec99748, offset=516096, fillc=0, bytes=7018105756081554803) at util/iov.c:530 #2 0x00005567a12f411c in qemu_laio_process_completion (laiocb=0x7ff6512ee6c0) at block/linux-aio.c:86 #3 0x00005567a12f42ff in qemu_laio_process_completions (s=0x7ff7182e8420) at block/linux-aio.c:217 #4 0x00005567a12f480d in ioq_submit (s=0x7ff7182e8420) at block/linux-aio.c:323 #5 0x00005567a12f43d9 in qemu_laio_process_completions_and_submit (s=0x7ff7182e8420) at block/linux-aio.c:236 #6 0x00005567a12f44c2 in qemu_laio_poll_cb (opaque=0x7ff7182e8430) at block/linux-aio.c:267 #7 0x00005567a13aed83 in run_poll_handlers_once (ctx=0x5567a2b58c70, timeout=0x7ff7367645f8) at util/aio-posix.c:520 #8 0x00005567a13aee9f in run_poll_handlers (ctx=0x5567a2b58c70, max_ns=16000, timeout=0x7ff7367645f8) at util/aio-posix.c:562 #9 0x00005567a13aefde in try_poll_mode (ctx=0x5567a2b58c70, timeout=0x7ff7367645f8) at util/aio-posix.c:597 #10 0x00005567a13af115 in aio_poll (ctx=0x5567a2b58c70, blocking=true) at util/aio-posix.c:639 #11 0x00005567a109acca in iothread_run (opaque=0x5567a2b29760) at iothread.c:75 #12 0x00005567a13b2790 in qemu_thread_start (args=0x5567a2b694c0) at util/qemu-thread-posix.c:519 #13 0x00007ff73eedf2de in start_thread () at /lib64/libpthread.so.0 #14 0x00007ff73ec10e83 in clone () at /lib64/libc.so.6 Thread 1 (Thread 0x7ff743986f00 (LWP 1062500)): #0 0x00005567a13b99d6 in iov_memset (iov=0x6563617073206f4e, iov_cnt=1717922848, offset=516096, fillc=0, bytes=7018105756081554803) at util/iov.c:69 #1 0x00005567a13bab73 in qemu_iovec_memset (qiov=0x7ff73ec99748, offset=516096, fillc=0, bytes=7018105756081554803) at util/iov.c:530 #2 0x00005567a12f411c in qemu_laio_process_completion (laiocb=0x7ff6512ee6c0) at block/linux-aio.c:86 #3 0x00005567a12f42ff in qemu_laio_process_completions (s=0x7ff7182e8420) at block/linux-aio.c:217 #4 0x00005567a12f480d in ioq_submit (s=0x7ff7182e8420) at block/linux-aio.c:323 #5 0x00005567a12f4a2f in laio_do_submit (fd=19, laiocb=0x7ff5f4ff9ae0, offset=472363008, type=2) at block/linux-aio.c:375 #6 0x00005567a12f4af2 in laio_co_submit (bs=0x5567a2b8c460, s=0x7ff7182e8420, fd=19, offset=472363008, qiov=0x7ff5f4ff9ca0, type=2) at block/linux-aio.c:394 #7 0x00005567a12f1803 in raw_co_prw (bs=0x5567a2b8c460, offset=472363008, bytes=20480, qiov=0x7ff5f4ff9ca0, type=2) at block/file-posix.c:1892 #8 0x00005567a12f1941 in raw_co_pwritev (bs=0x5567a2b8c460, offset=472363008, bytes=20480, qiov=0x7ff5f4ff9ca0, flags=0) at block/file-posix.c:1925 #9 0x00005567a12fe3e1 in bdrv_driver_pwritev (bs=0x5567a2b8c460, offset=472363008, bytes=20480, qiov=0x7ff5f4ff9ca0, qiov_offset=0, flags=0) at block/io.c:1183 #10 0x00005567a1300340 in bdrv_aligned_pwritev (child=0x5567a2b5b070, req=0x7ff5f4ff9db0, offset=472363008, bytes=20480, align=512, qiov=0x7ff72c0425b8, qiov_offset=0, flags=0) at block/io.c:1980 #11 0x00005567a1300b29 in bdrv_co_pwritev_part (child=0x5567a2b5b070, offset=472363008, bytes=20480, qiov=0x7ff72c0425b8, qiov_offset=0, flags=0) at block/io.c:2137 #12 0x00005567a12baba1 in qcow2_co_pwritev_task (bs=0x5567a2b92740, file_cluster_offset=472317952, offset=487305216, bytes=20480, qiov=0x7ff72c0425b8, qiov_offset=0, l2meta=0x0) at block/qcow2.c:2444 #13 0x00005567a12bacdb in qcow2_co_pwritev_task_entry (task=0x5567a2b48540) at block/qcow2.c:2475 #14 0x00005567a13167d8 in aio_task_co (opaque=0x5567a2b48540) at block/aio_task.c:45 #15 0x00005567a13cf00c in coroutine_trampoline (i0=738245600, i1=32759) at util/coroutine-ucontext.c:115 #16 0x00007ff73eb622e0 in __start_context () at /lib64/libc.so.6 #17 0x00007ff6626f1350 in () #18 0x0000000000000000 in () <------> This is also known to cause crashes with this message (assertion failed): aio_co_schedule: Co-routine was already scheduled in 'aio_co_schedule' RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=1812765 Signed-off-by: Sergio Lopez <slp@redhat.com> Message-Id: <20200603093240.40489-3-slp@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2020-06-17virtio-blk: Refactor the code that processes queued requestsSergio Lopez
Move the code that processes queued requests from virtio_blk_dma_restart_bh() to its own, non-static, function. This will allow us to call it from the virtio_blk_data_plane_start() in a future patch. Signed-off-by: Sergio Lopez <slp@redhat.com> Message-Id: <20200603093240.40489-2-slp@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2020-06-17hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointerPhilippe Mathieu-Daudé
Handlers don't need to modify the IDEDMA structure. Make it const. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200512194917.15807-1-philmd@redhat.com> Acked-by: John Snow <jsnow@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2020-06-17microvm: move virtio base to 0xfeb00000Gerd Hoffmann
Place virtio-mmio devices near the other mmio regions, next ioapic is at @ 0xfec00000. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20200529073957.8018-5-kraxel@redhat.com
2020-06-17x86: move max-ram-below-4g to pcGerd Hoffmann
Move from X86MachineClass to PCMachineClass so it disappears from microvm machine type property list. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Message-id: 20200529073957.8018-4-kraxel@redhat.com
2020-06-16Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-and-plugin-160620-2' into staging Testing and plugin updates - clear up dtc warnings - add support for --enable-tsan builds - re-enable shippable cross builds - serialise cirrus check steps - fix check-tcg plugin issues - add lockstep plugin # gpg: Signature made Tue 16 Jun 2020 14:50:09 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-plugin-160620-2: (21 commits) plugins: new lockstep plugin for debugging TCG changes tests/tcg: ensure -cpu max also used for plugin run tests/tcg: build plugin list from contents of src directory cirrus.yml: serialise make check Revert ".shippable: temporaily disable some cross builds" tests: Disable select tests under TSan, which hit TSan issue. docs: Added details on TSan to testing.rst util: Added tsan annotate for thread name. include/qemu: Added tsan.h for annotations. tests/docker: Added docker build support for TSan. thread: add tsan annotations to QemuSpin translate-all: call qemu_spin_destroy for PageDesc tcg: call qemu_spin_destroy for tb->jmp_lock qht: call qemu_spin_destroy for head buckets cputlb: destroy CPUTLB with tlb_destroy thread: add qemu_spin_destroy cpu: convert queued work to a QSIMPLEQ configure: add --enable-tsan flag + fiber annotations for coroutine-ucontext Makefile: remove old compatibility gunks Makefile: dtc: update, build the libfdt target ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-16cpu: convert queued work to a QSIMPLEQEmilio G. Cota
We convert queued work to a QSIMPLEQ, instead of open-coding it. While at it, make sure that all accesses to the list are performed while holding the list's lock. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Robert Foley <robert.foley@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-3-robert.foley@linaro.org> Message-Id: <20200612190237.30436-6-alex.bennee@linaro.org>
2020-06-16Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200616' into staging * hw: arm: Set vendor property for IMX SDHCI emulations * sd: sdhci: Implement basic vendor specific register support * hw/net/imx_fec: Convert debug fprintf() to trace events * target/arm/cpu: adjust virtual time for all KVM arm cpus * Implement configurable descriptor size in ftgmac100 * hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers * target/arm: More Neon decodetree conversion work # gpg: Signature made Tue 16 Jun 2020 10:56:10 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200616: (23 commits) hw: arm: Set vendor property for IMX SDHCI emulations sd: sdhci: Implement basic vendor specific register support hw/net/imx_fec: Convert debug fprintf() to trace events target/arm/cpu: adjust virtual time for all KVM arm cpus Implement configurable descriptor size in ftgmac100 hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers target/arm: Convert Neon VDUP (scalar) to decodetree target/arm: Convert Neon VTBL, VTBX to decodetree target/arm: Convert Neon VEXT to decodetree target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree target/arm: Add missing TCG temp free in do_2shift_env_64() target/arm: Add 'static' and 'const' annotations to VSHLL function arrays target/arm: Convert Neon 3-reg-diff polynomial VMULL target/arm: Convert Neon 3-reg-diff saturating doubling multiplies target/arm: Convert Neon 3-reg-diff long multiplies target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/fsl-imx25.c # hw/arm/fsl-imx6.c # hw/arm/fsl-imx6ul.c # hw/arm/fsl-imx7.c
2020-06-16sd: sdhci: Implement basic vendor specific register supportGuenter Roeck
The Linux kernel's IMX code now uses vendor specific commands. This results in endless warnings when booting the Linux kernel. sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_clock_gate_off: card clock still not gate off in 100us!. Implement support for the vendor specific command implemented in IMX hardware to be able to avoid this warning. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200603145258.195920-2-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-15qdev: qdev_init_nofail() is now unused, dropMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-58-armbru@redhat.com>
2020-06-15sysbus: sysbus_init_child_obj() is now unused, dropMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-52-armbru@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 16:59:50 +0000