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2019-02-01arm: Instantiate NRF51 special NVM's and NVMCSteffen Görtz
Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190201023357.22596-3-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01hw/nvram/nrf51_nvm: Add nRF51 non-volatile memoriesSteffen Görtz
The nRF51 contains three regions of non-volatile memory (NVM): - CODE (R/W): contains code - FICR (R): Factory information like code size, chip id etc. - UICR (R/W): Changeable configuration data. Lock bits, Code protection configuration, Bootloader address, Nordic SoftRadio configuration, Firmware configuration. Read and write access to the memories is managed by the Non-volatile memory controller. Memory schema: [ CPU ] -+- [ NVM, either FICR, UICR or CODE ] | | \- [ NVMC ] Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Tested-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190201023357.22596-2-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01hw/arm/armsse: Add SSE-200 modelPeter Maydell
Add a model of the SSE-200, now we have put in all the code that lets us make it different from the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-22-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add CPU_IDENTITY block to SSE-200Peter Maydell
Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-21-peter.maydell@linaro.org
2019-02-01hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register blockPeter Maydell
The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stub for CPU local control registersPeter Maydell
The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-19-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stub for cache control registersPeter Maydell
The SSE-200 gives each CPU a register bank to use to control its L1 instruction cache. Put in an unimplemented-device stub for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stubs for PPUsPeter Maydell
Add unimplemented-device stubs for the various Power Policy Unit devices that the SSE-200 has. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-17-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stubs for MHUsPeter Maydell
The SSE-200 has two Message Handling Units (MHUs), which sit behind the APB PPC0. Wire up some unimplemented-device stubs for these, since we don't yet implement a real model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-16-peter.maydell@linaro.org
2019-02-01iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurablePeter Maydell
The SYS_VERSION and SYS_CONFIG register values differ between the IoTKit and SSE-200. Make them configurable via QOM properties rather than hard-coded, and set them appropriately in the ARMSSE code that instantiates the IOTKIT_SYSINFO device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-15-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Put each CPU in its own cluster objectPeter Maydell
Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-14-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Give each CPU its own view of memoryPeter Maydell
Give each CPU its own container memory region. This is necessary for two reasons: * some devices are instantiated one per CPU and the CPU sees only its own device * since a memory region can only be put into one container, we must give each armv7m object a different MemoryRegion as its 'memory' property, or a dual-CPU configuration will assert on realize when the second armv7m object tries to put the MR into a container when it is already in the first armv7m object's container Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-13-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Support dual-CPU configurationPeter Maydell
The SSE-200 has two Cortex-M33 CPUs. These see the same view of memory, with the exception of the "private CPU region" which has per-CPU devices. Internal device interrupts for SSE-200 devices are mostly wired up to both CPUs, with the exception of a few per-CPU devices. External GPIO inputs on the SSE-200 device are provided for the second CPU's interrupts above 32, as is already the case for the first CPU. Refactor the code to support creation of multiple CPUs. For the moment we leave all CPUs with the same view of memory: this will not work in the multiple-CPU case, but we will fix this in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-12-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Make SRAM bank size configurablePeter Maydell
For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-11-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Make number of SRAM banks parameterisedPeter Maydell
The SSE-200 has four banks of SRAM, each with its own Memory Protection Controller, where the IoTKit has only one. Make the number of SRAM banks a field in ARMSSEInfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-10-peter.maydell@linaro.org
2019-02-01hw/misc/iotkit-secctl: Support 4 internal MPCsPeter Maydell
The SSE-200 has 4 banks of SRAM, each with its own internal Memory Protection Controller. The interrupt status for these extra MPCs appears in the same security controller SECMPCINTSTATUS register as the MPC for the IoTKit's single SRAM bank. Enhance the iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE variant in use does not have all 4 MPCs then the unused inputs will simply result in the SECMPCINTSTATUS bits being zero as required.) The hardcoded constant "1"s in armsse.c indicate the actual number of SRAM MPCs the IoTKit has, and will be replaced in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-9-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Rename files to hw/arm/armsse.[ch]Peter Maydell
Rename the files that used to be iotkit.[ch] to armsse.[ch] to reflect the fact they new cover multiple Arm subsystems for embedded. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-8-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Refactor into abstract base class and subclassPeter Maydell
The Arm SSE-200 Subsystem for Embedded is a revised and extended version of the older IoTKit SoC. Prepare for adding a model of it by refactoring the IoTKit code into an abstract base class which contains the functionality, driven by a class data block specific to each subclass. (This is the same approach used by the existing bcm283x SoC family implementation.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-6-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Rename IoTKit to ARMSSEPeter Maydell
The Arm IoTKit was effectively the forerunner of a series of subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200: https://developer.arm.com/products/system-design/subsystems These are generally quite similar, though later iterations have extra devices that earlier ones do not. We want to add a model of the SSE-200, which means refactoring the IoTKit code into an abstract base class and subclasses (using the same design that the bcm283x SoC and Aspeed SoC family implementations do). As a first step, rename the IoTKit struct and QOM macros to ARMSSE, which is what we're going to name the base class. We temporarily retain TYPE_IOTKIT to avoid changing the code that instantiates a TYPE_IOTKIT device here and then changing it back again when it is re-introduced as a subclass. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-5-peter.maydell@linaro.org
2019-02-01armv7m: Pass through start-powered-off CPU propertyPeter Maydell
Expose "start-powered-off" as a property of the ARMv7M container, which we just pass through to the CPU object in the same way that we do for "init-svtor" and "idau". (We want this for the SSE-200, which powers up only the first CPU at reset and leaves the second powered down.) As with the other CPU properties here, we can't just use alias properties, because the CPU QOM object is not created until armv7m realize time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-4-peter.maydell@linaro.org
2019-02-01hw/display/milkymist-tmu2: Move inlined code from header to sourcePhilippe Mathieu-Daudé
Move the complexity of milkymist_tmu2_create() into the source file. Doing so we avoid to include the X11/OpenGL headers in all LM32 devices, and we also avoid the duplicate declaration of glx_fbconfig_attr[] (it is already declared in hw/display/milkymist-tmu2.c). Since TYPE_MILKYMIST_TMU2 is now accessible, use it. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190130120005.23123-5-philmd@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-01-30Don't talk about the LGPL if the file is licensed under the GPLThomas Huth
Some files claim that the code is licensed under the GPL, but then suddenly suggest that the user should have a look at the LGPL. That's of course non-sense, replace it with the correct GPL wording instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1548255083-8190-1-git-send-email-thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30typo: apci->acpiDr. David Alan Gilbert
apci_1_compatible should be acpi_1_compatible. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190125094047.22276-1-dgilbert@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-29qom/cpu: Add cluster_index to CPUStatePeter Maydell
For TCG we want to distinguish which cluster a CPU is in, and we need to do it quickly. Cache the cluster index in the CPUState struct, by having the cluster object set cpu->cluster_index for each CPU child when it is realized. This means that board/SoC code must add all CPUs to the cluster before realizing the cluster object. Regrettably QOM provides no way to prevent adding children to a realized object and no way for the parent to be notified when a new child is added to it, so we don't have any way to enforce/assert this constraint; all we can do is document it in a comment. We can at least put in a check that the cluster contains at least one CPU, which should catch the typical cases of "realized cluster too early" or "forgot to parent the CPUs into it". The restriction on how many clusters can exist in the system is imposed by TCG code which will be added in a subsequent commit, but the check to enforce it in cluster.c fits better in this one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20190121152218.9592-3-peter.maydell@linaro.org
2019-01-29aspeed/smc: snoop SPI transfers to fake dummy cyclesCédric Le Goater
The m25p80 models dummy cycles using byte transfers. This works well when the transfers are initiated by the QEMU model of a SPI controller but when these are initiated by the OS, it breaks emulation. Snoop the SPI transfer to catch commands requiring dummy cycles and replace them with byte transfers compatible with the m25p80 model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20190124140519.13838-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29arm: Stub out NRF51 TWI magnetometer/accelerometer detectionSteffen Görtz
Recent microbit firmwares panic if the TWI magnetometer/accelerometer devices are not detected during startup. We don't implement TWI (I2C) so let's stub out these devices just to let the firmware boot. Signed-off by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190110094020.18354-2-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-28target/xtensa: add MX interrupt controllerMax Filippov
MX interrupt controller is a collection of the following devices accessible through the external registers interface: - interrupt distributor can route each external IRQ line to the corresponding external IRQ pin of selected subset of connected xtensa cores. It has per-CPU and per-IRQ enable signals and per-IRQ software assert signals; - IPI controller has 16 per-CPU IPI signals that may be routed to a combination of 3 designated external IRQ pins of connected xtensa cores; - cache coherecy register controls core L1 cache participation in the SMP cluster cache coherency protocol; - runstall register lets BSP core stall and unstall AP cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-25ide/via: Rename functions to match device nameBALATON Zoltan
The device is called via-ide and the modelled IDE controller is not specific to 82C686B but is also usable independently. Therefore, change function name prefixes accordingly to match device name. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-id: 2905ced862c8d2ad509d73152171ce2472d72605.1548160772.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25ide: Get rid of CMD646BAR structBALATON Zoltan
Now that no CMD646 specific parts are left in CMD646BAR (all remaining members are really PCI IDE specific) this struct can be deleted moving the memory regions for PCI IDE BARs to PCIIDEState where they better belong. The CMD646 PCI IDE model is adjusted accordingly. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 4b6cb2ae150dc0d21178209e4beb1e35140a7325.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25cmd646: Move PCI IDE specific functions to ide/pci.cBALATON Zoltan
The io mem ops callbacks are not specific to CMD646 but really follow the PCI IDE spec so move these from cmd646.c to pci.c to allow other PCI IDE implementations to use them. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: a2b1b2b74afdc78330b8b75605687f683a249635.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25cmd646: Remove IDEBus from CMD646BARBALATON Zoltan
The cmd646 io mem ops callbacks only need the IDEBus which is currently passed via a CMD646BAR struct. No need to wrap it up like that, we can pass it directly to these callbacks which then allows to drop the IDEBus from the CMD646BAR. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 7a31c155c9899869794499d841d30c7ef32aae47.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25cmd646: Remove unused variableBALATON Zoltan
There was a pointer to PCIIDEState in CMD646BAR which was set but not used afterwards. Get rid of this unused variable. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 1e352f091aa601fb2e19771aac46529fe278dd91.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-24virtio-net: Fix a typoPhilippe Mathieu-Daudé
Fixes: 2974e916df8 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20190121181335.3326-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-22virtio-net: Fix VirtIONet typedef redefinitionPhilippe Mathieu-Daudé
Commit 2974e916df8 introduced the VirtioNetRscChain structure which refer to a VirtIONet, declared later, thus required VirtIONet typedef to use a forward declaration. However, when compiling with Clang in -std=gnu99 mode, this triggers the following warning/error: CC hw/net/virtio-net.o In file included from qemu/hw/net/virtio-net.c:22: include/hw/virtio/virtio-net.h:189:3: error: redefinition of typedef 'VirtIONet' is a C11 feature [-Werror,-Wtypedef-redefinition] } VirtIONet; ^ include/hw/virtio/virtio-net.h:110:26: note: previous definition is here typedef struct VirtIONet VirtIONet; ^ 1 error generated. make: *** [rules.mak:69: hw/net/virtio-net.o] Error 1 Fix it by removing the duplicate typedef definition. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 modeThomas Huth
When compiling the ppc code with clang and -std=gnu99, there are a couple of warnings/errors like this one: CC ppc64-softmmu/hw/intc/xics.o In file included from hw/intc/xics.c:35: include/hw/ppc/xics.h:43:25: error: redefinition of typedef 'ICPState' is a C11 feature [-Werror,-Wtypedef-redefinition] typedef struct ICPState ICPState; ^ target/ppc/cpu.h:1181:25: note: previous definition is here typedef struct ICPState ICPState; ^ Work around the problems by including the proper headers in spapr.h and by using struct forward declarations in cpu.h. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22ppc: Move spapr-related prototypes from xics.h into a seperate header fileThomas Huth
When compiling with Clang in -std=gnu99 mode, there is a warning/error: CC ppc64-softmmu/hw/intc/xics_spapr.o In file included from /home/thuth/devel/qemu/hw/intc/xics_spapr.c:34: /home/thuth/devel/qemu/include/hw/ppc/xics.h:203:34: error: redefinition of typedef 'sPAPRMachineState' is a C11 feature [-Werror,-Wtypedef-redefinition] typedef struct sPAPRMachineState sPAPRMachineState; ^ /home/thuth/devel/qemu/include/hw/ppc/spapr_irq.h:25:34: note: previous definition is here typedef struct sPAPRMachineState sPAPRMachineState; ^ We have to remove the duplicated typedef here and include "spapr.h" instead. But "spapr.h" should not be included for the pnv machine files. So move the spapr-related prototypes into a new file called "xics_spapr.h" instead. Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22ui/console: Remove MouseTransformInfo from qemu/typedefs.hPhilippe Mathieu-Daudé
Header files requiring MouseTransformInfo already include "ui/console.h". To clean "qemu/typedefs.h", move the declaration to "ui/console.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22hw/i386: Remove PCMachineClass from "qemu/typedefs.h"Philippe Mathieu-Daudé
Files requiring PCMachineClass already include "hw/i386/pc.h". To clean "qemu/typedefs.h", move the declaration to "hw/i386/pc.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22hw/char/serial: Remove SerialState from "qemu/typedefs.h"Philippe Mathieu-Daudé
Files requiring SerialState already include "hw/char/serial.h". To clean "qemu/typedefs.h", move the declaration to "hw/char/serial.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22hw/i2c/smbus: Remove SMBusDevice from "qemu/typedefs.h"Philippe Mathieu-Daudé
Files requiring SMBusDevice already include "hw/i2c/smbus.h". To clean "qemu/typedefs.h", move the forward declaration to "hw/i2c/smbus.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22hw/ide/ahci: Remove AllwinnerAHCIState from "qemu/typedefs.h"Philippe Mathieu-Daudé
Files requiring AllwinnerAHCIState already include "hw/ide/ahci.h". To clean "qemu/typedefs.h", move the declaration to "hw/ide/ahci.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22hw/pcmcia: Remove PCMCIACardState from "qemu/typedefs.h"Philippe Mathieu-Daudé
There is only one header file requiring this typedef (hw/arm/pxa.h), let it include "hw/pcmcia.h" directly to simplify "qemu/typedefs.h". To clean "qemu/typedefs.h", move the declaration to "hw/pcmcia.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [thuth: slightly tweaked commit message] Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-22hw/input/ps2: Remove PS2State from "qemu/typedefs.h"Philippe Mathieu-Daudé
PS2State is only used in "hw/input/ps2.h", there is no need to expose it via "qemu/typedefs.h". To clean "qemu/typedefs.h", move the forward declaration to "hw/input/ps2.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-21Merge remote-tracking branch ↵Peter Maydell
'remotes/amarkovic/tags/mips-queue-january-17-2019-v2' into staging MIPS queue for January 17, 2019 - v2 # gpg: Signature made Fri 18 Jan 2019 15:55:35 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-january-17-2019-v2: target/mips: Introduce 32 R5900 multimedia registers target/mips: Rename 'rn' to 'register_name' target/mips: Add CP0 register MemoryMapID target/mips: Amend preprocessor constants for CP0 registers target/mips: Update ITU to handle bus errors target/mips: Update ITU to utilize SAARI and SAAR CP0 registers target/mips: Add field and R/W access to ITU control register ICR0 target/mips: Provide R/W access to SAARI and SAAR CP0 registers target/mips: Add fields for SAARI and SAAR CP0 registers target/mips: Use preprocessor constants for 32 major CP0 registers target/mips: Add preprocessor constants for 32 major CP0 registers target/mips: Move comment containing summary of CP0 registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 nodeEric Auger
Let's report IO-coherent access is supported for translation table walks, descriptor fetches and queues by setting the COHACC override flag. Without that, we observe wrong command opcodes. The DT description also advertises the dma coherency. Fixes a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table") Signed-off-by: Eric Auger <eric.auger@redhat.com> Reported-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20190107101041.765-1-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-18target/mips: Update ITU to utilize SAARI and SAAR CP0 registersYongbok Kim
Update ITU to utilize SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-18target/mips: Add field and R/W access to ITU control register ICR0Yongbok Kim
Add field and R/W access to ITU control register ICR0. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-17hw/acpi: Use QEMU_NONSTRING for non NUL-terminated arraysPhilippe Mathieu-Daudé
GCC 8 added a -Wstringop-truncation warning: The -Wstringop-truncation warning added in GCC 8.0 via r254630 for bug 81117 is specifically intended to highlight likely unintended uses of the strncpy function that truncate the terminating NUL character from the source string. This new warning leads to compilation failures: CC hw/acpi/core.o In function 'acpi_table_install', inlined from 'acpi_table_add' at qemu/hw/acpi/core.c:296:5: qemu/hw/acpi/core.c:184:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation] strncpy(ext_hdr->sig, hdrs->sig, sizeof ext_hdr->sig); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ make: *** [qemu/rules.mak:69: hw/acpi/core.o] Error 1 Use the QEMU_NONSTRING attribute, since ACPI tables don't require the strings to be NUL-terminated. Suggested-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-01-17acpi: build TPM Physical Presence interfaceStefan Berger
The TPM Physical Presence interface consists of an ACPI part, a shared memory part, and code in the firmware. Users can send messages to the firmware by writing a code into the shared memory through invoking the ACPI code. When a reboot happens, the firmware looks for the code and acts on it by sending sequences of commands to the TPM. This patch adds the ACPI code. It is similar to the one in EDK2 but doesn't assume that SMIs are necessary to use. It uses a similar datastructure for the shared memory as EDK2 does so that EDK2 and SeaBIOS could both make use of it. I extended the shared memory data structure with an array of 256 bytes, one for each code that could be implemented. The array contains flags describing the individual codes. This decouples the ACPI implementation from the firmware implementation. The underlying TCG specification is accessible from the following page. https://trustedcomputinggroup.org/tcg-physical-presence-interface-specification/ This patch implements version 1.30. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> [ Marc-André - ACPI code improvements and windows fixes ] Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-01-17acpi: expose TPM/PPI configuration parameters to firmware via fw_cfgStefan Berger
To avoid having to hard code the base address of the PPI virtual memory device we introduce a fw_cfg file etc/tpm/config that holds the base address of the PPI device, the version of the PPI interface and the version of the attached TPM. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> [ Marc-André: renamed to etc/tpm/config, made it static, document it ] Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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