slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Collapse)	Author
2019-05-13	Clean up ill-advised or unusual header guards	Markus Armbruster
	Leading underscores are ill-advised because such identifiers are reserved. Trailing underscores are merely ugly. Strip both. Our header guards commonly end in _H. Normalize the exceptions. Done with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-7-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [Changes to slirp/ dropped, as we're about to spin it off]
2019-01-28	target/xtensa: add MX interrupt controller	Max Filippov
	MX interrupt controller is a collection of the following devices accessible through the external registers interface: - interrupt distributor can route each external IRQ line to the corresponding external IRQ pin of selected subset of connected xtensa cores. It has per-CPU and per-IRQ enable signals and per-IRQ software assert signals; - IPI controller has 16 per-CPU IPI signals that may be routed to a combination of 3 designated external IRQ pins of connected xtensa cores; - cache coherecy register controls core L1 cache participation in the SMP cluster cache coherency protocol; - runstall register lets BSP core stall and unstall AP cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>