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2019-02-21hw/timer/pl031: Allow use as an embedded-struct devicePeter Maydell
Create a new include file for the pl031's device struct, type macros, etc, so that it can be instantiated using the "embedded struct" coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-07hw/timer/nrf51_timer: Add nRF51 Timer peripheralSteffen Görtz
This patch adds the model for the nRF51 timer peripheral. Currently, only the TIMER mode is implemented. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-9-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-11qom: make interface types abstractMarc-André Lureau
Interfaces don't have instance, let's make the interface type really abstract to avoid confusion. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20181204142023.15982-3-marcandre.lureau@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-09-25aspeed/timer: fix compile breakage with clang 3.4.2Cédric Le Goater
In file included from /home/thuth/devel/qemu/hw/timer/aspeed_timer.c:16: /home/thuth/devel/qemu/include/hw/misc/aspeed_scu.h:37:3: error: redefinition of typedef 'AspeedSCUState' is a C11 feature [-Werror,-Wtypedef-redefinition] } AspeedSCUState; ^ /home/thuth/devel/qemu/include/hw/timer/aspeed_timer.h:27:31: note: previous definition is here typedef struct AspeedSCUState AspeedSCUState; Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180921161939.822-2-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-24hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer modulePeter Maydell
The Arm Cortex-M System Design Kit includes a "dual-input timer module" which combines two programmable down-counters. Implement a model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-4-peter.maydell@linaro.org
2018-06-26aspeed/timer: use the APB frequency from the SCUCédric Le Goater
The timer controller can be driven by either an external 1MHz clock or by the APB clock. Today, the model makes the assumption that the APB frequency is always set to 24MHz but this is incorrect. The AST2400 SoC on the palmetto machines uses a 48MHz input clock source and the APB can be set to 48MHz. The consequence is a general system slowdown. The QEMU machines using the AST2500 SoC do not seem impacted today because the APB frequency is still set to 24MHz. We fix the timer frequency for all SoCs by linking the Timer model to the SCU model. The APB frequency driving the timers is now the one configured for the SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180622075700.5923-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02xlnx-zynqmp-rtc: Add basic time supportAlistair Francis
Allow the guest to determine the time set from the QEMU command line. This includes adding a trace event to debug the new time. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02xlnx-zynqmp-rtc: Initial commitAlistair Francis
Initial commit of the ZynqMP RTC device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09i.MX: Add i.MX7 GPT variantAndrey Smirnov
Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-12-18hw/timer/mc146818: rename rtc_init() -> mc146818_rtc_init()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-12-18hw/timer/i8254: rename pit_init() -> i8254_pit_init()Philippe Mathieu-Daudé
and remove the old i386/pc dependency Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-09-21msf2: Add Smartfusion2 System timerSubbaraya Sundeep
Modelled System Timer in Microsemi's Smartfusion2 Soc. Timer has two 32bit down counters and two interrupts. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17hw/char/cmsdk-apb-timer: Implement CMSDK APB timer devicePeter Maydell
Implement a model of the simple timer device found in the CMSDK. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500029487-14822-5-git-send-email-peter.maydell@linaro.org
2017-06-06qtest: add rtc periodic timer testXiao Guangrong
It tests the accuracy of rtc periodic timer which is recently improved & fixed by commit 7ffcb539a3 ("mc146818rtc: precisely count the clock for periodic timer", 2017-05-19). Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20170527025301.23499-1-xiaoguangrong@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-28armv7m: Split systick out from NVICPeter Maydell
The SysTick timer isn't really part of the NVIC proper; we just modelled it that way back when we couldn't easily have devices that only occupied a small chunk of a memory region. Split it out into its own device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-21hw/mips_gictimer: provide API for retrieving frequencyPaul Burton
Provide a new function mips_gictimer_get_freq() which returns the frequency at which a GIC timer will count. This will be useful for boards which perform setup based upon this frequency. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-01-18target-sparc: implement sun4v RTCArtyom Tarasenko
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2016-10-24arm_mptimer: Convert to use ptimerDmitry Osipenko
Current ARM MPTimer implementation uses QEMUTimer for the actual timer, this implementation isn't complete and mostly tries to duplicate of what generic ptimer is already doing fine. Conversion to ptimer brings the following benefits and fixes: - Simple timer pausing implementation - Fixes counter value preservation after stopping the timer - Properly handles prescaler != 0 / counter = 0 / load = 0 cases - Code simplification and reduction Bump VMSD to version 3, since VMState is changed and is not compatible with the previous implementation. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 37f378c33bb5a28d5cd71167a6bd5bff5e59cbc3.1475421224.git.digetx@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-12Clean up decorations and whitespace around header guardsMarkus Armbruster
Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12Clean up ill-advised or unusual header guardsMarkus Armbruster
Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12Clean up header guards that don't match their file nameMarkus Armbruster
Header guard symbols should match their file name to make guard collisions less likely. Offenders found with scripts/clean-header-guards.pl -vn. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into stagingPeter Maydell
MIPS patches 2016-07-12 Changes: * support 10-bit ASIDs * MIPS64R6-generic renamed to I6400 * initial GIC support * implement RESET_BASE register in CM GCR # gpg: Signature made Tue 12 Jul 2016 11:49:50 BST # gpg: using RSA key 0x52118E3C0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20160712: target-mips: enable 10-bit ASIDs in I6400 CPU target-mips: support CP0.Config4.AE bit target-mips: change ASID type to hold more than 8 bits target-mips: add ASID mask field and replace magic values target-mips: replace MIPS64R6-generic with the real I6400 CPU model hw/mips_cmgcr: implement RESET_BASE register in CM GCR hw/mips_cpc: make VP correctly start from the reset vector target-mips: add exception base to MIPS CPU hw/mips/cps: create GIC block inside CPS hw/mips: implement Global Interrupt Controller hw/mips: implement GIC Interval Timer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-12hw/mips: implement GIC Interval TimerYongbok Kim
The interval timer is similar to the CP0 Count/Compare timer within each processor. The difference is the GIC_SH_COUNTER register is global to the system so that all processors have the same time reference. To ease implementation, all VPs are having its own QEMU timer but sharing global settings and registers such as GIC_SH_CONFIG.COUTNSTOP and GIC_SH_COUNTER. MIPS GIC Interval Timer does support upto 64 bits of Count register but in this implementation it is limited to 32 bits only. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-07-07i.MX: split the GPT timer implementation into per SOC definitionsJean-Christophe Dubois
In various Freescale SOCs, the GPT timers can be configured to select its input clock. Depending on the SOC the set of available input clocks may vary. The actual single GPT definition was no good enough and because of it booting the sabrelite board with a i.MX6DL device tree would fail because of an incorrect input clock definition for the i.MX6DL SOC. This patch fixes the i.MX6DL boot failure by adding the ability to define a different set of input clocks depending on the considered SOC. A different class has been defined for i.MX25, i.MX31 and i.MX6 each with its specific set of input clocks. The patch has been tested by booting KZM, i.MX25 PDK, i.MX6Q sabrelite and i.MX6DL sabrelite. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 1467325619-8374-1-git-send-email-jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed spacing round '/' operator] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-30pcspk: fix KVMPaolo Bonzini
The link property that was added to the pcspk device has the wrong type: it is only correct for TCG and for KVM's userspace or split irqchip options. The default KVM option (fully in-kernel irqchip) breaks because it uses a PIT whose type is a sibling of TYPE_I8254. Fixes: 873b4d3f0571a1e415cf089a67a230ea8a12d059 Tested-by: Peter Lieven <pl@kamp.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1467298657-6588-1-git-send-email-pbonzini@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17hw/timer: Add value matching support to aspeed_timerAndrew Jeffery
Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the palmetto-bmc machine. Two match registers are provided for each timer. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1465974248-20434-1-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-22Use scripts/clean-includes to drop redundant qemu/typedefs.hMarkus Armbruster
Re-run scripts/clean-includes to apply the previous commit's corrections and updates. Besides redundant qemu/typedefs.h, this only finds a redundant config-host.h include in ui/egl-helpers.c. No idea how that escaped the previous runs. Some manual whitespace trimming around dropped includes squashed in. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-16hw/timer: Add ASPEED timer device modelAndrew Jeffery
Implement basic ASPEED timer functionality for the AST2400 SoC[1]: Up to 8 timers can independently be configured, enabled, reset and disabled. Some hardware features are not implemented, namely clock value matching and pulse generation, but the implementation is enough to boot the Linux kernel configured with aspeed_defconfig. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-2-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-09pc: acpi: move HPET from DSDT to SSDTIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-12-17i.MX: Split the CCM class into an abstract base class and a concrete classJean-Christophe Dubois
The IMX_CCM class is now the base abstract class that is used by EPIT and GPT timer implementation. IMX31_CCM class is the concrete class implementing CCM for i.MX31 SOC. For now the i.MX25 continues to use the i.MX31 CCM implementation. An i.MX25 specific CCM will be introduced in a later patch. We also rework initialization to stop using deprecated sysbus device init. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fd3c7f87b50f5ebc99ec91f01413db35017f116d.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-25hpet: remove muldiv64()Laurent Vivier
hpet defines a clock period in femtoseconds but then converts it to nanoseconds to use the internal timers. We can define the period in nanoseconds and use it directly, this allows to remove muldiv64(). We only need to convert the period to femtoseconds to put it in internal hpet capability register. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2015-08-13i.MX: Split GPT emulator in a header file and a source fileJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e32fba56b9dae3cc7c83726550514b2d0c890ae0.1437080501.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-13i.MX: Split EPIT emulator in a header file and a source fileJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 948927cab0c85da9a753c5f6d5501323d5604c8e.1437080501.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-27Fix Cortex-A9 global timerJohannes Schlatow
The auto increment bit of the timer control register was wrongly defined. See Cortex-A9 MPcore Technical Reference Manual, Section 4.4.2. Signed-off-by: Johannes Schlatow <schlatow@ida.ing.tu-bs.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-11stm32f2xx_timer: Add the stm32f2xx TimerAlistair Francis
This patch adds the stm32f2xx timers: TIM2, TIM3, TIM4 and TIM5 to QEMU. Signed-off-by: Alistair Francis <alistair@alistair23.me> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 155091a323390f8da3cca496e4c611c493e62a77.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-10m48t59: introduce new base-year qdev propertyMark Cave-Ayland
Currently the m48t59 device uses the hardware model in order to determine whether the year value is offset from the hardware value. As this will soon be required by the x59 model, create a qdev base-year property to represent the base year and update the callers appropriately. Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> CC: Andreas Färber <afaerber@suse.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2015-03-10m48t59: let init functions return a Nvram objectHervé Poussineau
Remove left-overs from header file. Move some functions only used by PReP to hw/ppc/prep.c Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> CC: Andreas Färber <afaerber@suse.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2015-03-10m48t59: add a Nvram interfaceHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> CC: Andreas Färber <afaerber@suse.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-04-17allwinner-a10-pit: implement prescaler and source selectionBeniamino Galvani
This implements the prescaler and source fields of the timer control register. The source for each timer can be selected among 4 clock inputs whose frequencies are set through model properties. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-6-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17allwinner-a10-pit: avoid generation of spurious interruptsBeniamino Galvani
The model was generating interrupts for all enabled timers after the expiration of one of them. Avoid this by passing explicitly the timer index to the callback function. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-4-git-send-email-b.galvani@gmail.com [PMM: avoid duplicate typedef of AwA10PITState] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/timer: add allwinner a10 timerliguang
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-3-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add timer supportAntony Pavlov
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-4-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-13Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori
acpi.pci,pc,memory core fixes Most notably this includes changes to exec to support full 64 bit addresses. This also flushes out patches that got queued during 1.7 freeze. There are new tests, and a bunch of bug fixes all over the place. There are also some changes mostly useful for downstreams. I'm also listing myself as pc co-maintainer. I'm doing this reluctantly, but this seems to be necessary to make sure patches are not lost or delayed too much, and posting the MAINTAINERS patch did not seem to make anyone else volunteer. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 11 Dec 2013 10:21:51 AM PST using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin (14) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: (28 commits) pc: use macro for HPET type hpet: fix build with CONFIG_HPET off acpi unit-test: adjust the test data structure for better handling acpi unit-test: load and check facs table exec: separate sections and nodes per address space memory.c: bugfix - ref counting mismatch in memory_region_find hpet: enable to entitle more irq pins for hpet hpet: inverse polarity when pin above ISA_NUM_IRQS pci: fix pci bridge fw path ACPI DSDT: Make control method `IQCR` serialized acpi: strip compiler info in built-in DSDT acpi unit-test: verify signature and checksum smbios: Set system manufacturer, product & version by default exec: reduce L2_PAGE_SIZE exec: make address spaces 64-bit wide exec: memory radix tree page level compression exec: pass hw address to phys_page_find exec: extend skip field to 6 bit, page entry to 32 bit exec: replace leaf with skip split definitions for exec.c and translate-all.c radix trees ... Message-id: cover.1386786228.git.mst@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-11hpet: fix build with CONFIG_HPET offMichael S. Tsirkin
make hpet_find inline so we don't need to build hpet.c to check if hpet is enabled. Fixes link error with CONFIG_HPET off. Cc: qemu-stable@nongnu.org Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10hw/timer: Introduce ARM A9 Global Timer.Peter Crosthwaite
The ARM A9 MPCore has a timer that is global to all cores in the cluster. The timer is shared but each core has a private independent comparator and interrupt. Based on version contributed by Francois LEGAL. Signed-off-by: François LEGAL <devel@thom.fr.eu.org> Message-id: 4918e89476b8da916be2964ec41578b50d569a37.1385969450.git.peter.crosthwaite@xilinx.com [PC changes: * New commit message * Re-implemented as single timer model * Fixed backwards counting issue in polled mode * completed VMSD fields * macroified magic numbers (and headerified reg definitions) * split of as device-model-only patch * use bitops for 64 bit register access * Fixed auto increment mode to check condition properly * general cleanup (names/style etc). ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [PMM: * minor typo fixes * added missing return after error_setg() * dropped setting dc->no_user = 1 ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-05a9mpcore: Embed ARMMPTimerStateAndreas Färber
Prepares for QOM realize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-10-14hpet: add API to find itMichael S. Tsirkin
Add API to find HPET using QOM. Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-07-29m48t59: QOM cast cleanup for M48t59SysBusStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07i8254: Convert PITCommonState to QOM realizefnAndreas Färber
Instead of having the parent provide PITCommonClass::init, let the children override DeviceClass::realize themselves. This pushes the responsibility for saving and calling the parent's realizefn to the children. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07kvm/i8254: QOM'ify some moreAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Prepares for PIT realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-04 07:34:58 +0000