Age | Commit message (Expand) | Author |
2020-11-03 | hw/riscv: microchip_pfsoc: Hook the I2C1 controller | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Correct DDR memory map | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect the SYSREG module | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect the IOSCB module | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect DDR memory controller modules | Bin Meng |
2020-10-22 | hw/riscv: Load the kernel after the firmware | Alistair Francis |
2020-10-22 | hw/riscv: Add a riscv_is_32_bit() function | Alistair Francis |
2020-10-22 | hw/riscv: Return the end address of the loaded firmware | Alistair Francis |
2020-10-22 | hw/riscv: sifive_u: Allow specifying the CPU | Alistair Francis |
2020-09-18 | Use OBJECT_DECLARE_SIMPLE_TYPE when possible | Eduardo Habkost |
2020-09-18 | sifive_u: Rename memmap enum constants | Eduardo Habkost |
2020-09-18 | sifive_e: Rename memmap enum constants | Eduardo Habkost |
2020-09-13 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200... | Peter Maydell |
2020-09-09 | hw/riscv: Move sifive_test model to hw/misc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_uart model to hw/char | Bin Meng |
2020-09-09 | hw/riscv: Move riscv_htif model to hw/char | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_plic model to hw/intc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_clint model to hw/intc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_gpio model to hw/gpio | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_u_otp model to hw/misc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_u_prci model to hw/misc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_e_prci model to hw/misc | Bin Meng |
2020-09-09 | hw/riscv: sifive_u: Connect a DMA controller | Bin Meng |
2020-09-09 | hw/riscv: clint: Avoid using hard-coded timebase frequency | Bin Meng |
2020-09-09 | hw/riscv: microchip_pfsoc: Hook GPIO controllers | Bin Meng |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs | Bin Meng |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect a DMA controller | Bin Meng |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card | Bin Meng |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs | Bin Meng |
2020-09-09 | hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board | Bin Meng |
2020-09-09 | hw/riscv: hart: Add a new 'resetvec' property | Bin Meng |
2020-09-09 | Use DECLARE_*CHECKER* macros | Eduardo Habkost |
2020-09-09 | Move QOM typedefs and add missing includes | Eduardo Habkost |
2020-08-27 | opentitan: Rename memmap enum constants | Eduardo Habkost |
2020-08-25 | hw/riscv: virt: Allow creating multiple NUMA sockets | Anup Patel |
2020-08-25 | hw/riscv: spike: Allow creating multiple NUMA sockets | Anup Patel |
2020-08-25 | hw/riscv: Add helpers for RISC-V multi-socket NUMA machines | Anup Patel |
2020-08-25 | hw/riscv: Allow creating multiple instances of PLIC | Anup Patel |
2020-08-25 | hw/riscv: Allow creating multiple instances of CLINT | Anup Patel |
2020-08-21 | hw/riscv: sifive_u: Add a dummy L2 cache controller device | Bin Meng |
2020-07-13 | riscv: Add opensbi firmware dynamic support | Atish Patra |
2020-07-13 | RISC-V: Copy the fdt in dram instead of ROM | Atish Patra |
2020-07-13 | riscv: Unify Qemu's reset vector code path | Atish Patra |
2020-06-19 | hw/riscv: sifive_u: Add a dummy DDR memory controller device | Bin Meng |
2020-06-19 | hw/riscv: sifive_u: Support different boot source per MSEL pin state | Bin Meng |
2020-06-19 | hw/riscv: sifive_u: Add a new property msel for MSEL pin state | Bin Meng |
2020-06-19 | hw/riscv: sifive_u: Hook a GPIO controller | Bin Meng |
2020-06-19 | hw/riscv: sifive_gpio: Add a new 'ngpio' property | Bin Meng |
2020-06-19 | hw/riscv: sifive_gpio: Clean up the codes | Bin Meng |