aboutsummaryrefslogtreecommitdiff
path: root/include/hw/riscv
AgeCommit message (Expand)Author
2019-08-16Clean up inclusion of sysemu/sysemu.hMarkus Armbruster
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster
2019-08-16include: Make headers more self-containedMarkus Armbruster
2019-07-18hw/riscv: Load OpenSBI as the default firmwareAlistair Francis
2019-06-27hw/riscv: Add support for loading a firmwareAlistair Francis
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis
2019-06-23RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt
2019-06-23sifive_prci: Read and write PRCI registersNathaniel Graff
2019-05-24target/riscv: Add a base 32 and 64 bit CPUAlistair Francis
2019-05-24SiFive RISC-V GPIO DeviceFabien Chouteau
2019-05-13Clean up decorations and whitespace around header guardsMarkus Armbruster
2019-04-04riscv: plic: Fix incorrect irq calculationAlistair Francis
2018-12-20sifive_uart: Implement interrupt pending registerNathaniel Graff
2018-12-20sifive_u: Add clock DT node for GEM ethernetAnup Patel
2018-12-20hw/riscv/virt: Connect the gpex PCIeAlistair Francis
2018-12-20hw/riscv/virt: Increase the number of interruptsAlistair Francis
2018-09-04RISC-V: Use atomic_cmpxchg to update PLIC bitmapsMichael Clark
2018-07-05hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis
2018-07-05hw/riscv/sifive_e: Create a SiFive E SoC objectAlistair Francis
2018-07-05hw/riscv/sifive_u: Create a SiFive U SoC objectAlistair Francis
2018-05-06RISC-V: Make virt header comment title consistentMichael Clark
2018-05-06RISC-V: Make some header guards more specificMichael Clark
2018-05-06RISC-V: Remove unused class definitionsMichael Clark
2018-05-06RISC-V: Use ROM base address and size from memmapMichael Clark
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark
2018-03-07SiFive Freedom E Series RISC-V MachineMichael Clark
2018-03-07SiFive RISC-V PRCI BlockMichael Clark
2018-03-07SiFive RISC-V UART DeviceMichael Clark
2018-03-07RISC-V VirtIO MachineMichael Clark
2018-03-07SiFive RISC-V Test FinisherMichael Clark
2018-03-07RISC-V Spike MachinesMichael Clark
2018-03-07SiFive RISC-V PLIC BlockMichael Clark
2018-03-07SiFive RISC-V CLINT BlockMichael Clark
2018-03-07RISC-V HART ArrayMichael Clark
2018-03-07RISC-V HTIF ConsoleMichael Clark