| Age | Commit message (Expand) | Author |
|---|
| 2022-04-29 | hw/riscv: virt: Create a platform bus | Alistair Francis |
| 2022-04-29 | hw/riscv: virt: Add a machine done notifier | Alistair Francis |
| 2022-03-03 | hw/riscv: virt: Increase maximum number of allowed CPUs | Anup Patel |
| 2022-03-03 | hw/riscv: virt: Add optional AIA IMSIC support to virt machine | Anup Patel |
| 2022-03-03 | hw/riscv: virt: Add optional AIA APLIC support to virt machine | Anup Patel |
| 2022-01-08 | hw/riscv: virt: Allow support for 32 cores | Alistair Francis |
| 2021-10-28 | hw/riscv: virt: Don't use a macro for the PLIC configuration | Alistair Francis |
| 2021-09-21 | hw/riscv: virt: Add optional ACLINT support to virt machine | Anup Patel |
| 2021-03-22 | hw/riscv: Add fw_cfg support to virt | Asherah Connor |
| 2021-03-10 | hw/riscv: migrate fdt field to generic MachineState | Alex Bennée |
| 2020-12-17 | riscv: virt: Remove target macro conditionals | Alistair Francis |
| 2020-09-09 | Use DECLARE_*CHECKER* macros | Eduardo Habkost |
| 2020-09-09 | Move QOM typedefs and add missing includes | Eduardo Habkost |
| 2020-08-25 | hw/riscv: virt: Allow creating multiple NUMA sockets | Anup Patel |
| 2020-02-10 | riscv: virt: Use Goldfish RTC device | Anup Patel |
| 2019-10-28 | riscv/virt: Add the PFlash CFI01 device | Alistair Francis |
| 2019-10-28 | riscv/virt: Manually define the machine | Alistair Francis |
| 2019-10-28 | riscv: hw: Drop "clock-frequency" property of cpu nodes | Bin Meng |
| 2019-08-16 | include: Make headers more self-contained | Markus Armbruster |
| 2019-05-24 | target/riscv: Add a base 32 and 64 bit CPU | Alistair Francis |
| 2019-04-04 | riscv: plic: Fix incorrect irq calculation | Alistair Francis |
| 2018-12-20 | hw/riscv/virt: Connect the gpex PCIe | Alistair Francis |
| 2018-12-20 | hw/riscv/virt: Increase the number of interrupts | Alistair Francis |
| 2018-05-06 | RISC-V: Make virt header comment title consistent | Michael Clark |
| 2018-05-06 | RISC-V: Make some header guards more specific | Michael Clark |
| 2018-05-06 | RISC-V: Remove unused class definitions | Michael Clark |
| 2018-05-06 | RISC-V: Use ROM base address and size from memmap | Michael Clark |
| 2018-05-06 | RISC-V: Replace hardcoded constants with enum values | Michael Clark |
| 2018-03-07 | RISC-V VirtIO Machine | Michael Clark |
