slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2020-08-21	hw/riscv: sifive_u: Add a dummy L2 cache controller device	Bin Meng
2020-06-19	hw/riscv: sifive_u: Add a dummy DDR memory controller device	Bin Meng
2020-06-19	hw/riscv: sifive_u: Support different boot source per MSEL pin state	Bin Meng
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng
2020-06-15	riscv: Fix type of SiFive[EU]SocState, member parent_obj	Markus Armbruster
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u machine	Bin Meng
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u SoC	Alistair Francis
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng
2019-09-17	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	Bin Meng
2019-08-16	include: Make headers more self-contained	Markus Armbruster
2019-04-04	riscv: plic: Fix incorrect irq calculation	Alistair Francis
2018-12-20	sifive_u: Add clock DT node for GEM ethernet	Anup Patel
2018-07-05	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device	Alistair Francis
2018-07-05	hw/riscv/sifive_u: Create a SiFive U SoC object	Alistair Francis
2018-05-06	RISC-V: Remove unused class definitions	Michael Clark
2018-05-06	RISC-V: Replace hardcoded constants with enum values	Michael Clark
2018-03-07	SiFive Freedom U Series RISC-V Machine	Michael Clark