aboutsummaryrefslogtreecommitdiff
path: root/include/hw/ppc
AgeCommit message (Collapse)Author
2024-03-13spapr: nested: Introduce cap-nested-papr for Nested PAPR APIHarsh Prateek Bora
Introduce a SPAPR capability cap-nested-papr which enables nested PAPR API for nested guests. This new API is to enable support for KVM on PowerVM and the support in Linux kernel has already merged upstream. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Use correct source for parttbl info for nested PAPR API.Harsh Prateek Bora
For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store partition table info, use the same in spapr_get_pate_nested() via helper. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.Harsh Prateek Bora
Introduce the nested PAPR hcalls: - H_GUEST_GET_STATE which is used to get state of a nested guest or a guest VCPU. The value field for each element in the request is destination to be updated to reflect current state on success. - H_GUEST_SET_STATE which is used to modify the state of a guest or a guest VCPU. On success, guest (or its VCPU) state shall be updated as per the value field for the requested element(s). Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Initialize the GSB elements lookup table.Harsh Prateek Bora
Nested PAPR API provides a standard Guest State Buffer (GSB) format with unique IDs for each guest state element for which get/set state is supported by the API. Some of the elements are read-only and/or guest-wide. Introducing additional required GSB elements and helper routines for state exchange of each of the nested guest state elements for which get/set state should be supported by the API. [amachhiw: set the PCR whenever logical PVR is set] Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Signed-off-by: Amit Machhiwal <amachhiw@linux.vnet.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Extend nested_ppc_state for nested PAPR APIHarsh Prateek Bora
Currently, nested_ppc_state stores a certain set of registers and works with nested_[load|save]_state() for state transfer as reqd for nested-hv API. Extending these with additional registers state as reqd for nested PAPR API. Acked-by: Nicholas Piggin <npiggin@gmail.com> Suggested-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall.Harsh Prateek Bora
Introduce the nested PAPR hcall H_GUEST_CREATE_VCPU which is used to create and initialize the specified VCPU resource for the previously created guest. Each guest can have multiple VCPUs upto max 2048. All VCPUs for a guest gets deallocated on guest delete. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls.Harsh Prateek Bora
Introduce the nested PAPR hcalls: - H_GUEST_CREATE which is used to create and allocate resources for nested guest being created. - H_GUEST_DELETE which is used to delete and deallocate resources for the nested guest being deleted. It also supports deleting all nested guests at once using a deleteAll flag. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls.Harsh Prateek Bora
Introduce the nested PAPR hcalls: - H_GUEST_GET_CAPABILITIES which is used to query the capabilities of the API and the L2 guests it provides. - H_GUEST_SET_CAPABILITIES which is used to set the Guest API capabilities that the Host Partition supports and may use. [amachhiw: support for p9 compat mode and return register bug fixes] Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Amit Machhiwal <amachhiw@linux.vnet.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: keep nested-hv related code restricted to its API.Harsh Prateek Bora
spapr_exit_nested and spapr_get_pate_nested_hv contains code which is specific to nested-hv API. Isolating code flows based on API helps extending it to be used with different API as well. Suggested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Introduce SpaprMachineStateNested to store related info.Harsh Prateek Bora
Currently, nested_ptcr is being used by existing nested-hv API to store nested guest related info. This need to be organised to extend support for the nested PAPR API which would need to store additional info related to nested guests in next series of patches. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: move nested part of spapr_get_pate into spapr_nested.cHarsh Prateek Bora
Most of the nested code has already been moved to spapr_nested.c This logic inside spapr_get_pate is related to nested guests and better suited for spapr_nested.c, hence moving there. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: register nested-hv api hcalls only for cap-nested-hvHarsh Prateek Bora
Since cap-nested-hv is an optional capability, it makes sense to register api specfic hcalls only when respective capability is enabled. This requires to introduce a new API to unregister hypercalls to maintain sanity across guest reboot since caps are re-applied across reboots and re-registeration of hypercalls would hit assert otherwise. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13ppc/pnv: Improve pervasive topology calculation for big-coreCaleb Schlossin
Big (SMT8) cores have a complicated function to map the core, thread ID to pervasive topology (PIR). Fix this for power8, power9, and power10. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Implement the ChipTOD to Core transferNicholas Piggin
One of the functions of the ChipTOD is to transfer TOD to the Core (aka PC - Pervasive Core) timebase facility. The ChipTOD can be programmed with a target address to send the TOD value to. The hardware implementation seems to perform this by sending the TOD value to a SCOM address. This implementation grabs the core directly and manipulates the timebase facility state in the core. This is a hack, but it works enough for now. A better implementation would implement the transfer to the PnvCore xscom register and drive the timebase state machine from there. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machinesNicholas Piggin
Wire the ChipTOD model to powernv9 and powernv10 machines. Suggested-by-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Add POWER9/10 chiptod modelNicholas Piggin
The ChipTOD (for Time-Of-Day) is a chip pervasive facility in IBM POWER (powernv) processors that keeps a time of day clock. In particular for this model are facilities that initialise and start the time of day clock, and that synchronise that clock to cores on the chip, and to other chips. In this way, all cores on all chips can synchronise timebase (TB). This model implements functionality sufficient to run the skiboot chiptod synchronisation procedure (with the following core timebase state machine implementation). It does not modify the TB in the cores where the real hardware would, because the QEMU ppc timebase implementation is always synchronised acros all cores. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc: N1 chiplet wiringChalapathi V
This part of the patchset connects the nest1 chiplet model to p10 chip. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc: Add N1 chiplet modelChalapathi V
The N1 chiplet handle the high speed i/o traffic over PCIe and others. The N1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a N1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented. This commit also implement the read/write method for the powerbus scom registers Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc: Add pnv nest pervasive common chiplet modelChalapathi V
A POWER10 chip is divided into logical units called chiplets. Chiplets are broadly divided into "core chiplets" (with the processor cores) and "nest chiplets" (with everything else). Each chiplet has an attachment to the pervasive bus (PIB) and with chiplet-specific registers. All nest chiplets have a common basic set of registers and This model will provide the registers functionality for common registers of nest chiplet (Pervasive Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets) This commit implement the read/write functions of chiplet control registers. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power controlGlenn Miles
The Power Hypervisor code expects to see a pca9552 device connected to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left- justified address of 0xC6). This is used by hypervisor code to control PCIe slot power during hotplug events. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs.Harsh Prateek Bora
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to the range of CPU IPIs during initialization of nr-irqs property. It is more appropriate to have its own define which can be further reused as appropriate for correct interpretation. Suggested-by: Cedric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Kowshik Jois <kowsjois@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_prPhilippe Mathieu-Daudé
Since 'softmmu' is quite a loaded term in QEMU, rename the vhyp MMU facilities to use the vhyp_mmu_ prefix rather than softmmu_. vhyp_mmu_ is chosen because the code that manipulates the hash table via guest software hypercalls is QEMU's implementation of the PAPR hypervisor interface, called vhyp. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> [npiggin: Pick a different name, explain it in changelog.] Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-22hw/ppc/ppc4xx_pci: Extract PCI host definitions to hw/pci-host/ppc4xx.hPhilippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240215105017.57748-3-philmd@linaro.org>
2024-01-30include: Clean up includesPeter Maydell
This commit was created with scripts/clean-includes: ./scripts/clean-includes --git include include/*/*.h include/*/*/*.h All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-05hw/ppc/xive2_regs: Remove unnecessary 'cpu.h' inclusionPhilippe Mathieu-Daudé
xive2_regs.h only requires declarations from "qemu/bswap.h". Include it instead of the huge target-specific "cpu.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20231122183920.17905-1-philmd@linaro.org>
2023-11-08Merge tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu into stagingStefan Hajnoczi
ppc patch queue for 2023-11-07: This queue, the last one before the 8.2 feature freeze, has miscellanous changes that includes new PowerNV features and the new AmigaONE XE board. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZUqiORYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFkBSUA/2qm8CyrRqY5+tsjtWQqZmPZ3L1F # CgnXFNqtY2tzbTe5AQCi6FeQBEmXbZYVfryZyA+CQ4DUERc+18pe6hV3bBR9Cg== # =cnHS # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Nov 2023 04:46:49 HKT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu: ppc: qtest already exports qtest_rtas_call() hw/pci-host: Update PHB5 XSCOM registers ppc/pnv: Fix number of I2C engines and ports for power9/10 ppc/pnv: Connect PNV I2C controller to powernv10 ppc/pnv: Connect I2C controller model to powernv9 chip ppc/pnv: Add an I2C controller model tests/avocado: Add test for amigaone board hw/ppc: Add emulation of AmigaOne XE board hw/pci-host: Add emulation of Mai Logic Articia S Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07ppc: qtest already exports qtest_rtas_call()Juan Quintela
Having two functions with the same name is a bad idea. As spapr only uses the function locally, made it static. When you compile with clang, you get this compilation error: /usr/bin/ld: tests/qtest/libqos/libqos.fa.p/.._libqtest.c.o: in function `qtest_rtas_call': /scratch/qemu/clang/full/all/../../../../../mnt/code/qemu/full/tests/qtest/libqtest.c:1195: multiple definition of `qtest_rtas_call'; libqemu-ppc64-softmmu.fa.p/hw_ppc_spapr_rtas.c.o:/scratch/qemu/clang/full/all/../../../../../mnt/code/qemu/full/hw/ppc/spapr_rtas.c:536: first defined here clang-16: error: linker command failed with exit code 1 (use -v to see invocation) ninja: build stopped: subcommand failed. make: *** [Makefile:162: run-ninja] Error 1 Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20231030163834.4638-1-quintela@redhat.com> [dhb: remove 'spapr_rtas.h' include from spapr_rtas.c] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07ppc/pnv: Fix number of I2C engines and ports for power9/10Glenn Miles
Power9 is supposed to have 4 PIB-connected I2C engines with the following number of ports on each engine: 0: 2 1: 13 2: 2 3: 2 Power10 also has 4 engines but has the following number of ports on each engine: 0: 14 1: 14 2: 2 3: 16 Current code assumes that they all have the same (maximum) number. This can be a problem if software expects to see a certain number of ports present (Power Hypervisor seems to care). Fixed this by adding separate tables for power9 and power10 that map the I2C controller number to the number of I2C buses that should be attached for that engine. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Message-ID: <20231025152714.956664-1-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07ppc/pnv: Connect PNV I2C controller to powernv10Glenn Miles
Wires up four I2C controller instances to the powernv10 chip XSCOM address space. Each controller instance is wired up to two I2C buses of its own. No other I2C devices are connected to the buses at this time. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20231017221434.810363-1-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07ppc/pnv: Connect I2C controller model to powernv9 chipCédric Le Goater
Wires up three I2C controller instances to the powernv9 chip XSCOM address space. Each controller instance is wired up to a single I2C bus of its own. No other I2C devices are connected to the buses at this time. Signed-off-by: Cédric Le Goater <clg@kaod.org> [milesg: Split wiring from addition of model itself] [milesg: Added new commit message] [milesg: Moved hardcoded attributes into PnvChipClass] [milesg: Removed TODO comment for I2C] Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <20231016222013.3739530-3-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07ppc/pnv: Add an I2C controller modelCédric Le Goater
The more recent IBM power processors have an embedded I2C controller that is accessible by software via the XSCOM address space. Each instance of the I2C controller is capable of controlling multiple I2C buses (one at a time). Prior to beginning a transaction on an I2C bus, the bus must be selected by writing the port number associated with the bus into the PORT_NUM field of the MODE register. Once an I2C bus is selected, the status of the bus can be determined by reading the Status and Extended Status registers. I2C bus transactions can be started by writing a command to the Command register and reading/writing data from/to the FIFO register. Not supported : . 10 bit I2C addresses . Multimaster . Slave Signed-off-by: Cédric Le Goater <clg@kaod.org> [milesg: Split wiring to powernv9 into its own commit] [milesg: Added more detail to commit message] [milesg: Added SPDX Licensed Identifier to new files] [milesg: updated copyright dates] [milesg: Added use of g_autofree] [milesg: Added NULL check after pnv_i2c_get_bus] Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <20231016222013.3739530-2-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07target/ppc: Move PowerPCCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares the PowerPCCPUClass type. This forward declaration is sufficient for code in hw/ to use the QOM definitions. No need to expose the structure definition. Keep it local to target/ppc/ by moving it to target/ppc/cpu.h. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013125630.95116-5-philmd@linaro.org>
2023-10-19hw/ppc/pnv_xscom: Move sysbus_mmio_map() call within pnv_xscom_init()Philippe Mathieu-Daudé
In order to make the next commit trivial, move sysbus_init_mmio() calls just before the corresponding sysbus_mmio_map() calls. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-4-philmd@linaro.org>
2023-10-19hw/ppc/pnv_xscom: Rename pnv_xscom_realize(Error **) -> pnv_xscom_init()Philippe Mathieu-Daudé
pnv_xscom_realize() is not used to *realize* QDev object, rename it as pnv_xscom_init(). The Error** argument is unused: remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-3-philmd@linaro.org>
2023-09-29hw/ppc: Clean up local variable shadowing in _FDT helper routineCédric Le Goater
this fixes numerous warnings of this type : In file included from ../hw/ppc/spapr_pci.c:43: ../hw/ppc/spapr_pci.c: In function ‘spapr_dt_phb’: ../include/hw/ppc/fdt.h:18:13: warning: declaration of ‘ret’ shadows a previous local [-Wshadow=compatible-local] 18 | int ret = (exp); \ | ^~~ ../hw/ppc/spapr_pci.c:2355:5: note: in expansion of macro ‘_FDT’ 2355 | _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); | ^~~~ ../hw/ppc/spapr_pci.c:2311:24: note: shadowed declaration is here 2311 | int bus_off, i, j, ret; | ^~~ Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230918145850.241074-2-clg@kaod.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2023-09-20ppc: spelling fixesMichael Tokarev
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2023-09-18spapr: Remove support for NVIDIA V100 GPU with NVLink2Cédric Le Goater
NVLink2 support was removed from the PPC PowerNV platform and VFIO in Linux 5.13 with commits : 562d1e207d32 ("powerpc/powernv: remove the nvlink support") b392a1989170 ("vfio/pci: remove vfio_pci_nvlink2") This was 2.5 years ago. Do the same in QEMU with a revert of commit ec132efaa81f ("spapr: Support NVIDIA V100 GPU with NVLink2"). Some adjustements are required on the NUMA part. Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Acked-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Message-ID: <20230918091717.149950-1-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-09-06ppc/xive: Introduce a new XiveRouter end_notify() handlerCédric Le Goater
It will help us model the END triggers on the PowerNV machine, which can be rerouted to another interrupt controller. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-06spapr: Fix record-replay machine reset consuming too many eventsNicholas Piggin
spapr_machine_reset gets a random number to populate the device-tree rng seed with. When loading a snapshot for record-replay, the machine is reset again, and that tries to consume the random event record again, crashing due to inconsistent record Fix this by saving the seed to populate the device tree with, and skipping the rng on snapshot load. Acked-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-06spapr: Fix machine reset deadlock from replay-recordNicholas Piggin
When the machine is reset to load a new snapshot while being debugged with replay-record, it is done from another thread, so the CPU does not run the register setting operations. Set CPU registers directly in machine reset. Cc: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-06hw/ppc: Reset timebase facilities on machine resetNicholas Piggin
Lower interrupts, delete timers, and set time facility registers back to initial state on machine reset. This is not so important for record-replay since timebase and decrementer are migrated, but it gives a cleaner reset state. Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: checkpatch.pl fixes ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-07-07ppc/pnv: Add QME region for P10Joel Stanley
The Quad Management Engine (QME) manages power related settings for its quad. The xscom region is separate from the quad xscoms, therefore a new region is added. The xscoms in a QME select a given core by selecting the forth nibble. Implement dummy reads for the stop state history (SSH) and special wakeup (SPWU) registers. This quietens some sxcom errors when skiboot boots on p10. Power9 does not have a QME. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20230707071213.9924-1-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Set P10 core xscom region size to match hardwareNicholas Piggin
The P10 core xscom memory regions overlap because the size is wrong. The P10 core+L2 xscom region size is allocated as 0x1000 (with some unused ranges). "EC" is used as a closer match, as "EX" includes L3 which has a disjoint xscom range that would require a different region if it were implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230706053923.115003-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440_pcix: Rename QOM type define abd move it to common headerBALATON Zoltan
Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value, move it to common header and use it also in sam460ex to replace hard coded type name. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <1a1c3fe4b120f345d1005ad7ceca4500783691f7.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc4xx_pci: Add define for ppc4xx-host-bridge type nameBALATON Zoltan
Add a QOM type name define for ppc4xx-host-bridge in the common header and replace direct use of the string name with the constant. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <f6e2956b3a09ee481b970ef7873b374c846ba0a8.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc4xx_pci: Rename QOM type name defineBALATON Zoltan
Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to match each other and other similar types and to avoid confusion with "ppc4xx-host-bridge" type defined in same file. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <c59c28ef440633dbd1de0bda0a93b7862ef91104.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Remove ppc460ex_pcie_init legacy init functionBALATON Zoltan
After previous changes we can now remove the legacy init function and move the device creation to board code. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <29aafeea9f1c871c739600a7b093c5456e8a1dc8.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Add P10 quad xscom modelJoel Stanley
Add a PnvQuad class for the P10 powernv machine. No xscoms are implemented yet, but this allows them to be added. The size is reduced to avoid the quad region from overlapping with the core region. address-space: xscom-0 0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0 0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0 0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3 0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2 0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1 0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0 Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230704054204.168547-4-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Subclass quad xscom callbacksJoel Stanley
Make the existing pnv_quad_xscom_read/write be P9 specific, in preparation for a different P10 callback. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230704054204.168547-3-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive: Add property on xive sources to define PQ state on resetFrederic Barrat
The PQ state of a xive interrupt is always initialized to Q=1, which means the interrupt is disabled. Since a xive source can be embedded in many objects, this patch adds a property to allow that behavior to be refined if needed. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230703081215.55252-2-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>