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2013-07-29xics: rename types to be sane and follow coding styleAnthony Liguori
Basically, in HW the layout of the interrupt network is: - One ICP per processor thread (the "presenter"). This contains the registers to fetch a pending interrupt (ack), EOI, and control the processor priority. - One ICS per logical source of interrupts (ie, one per PCI host bridge, and a few others here or there). This contains the per-interrupt source configuration (target processor(s), priority, mask) and the per-interrupt internal state. Under PAPR, there is a single "virtual" ICS ... somewhat (it's a bit oddball what pHyp does here, arguably there are two but we can ignore that distinction). There is no register level access. A pair of firmware (RTAS) calls is used to configure each virtual interrupt. So our model here is somewhat the same. We have one ICS in the emulated XICS which arguably *is* the emulated XICS, there's no point making it a separate "device", that would just be gross, and each VCPU has an associated ICP. Yet we call the "XICS" struct icp_state and then the ICPs 'struct icp_server_state'. It's particularly confusing when all of the functions have xics_prefixes yet take *icp arguments. Rename: struct icp_state -> XICSState struct icp_server_state -> ICPState struct ics_state -> ICSState struct ics_irq_state -> ICSIRQState Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-12-git-send-email-aliguori@us.ibm.com [aik: added ics_resend() on post_load] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support with KVMAlexey Kardashevskiy
At present, the savevm / migration support for the pseries machine will not work when KVM is enabled. That's because KVM manages the guest's hash page table in the host kernel, so qemu has no visibility of it. This patch fixes this by using new kernel interfaces to extract and reinsert the guest's hash table during the migration process. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1374175984-8930-11-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support for pseries machineDavid Gibson
This adds the necessary pieces to implement savevm / migration for the pseries machine. The most complex part here is migrating the hash table - for the paravirtualized pseries machine the guest's hash page table is not stored within guest memory, but externally and the guest accesses it via hypercalls. This patch uses a hypervisor reserved bit of the HPTE as a dirty bit (tracking changes to the HPTE itself, not the page it references). This is used to implement a live migration style incremental save and restore of the hash table contents. Normally a hash table is 16MB but it can get bigger depending on how much RAM the guest has. Due to its nature, updates to it are random so the live migration style is used for it. In addition it adds VMStateDescription information to save and restore the (few) remaining pieces of state information needed by the pseries machine. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374175984-8930-9-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29spapr-tce: make sPAPRTCETable a proper deviceAnthony Liguori
Model TCE tables as a device that's hooked up as a child object to the owner. Besides the code cleanup, we get a few nice benefits: 1) free actually works now (it was dead code before) 2) the TCE information is visible in the device tree 3) we can expose table information as properties such that if we change the window_size, we can use globals to keep migration working. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-6-git-send-email-aliguori@us.ibm.com [dwg: pseries: savevm support for PAPR TCE tables] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [alexey: ppc kvm: fix to compile] Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support for VIO devicesDavid Gibson
This patch adds helpers to allow PAPR VIO devices to save state common to all VIO devices during savevm. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374175984-8930-3-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-11PPC: dbdma: Support unaligned DMA accessAlexander Graf
The DBDMA engine really just reads bytes from a producing device (IDE in our case) and shoves these bytes into memory. It doesn't care whether any alignment takes place or not. Our code today however assumes that block accesses always happen on sector (512 byte) boundaries. This is a fair assumption for most cases. However, Mac OS X really likes to do unaligned, incomplete accesses that it finishes with the next DMA request. So we need to read / write the unaligned bits independent of the actual asynchronous request, because that one can only handle 512-byte-aligned data. We also need to cache these unaligned sectors until the next DMA request, at which point the data might be successfully flushed from the pipe. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Move processing to ioAlexander Graf
Soon we will introduce intermediate processing pauses which will allow the bottom half to restart a DMA request that couldn't be fulfilled yet. For that to work, move the processing variable into the io struct which is what DMA providers work with. While touching it, also change it into a bool Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Move static bh variable to device structAlexander Graf
The DBDMA controller has a bottom half to asynchronously process DMA request queues. This bh was stored as a gross static variable. Move it into the device struct instead. While at it, move all users of it to the new generic kick function. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Introduce kick functionAlexander Graf
The DBDMA engine really is running all the time, waiting for input. However we don't want to waste cycles constantly polling. So introduce a kick function that data providers can call to notify the DBDMA controller of new input. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Move defines into header fileAlexander Graf
We usually keep struct and constant definitions in header files. Move them there to stay consistent and to make access to fields easier. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-09intc/openpic: Build openpic only onceAndreas Färber
Since current_cpu is CPUState it no longer depends on CPUPPCState. Move ppce500_set_mpic_proxy() to a new hw/ppc/ppc_e500.h because hw/ppc/ppc.h is too heavily using CPUPPCState and PowerPCCPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-04spapr_iommu: pass device to spapr_tce_new_table and use it to set ownerPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-01PPC: Add clock-frequency export for Mac machinesAlexander Graf
Support in fwcfg has been around for exposure of the clock-frequency CPU property. OpenBIOS reads it, we just never exposed it. Since Mac OS X is very picky about its clock frequency values, let's just take a known good value and always expose that. Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01spapr-rtas: add CPU argument to RTAS callsAnthony Liguori
RTAS is a hypervisor provided binary blob that a guest loads and calls into to execute certain functions. It's similar to the vsyscall page in Linux or the short lived VMCI paravirt interface from VMware. The QEMU implementation of the RTAS blob is simply a passthrough that proxies all RTAS calls to the hypervisor via an hypercall. While we pass a CPU argument for hypercall handling in QEMU, we don't pass it for RTAS calls. Since some RTAs calls require making hypercalls (normally RTAS is implemented as guest code) we have nasty hacks to allow that. Add a CPU argument to RTAS call handling so we can more easily invoke hypercalls just as guest code would. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01intc/openpic_kvm: Fix QOM and build issuesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01intc/openpic: QOM'ifyAndreas Färber
Introduce type constant and cast macro. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01kvm/openpic: in-kernel mpic supportScott Wood
Enables support for the in-kernel MPIC that thas been merged into the KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex Graf (along with some other improvements). Note from Alex regarding kvm_irqchip_create(): On x86, one would call kvm_irqchip_create() to initialize an in-kernel interrupt controller. That function then goes ahead and initializes global capability variables as well as the default irq routing table. On ppc, we can't call kvm_irqchip_create() because we can have different types of interrupt controllers. So we want to do all the things that function would do for us in the in-kernel device init handler. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build, fix ppcemb] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01openpic: factor out some common defines into openpic.hScott Wood
...for use by the KVM in-kernel irqchip stub. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-06-20dma: eliminate DMAContextPaolo Bonzini
The DMAContext is a simple pointer to an AddressSpace that is now always already available. Make everyone hold the address space directly, and clean up the DMA API to use the AddressSpace directly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-20spapr_vio: take care of creating our own AddressSpace/DMAContextPaolo Bonzini
Fetch the root region from the sPAPRTCETable, and use it to build an AddressSpace and DMAContext. Now, everywhere we have a DMAContext we also have access to the corresponding AddressSpace (either because we create it just before the DMAContext, or because dma_context_memory's AddressSpace is trivially address_space_memory). Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-20spapr: use memory core for iommu supportPaolo Bonzini
Now we can stop using a "translating" DMAContext, but we do not yet modify the sPAPRTCETable users to get an AddressSpace; they keep using the table via a DMAContext. Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-20spapr: convert TCE API to use an opaque typePaolo Bonzini
The TCE table is currently returned as a DMAContext, and non-type-safe APIs are called later passing back the DMAContext. Since we want to move away from DMAContext, use an opaque type instead, and add an accessor to retrieve the DMAContext from it. Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move headers to include/Paolo Bonzini
Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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