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AgeCommit message (Expand)Author
2020-01-08ppc/pnv: fix check on return value of blk_getlength()Cédric Le Goater
2020-01-08pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptrGreg Kurz
2020-01-08xive: Add a "presenter" link property to the TCTX objectCédric Le Goater
2020-01-08ppc/pnv: Add a "pnor" const link property to the BMC internal simulatorGreg Kurz
2020-01-08ppc/pnv: Add an "nr-threads" property to the base chip classGreg Kurz
2020-01-08spapr, pnv, xive: Add a "xive-fabric" link to the XIVE routerGreg Kurz
2020-01-08pnv/xive: Use device_class_set_parent_realize()Greg Kurz
2020-01-08ppc/pnv: Introduce a "xics" property under the POWER8 chipCédric Le Goater
2020-01-08spapr/xive: Use device_class_set_parent_realize()Greg Kurz
2019-12-17ppc/pnv: Drop PnvChipClass::typeGreg Kurz
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_pcba() methodGreg Kurz
2019-12-17ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpersGreg Kurz
2019-12-17ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()Greg Kurz
2019-12-17ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()Greg Kurz
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_core_base() methodGreg Kurz
2019-12-17ppc/pnv: Introduce PnvChipClass::intc_print_info() methodGreg Kurz
2019-12-17ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpersGreg Kurz
2019-12-17ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()Greg Kurz
2019-12-17ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz
2019-12-17ppc/pnv: Drop PnvPsiClass::chip_typeGreg Kurz
2019-12-17ppc/pnv: Introduce PnvPsiClass::compatGreg Kurz
2019-12-17ppc: Drop useless extern annotation for functionsGreg Kurz
2019-12-17ppc/pnv: Fix OCC common area region mappingCédric Le Goater
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater
2019-12-17ppc/pnv: Make PnvXScomInterface an incomplete typeGreg Kurz
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh
2019-12-17target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater
2019-12-17ppc: Deassert the external interrupt pin in KVM on resetGreg Kurz
2019-12-17spapr: Simplify ovec diffDavid Gibson
2019-12-17spapr: Fold h_cas_compose_response() into h_client_architecture_support()David Gibson
2019-12-17ppc/pnv: Dump the XIVE NVT tableCédric Le Goater
2019-12-17ppc/pnv: Extend XiveRouter with a get_block_id() handlerCédric Le Goater
2019-12-17ppc/pnv: Introduce a pnv_xive_block_id() helperCédric Le Goater
2019-12-17ppc/xive: Introduce a xive_tctx_ipb_update() helperCédric Le Goater
2019-12-17ppc/xive: Remove the get_tctx() XiveRouter handlerCédric Le Goater
2019-12-17ppc/xive: Move the TIMA operations to the controller modelCédric Le Goater
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater
2019-12-17spapr: Pass the maximum number of vCPUs to the KVM interrupt controllerGreg Kurz
2019-12-17ppc/xive: Extend the TIMA operation with a XivePresenter parameterCédric Le Goater
2019-12-17ppc/xive: Introduce a XiveFabric interfaceCédric Le Goater
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater
2019-12-17ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helperCédric Le Goater
2019-12-17ppc: Introduce a ppc_cpu_pir() helperCédric Le Goater
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz
2019-12-17ppc/xive: Introduce a XivePresenter interfaceCédric Le Goater
2019-12-17ppc/pnv: Create BMC devices at machine initCédric Le Goater
2019-12-17ppc/pnv: Add HIOMAP commandsCédric Le Goater
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