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path: root/include/hw/ppc
AgeCommit message (Expand)Author
2019-12-17ppc/pnv: Make PnvXScomInterface an incomplete typeGreg Kurz
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh
2019-12-17target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater
2019-12-17ppc: Deassert the external interrupt pin in KVM on resetGreg Kurz
2019-12-17spapr: Simplify ovec diffDavid Gibson
2019-12-17spapr: Fold h_cas_compose_response() into h_client_architecture_support()David Gibson
2019-12-17ppc/pnv: Dump the XIVE NVT tableCédric Le Goater
2019-12-17ppc/pnv: Extend XiveRouter with a get_block_id() handlerCédric Le Goater
2019-12-17ppc/pnv: Introduce a pnv_xive_block_id() helperCédric Le Goater
2019-12-17ppc/xive: Introduce a xive_tctx_ipb_update() helperCédric Le Goater
2019-12-17ppc/xive: Remove the get_tctx() XiveRouter handlerCédric Le Goater
2019-12-17ppc/xive: Move the TIMA operations to the controller modelCédric Le Goater
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater
2019-12-17spapr: Pass the maximum number of vCPUs to the KVM interrupt controllerGreg Kurz
2019-12-17ppc/xive: Extend the TIMA operation with a XivePresenter parameterCédric Le Goater
2019-12-17ppc/xive: Introduce a XiveFabric interfaceCédric Le Goater
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater
2019-12-17ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helperCédric Le Goater
2019-12-17ppc: Introduce a ppc_cpu_pir() helperCédric Le Goater
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz
2019-12-17ppc/xive: Introduce a XivePresenter interfaceCédric Le Goater
2019-12-17ppc/pnv: Create BMC devices at machine initCédric Le Goater
2019-12-17ppc/pnv: Add HIOMAP commandsCédric Le Goater
2019-12-17ppc/xive: Introduce helpers for the NVT idCédric Le Goater
2019-12-17ppc/xive: Record the IPB in the associated NVTCédric Le Goater
2019-12-17ppc/pnv: Add a PNOR modelCédric Le Goater
2019-11-18ppc: Add intc_destroy() handlers to SpaprInterruptController/PnvChipGreg Kurz
2019-10-24spapr/xive: Set the OS CAM line at resetCédric Le Goater
2019-10-24ppc: Reset the interrupt presenter from the CPU reset handlerCédric Le Goater
2019-10-24ppc/pnv: Add a PnvChip pointer to PnvCoreCédric Le Goater
2019-10-24spapr: Move SpaprIrq::nr_xirqs to SpaprMachineClassDavid Gibson
2019-10-24spapr: Remove SpaprIrq::nr_msisDavid Gibson
2019-10-24spapr, xics, xive: Move SpaprIrq::post_load hook to backendsDavid Gibson
2019-10-24spapr, xics, xive: Move SpaprIrq::reset hook logic into activate/deactivateDavid Gibson
2019-10-24spapr: Remove SpaprIrq::init_kvm hookDavid Gibson
2019-10-24spapr, xics, xive: Match signatures for XICS and XIVE KVM connect routinesDavid Gibson
2019-10-24spapr, xics, xive: Move dt_populate from SpaprIrq to SpaprInterruptControllerDavid Gibson
2019-10-24spapr, xics, xive: Move print_info from SpaprIrq to SpaprInterruptControllerDavid Gibson
2019-10-24spapr, xics, xive: Move set_irq from SpaprIrq to SpaprInterruptControllerDavid Gibson
2019-10-24spapr: Formalize notion of active interrupt controllerDavid Gibson
2019-10-24spapr, xics, xive: Move irq claim and free from SpaprIrq to SpaprInterruptCon...David Gibson
2019-10-24spapr, xics, xive: Move cpu_intc_create from SpaprIrq to SpaprInterruptContro...David Gibson
2019-10-24spapr, xics, xive: Introduce SpaprInterruptController QOM interfaceDavid Gibson
2019-10-24spapr: Set VSMT to smp_threads by defaultGreg Kurz
2019-10-24ppc/pnv: Improve trigger data definitionCédric Le Goater
2019-10-04spapr: Eliminate SpaprIrq::init hookDavid Gibson
2019-10-04spapr: Use less cryptic representation of which irq backends are supportedDavid Gibson
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