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path: root/include/hw/ppc/pnv.h
AgeCommit message (Expand)Author
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater
2019-12-17ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helperCédric Le Goater
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz
2019-12-17ppc/pnv: Create BMC devices at machine initCédric Le Goater
2019-12-17ppc/pnv: Add HIOMAP commandsCédric Le Goater
2019-12-17ppc/pnv: Add a PNOR modelCédric Le Goater
2019-11-18ppc: Add intc_destroy() handlers to SpaprInterruptController/PnvChipGreg Kurz
2019-10-24ppc: Reset the interrupt presenter from the CPU reset handlerCédric Le Goater
2019-10-04hw/ppc/pnv_homer: add PowerNV homer device modelBalamuruhan S
2019-10-04hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARsBalamuruhan S
2019-07-02ppc/pnv: remove xscom_base field from PnvChipCédric Le Goater
2019-07-02ppc/pnv: fix XSCOM MMIO base address for P9 machines with multiple chipsCédric Le Goater
2019-05-13Clean up ill-advised or unusual header guardsMarkus Armbruster
2019-03-12ppc/pnv: POWER9 XSCOM quad supportCédric Le Goater
2019-03-12ppc/pnv: add a OCC model for POWER9Cédric Le Goater
2019-03-12ppc/pnv: add a LPC Controller model for POWER9Cédric Le Goater
2019-03-12ppc/pnv: add a 'dt_isa_nodename' to the chipCédric Le Goater
2019-03-12ppc/pnv: add a PSI bridge model for POWER9Cédric Le Goater
2019-03-12ppc/pnv: add a PSI bridge class modelCédric Le Goater
2019-03-12ppc/pnv: introduce a new pic_print_info() operation to the chip modelCédric Le Goater
2019-03-12ppc/pnv: introduce a new dt_populate() operation to the chip modelCédric Le Goater
2019-03-12ppc/pnv: add a XIVE interrupt controller model for POWER9Cédric Le Goater
2019-01-09spapr: modify the prototype of the cpu_intc_create() methodCédric Le Goater
2018-06-21ppc/pnv: introduce Pnv8Chip and Pnv9Chip modelsCédric Le Goater
2018-06-21ppc/pnv: introduce a new isa_create() operation to the chip modelCédric Le Goater
2018-06-21ppc/pnv: introduce a new intc_create() operation to the chip modelCédric Le Goater
2018-01-17ppc/pnv: fix XSCOM core addressing on POWER9Cédric Le Goater
2018-01-17ppc/pnv: introduce pnv*_is_power9() helpersCédric Le Goater
2018-01-10ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistencyCédric Le Goater
2017-10-17ppc: pnv: drop PnvChipClass::cpu_model fieldIgor Mammedov
2017-10-17ppc: pnv: normalize core/chip type namesIgor Mammedov
2017-10-17ppc: pnv: use generic cpu_model parsingIgor Mammedov
2017-05-11pnv: Fix build failures on some host platformsDavid Gibson
2017-04-26ppc/pnv: generate an OEM SEL event on shutdownCédric Le Goater
2017-04-26ppc/pnv: add initial IPMI sensors for the BMC simulatorCédric Le Goater
2017-04-26ppc/pnv: Add OCC model stub with interrupt supportBenjamin Herrenschmidt
2017-04-26ppc/pnv: Add cut down PSI bridge model and hookup external interruptCédric Le Goater
2017-04-26ppc/pnv: add memory regions for the ICP registersCédric Le Goater
2017-04-26ppc/pnv: add a helper to calculate MMIO addresses registersCédric Le Goater
2016-11-15ppc/pnv: add a 'xscom_core_base' field to PnvChipClassCédric Le Goater
2016-11-15ppc/pnv: fix compile breakage on old gccCédric Le Goater
2016-10-28ppc/pnv: add a ISA busCédric Le Goater
2016-10-28ppc/pnv: add a LPC controllerBenjamin Herrenschmidt
2016-10-28ppc/pnv: add XSCOM infrastructureCédric Le Goater
2016-10-28ppc/pnv: add a PnvCore objectCédric Le Goater
2016-10-28ppc/pnv: add a PIR handler to PnvChipCédric Le Goater
2016-10-28ppc/pnv: add a core mask to PnvChipCédric Le Goater
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