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path: root/include/hw/ppc/pnv.h
AgeCommit message (Expand)Author
2021-08-27ppc/pnv: Use a simple incrementing index for the chip-idCédric Le Goater
2021-08-27ppc/pnv: Change the POWER10 machine to support DD2 onlyCédric Le Goater
2021-02-10ppc/pnv: Introduce a LPC FW memory region attribute to map the PNORCédric Le Goater
2020-11-15non-virt: Fix Lesser GPL version numberChetan Pant
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
2020-04-07ppc/pnv: Create BMC devices only when defaults are enabledCédric Le Goater
2020-02-02ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridgeCédric Le Goater
2020-02-02ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridgeBenjamin Herrenschmidt
2020-02-02ppc/pnv: Add support for "hostboot" modeCédric Le Goater
2020-01-08pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptrGreg Kurz
2020-01-08ppc/pnv: Add a "pnor" const link property to the BMC internal simulatorGreg Kurz
2020-01-08ppc/pnv: Add an "nr-threads" property to the base chip classGreg Kurz
2020-01-08ppc/pnv: Introduce a "xics" property under the POWER8 chipCédric Le Goater
2019-12-17ppc/pnv: Drop PnvChipClass::typeGreg Kurz
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_pcba() methodGreg Kurz
2019-12-17ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpersGreg Kurz
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_core_base() methodGreg Kurz
2019-12-17ppc/pnv: Introduce PnvChipClass::intc_print_info() methodGreg Kurz
2019-12-17ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpersGreg Kurz
2019-12-17ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()Greg Kurz
2019-12-17ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz
2019-12-17ppc/pnv: Fix OCC common area region mappingCédric Le Goater
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater
2019-12-17ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helperCédric Le Goater
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz
2019-12-17ppc/pnv: Create BMC devices at machine initCédric Le Goater
2019-12-17ppc/pnv: Add HIOMAP commandsCédric Le Goater
2019-12-17ppc/pnv: Add a PNOR modelCédric Le Goater
2019-11-18ppc: Add intc_destroy() handlers to SpaprInterruptController/PnvChipGreg Kurz
2019-10-24ppc: Reset the interrupt presenter from the CPU reset handlerCédric Le Goater
2019-10-04hw/ppc/pnv_homer: add PowerNV homer device modelBalamuruhan S
2019-10-04hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARsBalamuruhan S
2019-07-02ppc/pnv: remove xscom_base field from PnvChipCédric Le Goater
2019-07-02ppc/pnv: fix XSCOM MMIO base address for P9 machines with multiple chipsCédric Le Goater
2019-05-13Clean up ill-advised or unusual header guardsMarkus Armbruster
2019-03-12ppc/pnv: POWER9 XSCOM quad supportCédric Le Goater
2019-03-12ppc/pnv: add a OCC model for POWER9Cédric Le Goater
2019-03-12ppc/pnv: add a LPC Controller model for POWER9Cédric Le Goater
2019-03-12ppc/pnv: add a 'dt_isa_nodename' to the chipCédric Le Goater
2019-03-12ppc/pnv: add a PSI bridge model for POWER9Cédric Le Goater
2019-03-12ppc/pnv: add a PSI bridge class modelCédric Le Goater
2019-03-12ppc/pnv: introduce a new pic_print_info() operation to the chip modelCédric Le Goater
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