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2019-02-28hw/arm/armsse: Wire up the MHUsPeter Maydell
Create and connect the MHUs in the SSE-200. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219125808.25174-3-peter.maydell@linaro.org
2019-02-21hw/arm/armsse: Make 0x5... alias region work for per-CPU devicesPeter Maydell
The region 0x40010000 .. 0x4001ffff and its secure-only alias at 0x50010000... are for per-CPU devices. We implement this by giving each CPU its own container memory region, where the per-CPU devices live. Unfortunately, the alias region which makes devices mapped at 0x4... addresses also appear at 0x5... is only implemented in the overall "all CPUs" container. The effect of this bug is that the CPU_IDENTITY register block appears only at 0x4001f000, but not at the 0x5001f000 alias where it should also appear. Guests (like very recent Arm Trusted Firmware-M) which try to access it at 0x5001f000 will crash. Fix this by moving the handling for this alias from the "all CPUs" container to the per-CPU container. (We leave the aliases for 0x1... and 0x3... in the overall container, because there are no per-CPU devices there.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190215180500.6906-1-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-21hw/arm/armsse: Allow boards to specify init-svtorPeter Maydell
The Musca boards have DAPLink firmware that sets the initial secure VTOR value (the location of the vector table) differently depending on the boot mode (from flash, from RAM, etc). Export the init-svtor as a QOM property of the ARMSSE object so that the board can change it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header commentPeter Maydell
In commit 4b635cf7a95e501211 we added a QOM property to the ARMSSE object, but forgot to add it to the documentation comment in the header. Correct the omission. Fixes: 4b635cf7a95e501211 ("hw/arm/armsse: Make SRAM bank size configurable") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-01arm: Instantiate NRF51 special NVM's and NVMCSteffen Görtz
Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190201023357.22596-3-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01hw/arm/armsse: Add SSE-200 modelPeter Maydell
Add a model of the SSE-200, now we have put in all the code that lets us make it different from the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-22-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add CPU_IDENTITY block to SSE-200Peter Maydell
Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-21-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stub for CPU local control registersPeter Maydell
The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-19-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stub for cache control registersPeter Maydell
The SSE-200 gives each CPU a register bank to use to control its L1 instruction cache. Put in an unimplemented-device stub for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stubs for PPUsPeter Maydell
Add unimplemented-device stubs for the various Power Policy Unit devices that the SSE-200 has. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-17-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stubs for MHUsPeter Maydell
The SSE-200 has two Message Handling Units (MHUs), which sit behind the APB PPC0. Wire up some unimplemented-device stubs for these, since we don't yet implement a real model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-16-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Put each CPU in its own cluster objectPeter Maydell
Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-14-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Give each CPU its own view of memoryPeter Maydell
Give each CPU its own container memory region. This is necessary for two reasons: * some devices are instantiated one per CPU and the CPU sees only its own device * since a memory region can only be put into one container, we must give each armv7m object a different MemoryRegion as its 'memory' property, or a dual-CPU configuration will assert on realize when the second armv7m object tries to put the MR into a container when it is already in the first armv7m object's container Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-13-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Support dual-CPU configurationPeter Maydell
The SSE-200 has two Cortex-M33 CPUs. These see the same view of memory, with the exception of the "private CPU region" which has per-CPU devices. Internal device interrupts for SSE-200 devices are mostly wired up to both CPUs, with the exception of a few per-CPU devices. External GPIO inputs on the SSE-200 device are provided for the second CPU's interrupts above 32, as is already the case for the first CPU. Refactor the code to support creation of multiple CPUs. For the moment we leave all CPUs with the same view of memory: this will not work in the multiple-CPU case, but we will fix this in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-12-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Make SRAM bank size configurablePeter Maydell
For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-11-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Make number of SRAM banks parameterisedPeter Maydell
The SSE-200 has four banks of SRAM, each with its own Memory Protection Controller, where the IoTKit has only one. Make the number of SRAM banks a field in ARMSSEInfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-10-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Rename files to hw/arm/armsse.[ch]Peter Maydell
Rename the files that used to be iotkit.[ch] to armsse.[ch] to reflect the fact they new cover multiple Arm subsystems for embedded. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-8-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Refactor into abstract base class and subclassPeter Maydell
The Arm SSE-200 Subsystem for Embedded is a revised and extended version of the older IoTKit SoC. Prepare for adding a model of it by refactoring the IoTKit code into an abstract base class which contains the functionality, driven by a class data block specific to each subclass. (This is the same approach used by the existing bcm283x SoC family implementation.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-6-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Rename IoTKit to ARMSSEPeter Maydell
The Arm IoTKit was effectively the forerunner of a series of subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200: https://developer.arm.com/products/system-design/subsystems These are generally quite similar, though later iterations have extra devices that earlier ones do not. We want to add a model of the SSE-200, which means refactoring the IoTKit code into an abstract base class and subclasses (using the same design that the bcm283x SoC and Aspeed SoC family implementations do). As a first step, rename the IoTKit struct and QOM macros to ARMSSE, which is what we're going to name the base class. We temporarily retain TYPE_IOTKIT to avoid changing the code that instantiates a TYPE_IOTKIT device here and then changing it back again when it is re-introduced as a subclass. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-5-peter.maydell@linaro.org
2019-02-01armv7m: Pass through start-powered-off CPU propertyPeter Maydell
Expose "start-powered-off" as a property of the ARMv7M container, which we just pass through to the CPU object in the same way that we do for "init-svtor" and "idau". (We want this for the SSE-200, which powers up only the first CPU at reset and leaves the second powered down.) As with the other CPU properties here, we can't just use alias properties, because the CPU QOM object is not created until armv7m realize time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-4-peter.maydell@linaro.org
2019-01-29arm: Stub out NRF51 TWI magnetometer/accelerometer detectionSteffen Görtz
Recent microbit firmwares panic if the TWI magnetometer/accelerometer devices are not detected during startup. We don't implement TWI (I2C) so let's stub out these devices just to let the firmware boot. Signed-off by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190110094020.18354-2-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-22hw/pcmcia: Remove PCMCIACardState from "qemu/typedefs.h"Philippe Mathieu-Daudé
There is only one header file requiring this typedef (hw/arm/pxa.h), let it include "hw/pcmcia.h" directly to simplify "qemu/typedefs.h". To clean "qemu/typedefs.h", move the declaration to "hw/pcmcia.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [thuth: slightly tweaked commit message] Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-07arm: Add Clock peripheral stub to NRF51 SOCSteffen Görtz
This stubs enables the microbit-micropython firmware to run on the microbit machine. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-12-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm: Instantiate NRF51 TimersSteffen Görtz
Instantiates TIMER0 - TIMER2 Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-10-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm: Instantiate NRF51 general purpose I/OSteffen Görtz
Instantiates GPIO peripheral model Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-7-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm: Instantiate NRF51 random number generatorSteffen Görtz
Use RNG in SOC. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-5-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm: Add header to host common definition for nRF51 SOC peripheralsSteffen Görtz
Adds a header that provides definitions that are used across nRF51 peripherals Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-3-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controllerPhilippe Mathieu-Daudé
From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and: 7. System Control 7.1. Overview A10 embeds a high-speed SRAM which has been split into five segments. See detailed memory mapping in following table: Area Address Size (Bytes) A1 0x00000000-0x00003FFF 16K A2 0x00004000-0x00007FFF 16K A3 0x00008000-0x0000B3FF 13K A4 0x0000B400-0x0000BFFF 3K Since for emulation purpose we don't need the segmentations, we simply define the 'A' area as a single 48KB SRAM. We don't implement the following others areas: - 'B': 'Secure RAM' (64K), - 'C': Debug/ISP SRAM - 'D': USB SRAM (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000bfff (prio 0, ram): sram A 0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl 0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac 0000000001c18000-0000000001c18fff (prio 0, i/o): ahci 0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci 0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic 0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer 0000000001c28000-0000000001c2801f (prio 0, i/o): serial 0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram Reported-by: Charlie Smurthwaite <charlie@atech.media> Tested-by: Charlie Smurthwaite <charlie@atech.media> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20190104142921.878-1-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clustersLuc Michel
Create two separate CPU clusters for APUs and RPUs. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20181207090135.7651-17-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13hw/arm: versal: Correct the nr of IRQs to 192Edgar E. Iglesias
Correct the nr of IRQs to 192. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20181129163655.20370-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13hw/arm: versal: Use IRQs 111 - 118 for virtio-mmioEdgar E. Iglesias
Use IRQs 111 - 118 for virtio-mmio. The interrupts we're currently using 160+ are not available in the Versal GIC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20181129163655.20370-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-11qom: make interface types abstractMarc-André Lureau
Interfaces don't have instance, let's make the interface type really abstract to avoid confusion. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20181204142023.15982-3-marcandre.lureau@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-11-02hw/arm: versal: Add a model of Xilinx Versal SoCEdgar E. Iglesias
Add a model of Xilinx Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-02hw/arm/nrf51_soc: Connect UART to nRF51 SoCJulia Suvorova
Wire up nRF51 UART in the corresponding SoC. Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/aspeed: Add an Aspeed machine classCédric Le Goater
The code looks better, it removes duplicated lines and it will ease the introduction of common properties for the Aspeed machines. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180921161939.822-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25arm: Add Nordic Semiconductor nRF51 SoCJoel Stanley
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-3-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: wrapped a few long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-24hw/arm/iotkit: Wire up the lines for MSCsPeter Maydell
The IoTKit doesn't have any MSCs itself but it does need some wiring to connect the external signals from MSCs in the outer board model up to the registers and the NVIC IRQ line. We also need to expose a MemoryRegion corresponding to the AHB bus, so that MSCs in the outer board model can use that as their downstream port. (In the FPGA this is the "AHB Slave Expansion" ports shown in the block diagram in the AN505 documentation.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180820141116.9118-14-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24hw/misc/iotkit: Wire up the sysctl and sysinfo register blocksPeter Maydell
Wire up the system control element's register banks (sysctl and sysinfo). This is the last of the previously completely unimplemented components in the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-11-peter.maydell@linaro.org
2018-08-24hw/arm/iotkit: Wire up the S32KTIMERPeter Maydell
The IoTKit has a CMSDK timer device that runs on the S32KCLK. Create this and wire it up. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-8-peter.maydell@linaro.org
2018-08-24hw/arm/iotkit: Wire up the watchdogsPeter Maydell
The IoTKit includes three different instances of the CMSDK APB watchdog; create and wire them up. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-7-peter.maydell@linaro.org
2018-08-24hw/arm/iotkit: Wire up the dualtimerPeter Maydell
Now we have a model of the CMSDK dual timer, we can wire it up in the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-5-peter.maydell@linaro.org
2018-08-16hw/arm: make bitbanded IO optional on ARMv7-MStefan Hajnoczi
Some ARM CPUs have bitbanded IO, a memory region that allows convenient bit access via 32-bit memory loads/stores. This eliminates the need for read-modify-update instruction sequences. This patch makes this optional feature an ARMv7MState qdev property, allowing boards to choose whether they want bitbanding or not. Status of boards: * iotkit (Cortex M33), no bitband * mps2 (Cortex M3), bitband * msf2 (Cortex M3), bitband * stellaris (Cortex M3), bitband * stm32f205 (Cortex M3), bitband As a side-effect of this patch, Peter Maydell noted that the Ethernet controller on mps2 board is now accessible. Previously they were hidden by the bitband region (which does not exist on the real board). Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180814162739.11814-2-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16i.MX6UL: Add i.MX6UL SOCJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 3853ec555d68e7e25d726170833b775796151a07.1532984236.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14arm/virt: Add support for GICv2 virtualization extensionsLuc Michel
Add support for GICv2 virtualization extensions by mapping the necessary I/O regions and connecting the maintenance IRQ lines. Declare those additions in the device tree and in the ACPI tables. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-21-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14xlnx-zynqmp: Improve GIC wiring and MMIO mappingLuc Michel
This commit improve the way the GIC is realized and connected in the ZynqMP SoC. The security extensions are enabled only if requested in the machine state. The same goes for the virtualization extensions. All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ, vIRQ and vFIQ. The missing CPU to GIC timers IRQ connections are also added (HYP and SEC timers). The GIC maintenance IRQs are back-wired to the correct GIC PPIs. Finally, the MMIO mappings are reworked to take into account the ZynqMP specifics. The GIC (v)CPU interface is aliased 16 times: * for the first 0x1000 bytes from 0xf9010000 to 0xf901f000 * for the second 0x1000 bytes from 0xf9020000 to 0xf902f000 Mappings of the virtual interface and virtual CPU interface are mapped only when virtualization extensions are requested. The XlnxZynqMPGICRegion struct has been enhanced to be able to catch all this information. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20180727095421.386-20-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-09hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mrEric Auger
smmu_iommu_mr() aims at returning the IOMMUMemoryRegion corresponding to a given sid. The function extracts both the PCIe bus number and the devfn to return this data. Current computation of devfn is wrong as it only returns the PCIe function instead of slot | function. Fixes 32cfd7f39e08 ("hw/arm/smmuv3: Cache/invalidate config data") Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1530775623-32399-1-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-26hw/arm/smmuv3: Add notifications on invalidationEric Auger
On TLB invalidation commands, let's call registered IOMMU notifiers. Those can only be UNMAP notifiers. SMMUv3 does not support notification on MAP (VFIO). This patch allows vhost use case where IOTLB API is notified on each guest IOTLB invalidation. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1529653501-15358-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-26hw/arm/smmuv3: IOTLB emulationEric Auger
We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256. It is implemented as a hash table whose key is a combination of the 16b asid and 48b IOVA (Jenkins hash). Entries are invalidated on TLB invalidation commands, either globally, or per asid, or per asid/iova. Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1529653501-15358-4-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-26hw/arm/smmuv3: Cache/invalidate config dataEric Auger
Let's cache config data to avoid fetching and parsing STE/CD structures on each translation. We invalidate them on data structure invalidation commands. We put in place a per-smmu mutex to protect the config cache. This will be useful too to protect the IOTLB cache. The caches can be accessed without BQL, ie. in IO dataplane. The same kind of mutex was put in place in the intel viommu. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1529653501-15358-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-26hw/arm/omap: Use qemu_log_mask(GUEST_ERROR) instead of fprintfPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20180624040609.17572-10-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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