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2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost
Replace DECLARE_OBJ_CHECKERS with OBJECT_DECLARE_TYPE where the typedefs can be safely removed. Generated running: $ ./scripts/codeconverter/converter.py -i \ --pattern=DeclareObjCheckers $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-16-ehabkost@redhat.com> Message-Id: <20200831210740.126168-17-ehabkost@redhat.com> Message-Id: <20200831210740.126168-18-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-28Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200828' into staging target-arm queue: * target/arm: Cleanup and refactoring preparatory to SVE2 * armsse: Define ARMSSEClass correctly * hw/misc/unimp: Improve information provided in log messages * hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize * hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize * hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers * hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers * target/arm: Fill in the WnR syndrome bit in mte_check_fail * target/arm: Clarify HCR_EL2 ARMCPRegInfo type * hw/arm/musicpal: Use AddressSpace for DMA transfers * hw/clock: Minor cleanups * hw/arm/sbsa-ref: fix typo breaking PCIe IRQs # gpg: Signature made Fri 28 Aug 2020 10:23:02 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200828: (35 commits) target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd target/arm: Generalize inl_qrdmlah_* helper functions target/arm: Tidy SVE tszimm shift formats target/arm: Split out gen_gvec_ool_zz target/arm: Split out gen_gvec_ool_zzz target/arm: Split out gen_gvec_ool_zzp target/arm: Merge helper_sve_clr_* and helper_sve_movz_* target/arm: Split out gen_gvec_ool_zzzp target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp target/arm: Clean up 4-operand predicate expansion target/arm: Merge do_vector2_p into do_mov_p target/arm: Rearrange {sve,fp}_check_access assert target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn target/arm: Split out gen_gvec_fn_zz qemu/int128: Add int128_lshift armsse: Define ARMSSEClass correctly hw/misc/unimp: Display the offset with width of the region size hw/misc/unimp: Display the value with width of the access size ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-28armsse: Define ARMSSEClass correctlyEduardo Habkost
TYPE_ARM_SSE is a TYPE_SYS_BUS_DEVICE subclass, but ARMSSEClass::parent_class is declared as DeviceClass. It never caused any problems by pure luck: We were not setting class_size for TYPE_ARM_SSE, so class_size of TYPE_SYS_BUS_DEVICE was being used (sizeof(SysBusDeviceClass)). This made the system allocate enough memory for TYPE_ARM_SSE devices even though ARMSSEClass was too small for a sysbus device. Additionally, the ARMSSEClass::info field ended up at the same offset as SysBusDeviceClass::explicit_ofw_unit_address. This would make sysbus_get_fw_dev_path() crash for the device. Luckily, sysbus_get_fw_dev_path() never gets called for TYPE_ARM_SSE devices, because qdev_get_fw_dev_path() is only used by the boot device code, and TYPE_ARM_SSE devices don't appear at the fw_boot_order list. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-id: 20200826181006.4097163-1-ehabkost@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-27pxa2xx: Move QOM macros to headerEduardo Habkost
This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-40-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-27armsse: Rename QOM macros to avoid conflictsEduardo Habkost
Rename TYPE_ARMSSE to TYPE_ARM_SSE, and ARMSSE*() type checking macros to ARM_SSE*(). This will avoid a future conflict between an ARM_SSE() type checking macro and the ARMSSE typedef name. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-26-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-27aspeed_soc: Rename memmap/irqmap enum constantsEduardo Habkost
Some of the enum constant names conflict with the QOM type check macros: ASPEED_GPIO ASPEED_I2C ASPEED_RTC ASPEED_SCU ASPEED_SDHCI ASPEED_SDMC ASPEED_VIC ASPEED_WDT ASPEED_XDMA This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to ASPEED_DEV_*, to avoid conflicts. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-7-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-27allwinner-h3: Rename memmap enum constantsEduardo Habkost
Some of the enum constant names conflict with the QOM type check macros (AW_H3_CCU, AW_H3_SYSCTRL). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to AW_H3_DEV_*, to avoid conflicts. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-24hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 supportEric Auger
HAD is a mandatory features with SMMUv3.1 if S1P is set, which is our case. Other 3.1 mandatory features come with S2P which we don't have. So let's support HAD and advertise SMMUv3.1 support in AIDR. HAD support allows the CD to disable hierarchical attributes, ie. if the HAD0/1 bit is set, the APTable field of table descriptors walked through TTB0/1 is ignored. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-11-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-24hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 supportEric Auger
Add the support for AIDR register. It currently advertises SMMU V3.0 spec. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-10-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-24hw/arm/smmuv3: Get prepared for range invalidationEric Auger
Enhance the smmu_iotlb_inv_iova() helper with range invalidation. This uses the new fields passed in the NH_VA and NH_VAA commands: the size of the range, the level and the granule. As NH_VA and NH_VAA both use those fields, their decoding and handling is factorized in a new smmuv3_s1_range_inval() helper. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-8-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-24hw/arm/smmu-common: Manage IOTLB block entriesEric Auger
At the moment each entry in the IOTLB corresponds to a page sized mapping (4K, 16K or 64K), even if the page belongs to a mapped block. In case of block mapping this unefficiently consumes IOTLB entries. Change the value of the entry so that it reflects the actual mapping it belongs to (block or page start address and size). Also the level/tg of the entry is encoded in the key. In subsequent patches we will enable range invalidation. This latter is able to provide the level/tg of the entry. Encoding the level/tg directly in the key will allow to invalidate using g_hash_table_remove() when num_pages equals to 1. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-6-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-24hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB valueEric Auger
Introduce a specialized SMMUTLBEntry to store the result of the PTW and cache in the IOTLB. This structure extends the generic IOMMUTLBEntry struct with the level of the entry and the granule size. Those latter will be useful when implementing range invalidation. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-5-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-24hw/arm/smmu: Introduce smmu_get_iotlb_key()Eric Auger
Introduce the smmu_get_iotlb_key() helper and the SMMU_IOTLB_ASID() macro. Also move smmu_get_iotlb_key and smmu_iotlb_key_hash in the IOTLB related code section. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-4-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-24hw/arm/smmu-common: Add IOTLB helpersEric Auger
Add two helpers: one to lookup for a given IOTLB entry and one to insert a new entry. We also move the tracing there. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-3-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-21hw/sd/pxa2xx_mmci: Do not create SD card within the SD host controllerPhilippe Mathieu-Daudé
SD/MMC host controllers provide a SD Bus to plug SD cards, but don't come with SD card plugged in :) The machine/board object is where the SD cards are created. Since the PXA2xx is not qdevified, for now create the cards in pxa270_init() which is the SoC model. In the future we will move this to the board model. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200705213350.24725-2-f4bug@amsat.org>
2020-08-03hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for ↵Peter Maydell
SYSRESETREQ The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals when the guest sets the SYSRESETREQ bit in the AIRCR register. This matches the hardware design (where the CPU has a signal of this name and it is up to the SoC to connect that up to an actual reset mechanism), but in QEMU it mostly results in duplicated code in SoC objects and bugs where SoC model implementors forget to wire up the SYSRESETREQ line. Provide a default behaviour for the case where SYSRESETREQ is not actually connected to anything: use qemu_system_reset_request() to perform a system reset. This will allow us to remove the implementations of SYSRESETREQ handling from the boards where that's exactly what it does, and also fixes the bugs in the board models which forgot to wire up the signal: * microbit * mps2-an385 * mps2-an505 * mps2-an511 * mps2-an521 * musca-a * musca-b1 * netduino * netduinoplus2 We still allow the board to wire up the signal if it needs to, in case we need to model more complicated reset controller logic or to model buggy SoC hardware which forgot to wire up the line itself. But defaulting to "reset the system" is more often going to be correct than defaulting to "do nothing". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200728103744.6909-3-peter.maydell@linaro.org
2020-07-20hw/arm/virt: Enable MTE via a machine propertyRichard Henderson
Control this cpu feature via a machine property, much as we do with secure=on, since both require specialized support in the machine setup to be functional. Default MTE to off, since this feature implies extra overhead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200713213341.590275-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13Add the ability to change the FEC PHY MDIO devices numbers on i.MX7 processorJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: c850187322be9930e47c8b234c385a7d0da245cb.1593806826.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: updated for object_property_set_uint() argument reordering] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13Add the ability to change the FEC PHY MDIO device number on i.MX6 processorJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 05a64e83eb1c0c865ac077b22c599425c024c02c.1593806826.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: updated for object_property_set_uint() argument reordering] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13Add the ability to change the FEC PHY MDIO device number on i.MX25 processorJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 9f8923ecd974160ae8f634c275b1100c2cbe66d7.1593806826.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: updated for object_property_set_uint() argument reordering] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13hw/arm/bcm2836: Remove unused 'cpu_type' fieldPhilippe Mathieu-Daudé
The 'cpu_type' has been moved from BCM283XState to BCM283XClass in commit 210f47840d, but we forgot to remove the old variable. Do it now. Fixes: 210f47840d ("hw/arm/bcm2836: Hardcode correct CPU type") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200703200459.23294-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-03hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accessesPeter Maydell
Instead of using printf() for logging guest accesses to invalid register offsets in the pxa2xx PIC device, use the usual qemu_log_mask(LOG_GUEST_ERROR,...). This was the only user of the REG_FMT macro in pxa.h, so we can remove that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200628142429.17111-16-peter.maydell@linaro.org
2020-07-03hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accessesPeter Maydell
Instead of logging guest accesses to invalid register offsets in this device using zaurus_printf() (which just prints to stderr), use the usual qemu_log_mask(LOG_GUEST_ERROR,...). Since this was the only use of the zaurus_printf() macro outside spitz.c, we can move the definition of that macro from sharpsl.h to spitz.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200628142429.17111-14-peter.maydell@linaro.org
2020-07-03hw/arm/virt-acpi-build: Only expose flash on older machine typesAndrew Jones
The flash device is exclusively for the host-controlled firmware, so we should not expose it to the OS. Exposing it risks the OS messing with it, which could break firmware runtime services and surprise the OS when all its changes disappear after reboot. As firmware needs the device and uses DT, we leave the device exposed there. It's up to firmware to remove the nodes from DT before sending it on to the OS. However, there's no need to force firmware to remove tables from ACPI (which it doesn't know how to do anyway), so we simply don't add the tables in the first place. But, as we've been adding the tables for quite some time and don't want to change the default hardware exposed to versioned machines, then we only stop exposing the flash device tables for 5.1 and later machine types. Suggested-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Suggested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-id: 20200629140938.17566-4-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-03hw/arm/virt: Let the virtio-iommu bypass MSIsEric Auger
At the moment the virtio-iommu translates MSI transactions. This behavior is inherited from ARM SMMU. The virt machine code knows where the guest MSI doorbells are so we can easily declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that setting the guest will not map MSIs through the IOMMU and those transactions will be simply bypassed. Depending on which MSI controller is in use (ITS or GICV2M), we declare either: - the ITS interrupt translation space (ITS_base + 0x10000), containing the GITS_TRANSLATOR or - The GICV2M single frame, containing the MSI_SETSP_NS register. Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 20200629070404.10969-6-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-03Add the ability to select a different PHY for each i.MX6UL FEC interfaceJean-Christophe Dubois
Add properties to the i.MX6UL processor to be able to select a particular PHY on the MDIO bus for each FEC device. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-26hw/arm/aspeed: QOM'ify AspeedMachineStatePhilippe Mathieu-Daudé
AspeedMachineState seems crippled. We use incorrectly 2 different structures to do the same thing. Merge them altogether: - Move AspeedMachine fields to AspeedMachineState - AspeedMachineState is now QOM - Remove unused AspeedMachine structure Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200623072132.2868-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-26hw/arm/aspeed: Rename AspeedBoardState as AspeedMachineStatePhilippe Mathieu-Daudé
To have a more consistent naming, rename AspeedBoardState as AspeedMachineState. Suggested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200623072132.2868-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-15arm/aspeed: Rework NIC attachmentCédric Le Goater
The number of MACs supported by an Aspeed SoC is defined by "macs_num" under the SoC model, that is two for the AST2400 and AST2500 and four for the AST2600. The model initializes the maximum number of supported MACs but the number of realized devices is capped by the number of network device back-ends defined on the command line. This can leave unrealized devices hanging around in the QOM composition tree. To get virtual hardware that matches the physical hardware, you have to pass exactly as many -nic options as there are MACs, and some of them must be -nic none: * Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and witherspoon-bmc: two -nic, and the second one must be -nic none. * Machine ast2600-evb: four -nic, the first one must be -nic none. * Machine tacoma-bmc: four nic, the first two and the last one must be -nic none. Modify the machine initialization to define which MACs are attached to a network device back-end using a bit-field property "macs-mask" and let the SoC realize all network devices. The default setting of "macs-mask" is "use MAC0" only, which works for all our AST2400 and AST2500 machines. The AST2600 machines have different configurations. The AST2600 EVB machine activates MAC1, MAC2 and MAC3 and the Tacoma BMC machine activates MAC2. Incompatible CLI change: -nic options now apply to *active* MACs: MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for all the others. The machines now always get all MACs as they should. Visible in "info qom-tree", here's the change for tacoma-bmc: /machine (tacoma-bmc-machine) /peripheral (container) /peripheral-anon (container) /soc (ast2600-a1) [...] /ftgmac100[0] (ftgmac100) /ftgmac100[0] (qemu:memory-region) /ftgmac100[1] (ftgmac100) + /ftgmac100[0] (qemu:memory-region) /ftgmac100[2] (ftgmac100) + /ftgmac100[0] (qemu:memory-region) /ftgmac100[3] (ftgmac100) + /ftgmac100[0] (qemu:memory-region) [...] /mii[0] (aspeed-mmi) /aspeed-mmi[0] (qemu:memory-region) /mii[1] (aspeed-mmi) + /aspeed-mmi[0] (qemu:memory-region) /mii[2] (aspeed-mmi) + /aspeed-mmi[0] (qemu:memory-region) /mii[3] (aspeed-mmi) + /aspeed-mmi[0] (qemu:memory-region) Also visible in "info qtree"; here's the change for tacoma-bmc: dev: ftgmac100, id "" gpio-out "sysbus-irq" 1 aspeed = true - mac = "52:54:00:12:34:56" - netdev = "hub0port0" + mac = "52:54:00:12:34:57" + netdev = "" mmio 000000001e660000/0000000000002000 dev: ftgmac100, id "" - aspeed = false - mac = "00:00:00:00:00:00" + gpio-out "sysbus-irq" 1 + aspeed = true + mac = "52:54:00:12:34:58" netdev = "" + mmio 000000001e680000/0000000000002000 dev: ftgmac100, id "" - aspeed = false - mac = "00:00:00:00:00:00" - netdev = "" + gpio-out "sysbus-irq" 1 + aspeed = true + mac = "52:54:00:12:34:56" + netdev = "hub0port0" + mmio 000000001e670000/0000000000002000 dev: ftgmac100, id "" - aspeed = false - mac = "00:00:00:00:00:00" + gpio-out "sysbus-irq" 1 + aspeed = true + mac = "52:54:00:12:34:59" netdev = "" + mmio 000000001e690000/0000000000002000 [...] dev: aspeed-mmi, id "" mmio 000000001e650000/0000000000000008 dev: aspeed-mmi, id "" + mmio 000000001e650008/0000000000000008 dev: aspeed-mmi, id "" + mmio 000000001e650010/0000000000000008 dev: aspeed-mmi, id "" + mmio 000000001e650018/0000000000000008 Inactive MACs will have no peer and QEMU may warn the user with : qemu-system-arm: warning: nic ftgmac100.0 has no peer qemu-system-arm: warning: nic ftgmac100.1 has no peer qemu-system-arm: warning: nic ftgmac100.3 has no peer Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Joel Stanley <joel@jms.id.au> [Commit message expanded] Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-15arm/aspeed: Compute the number of CPUs from the SoC definitionCédric Le Goater
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU per machine") was a convient change during bringup but the Aspeed SoCs have a fixed number of CPUs : one for the AST2400 and AST2500, and two for the AST2600. When the number of CPUs configured with -smp is less than the SoC's fixed number, the "unconfigured" CPUs are left unrealized. This can happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed number is 2. To get virtual hardware that matches the physical hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2). We normally reject -smp cpus=N when N exceeds the machine's limit. Except we ignore cpus=2 (and only cpus=2) with a warning for machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and witherspoon-bmc. Remove the "num-cpu" property from the SoC state and use the fixed number of CPUs defined in the SoC class instead. Compute the default, min, max number of CPUs of the machine directly from the SoC class definition. Machines ast2600-evb and tacoma-bmc now always get their second CPU as they should. Visible in "info qom-tree"; here's the change for ast2600-evb: /machine (ast2600-evb-machine) /peripheral (container) /peripheral-anon (container) /soc (ast2600-a1) /a7mpcore (a15mpcore_priv) /a15mp-priv-container[0] (qemu:memory-region) /gic (arm_gic) /gic_cpu[0] (qemu:memory-region) /gic_cpu[1] (qemu:memory-region) + /gic_cpu[2] (qemu:memory-region) /gic_dist[0] (qemu:memory-region) /gic_vcpu[0] (qemu:memory-region) /gic_viface[0] (qemu:memory-region) /gic_viface[1] (qemu:memory-region) + /gic_viface[2] (qemu:memory-region) /unnamed-gpio-in[0] (irq) [...] + /unnamed-gpio-in[160] (irq) [same for 161 to 190...] + /unnamed-gpio-in[191] (irq) Also visible in "info qtree"; here's the change for ast2600-evb: bus: main-system-bus type System dev: a15mpcore_priv, id "" gpio-in "" 128 - gpio-out "sysbus-irq" 5 - num-cpu = 1 (0x1) + gpio-out "sysbus-irq" 10 + num-cpu = 2 (0x2) num-irq = 160 (0xa0) mmio 0000000040460000/0000000000008000 dev: arm_gic, id "" - gpio-in "" 160 - num-cpu = 1 (0x1) + gpio-in "" 192 + num-cpu = 2 (0x2) num-irq = 160 (0xa0) revision = 2 (0x2) has-security-extensions = true has-virtualization-extensions = true num-priority-bits = 8 (0x8) mmio ffffffffffffffff/0000000000001000 mmio ffffffffffffffff/0000000000002000 mmio ffffffffffffffff/0000000000001000 mmio ffffffffffffffff/0000000000002000 mmio ffffffffffffffff/0000000000000100 + mmio ffffffffffffffff/0000000000000100 + mmio ffffffffffffffff/0000000000000200 mmio ffffffffffffffff/0000000000000200 The other machines now reject -smp cpus=2 just like -smp cpus=3 and up. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Commit message expanded] Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-05wire in the dwc-hsotg (dwc2) USB host controller emulationPaul Zimmerman
Wire the dwc-hsotg (dwc2) emulation into Qemu Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org> Message-id: 20200520235349.21215-7-pauldzim@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-05raspi: add BCM2835 SOC MPHI emulationPaul Zimmerman
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface) emulation. It is very basic, only providing the FIQ interrupt needed to allow the dwc-otg USB host controller driver in the Raspbian kernel to function. Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200520235349.21215-2-pauldzim@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-21hw/arm/fsl-imx7: Connect watchdog interruptsGuenter Roeck
i.MX7 supports watchdog pretimeout interupts. With this commit, the watchdog in mcimx7d-sabre is fully operational, including pretimeout support. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200517162135.110364-9-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-21hw/arm/fsl-imx7: Instantiate various unimplemented devicesGuenter Roeck
Instantiating PWM, CAN, CAAM, and OCOTP devices is necessary to avoid crashes when booting mainline Linux. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200517162135.110364-8-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-21hw/arm/fsl-imx31: Wire up watchdogGuenter Roeck
With this patch, the watchdog on i.MX31 emulations is fully operational. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200517162135.110364-5-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-21hw/arm/fsl-imx25: Wire up watchdogGuenter Roeck
With this commit, the watchdog on imx25-pdk is fully operational, including pretimeout support. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200517162135.110364-4-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-21hw: Move i.MX watchdog driver to hw/watchdogGuenter Roeck
In preparation for a full implementation, move i.MX watchdog driver from hw/misc to hw/watchdog. While at it, add the watchdog files to MAINTAINERS. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200517162135.110364-2-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-14hw/arm/virt: Introduce a RAS machine optionDongjiu Geng
RAS Virtualization feature is not supported now, so add a RAS machine option and disable it by default. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200512030609.19593-3-gengdongjiu@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definitionPhilippe Mathieu-Daudé
On the NRF51 series, all peripherals have a fixed I/O size of 4KiB. Define NRF51_PERIPHERAL_SIZE and use it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200504072822.18799-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-04hw/arm/virt: Add nvdimm hot-plug infrastructureKwangwoo Lee
This adds support to init nvdimm acpi state and build nvdimm acpi tables. Please note nvdimm_support is not yet enabled. Signed-off-by: Kwangwoo Lee <kwangwoo.lee@sk.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20200421125934.14952-4-shameerali.kolothum.thodi@huawei.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-05-04hw/arm: versal: Add support for the RTCEdgar E. Iglesias
hw/arm: versal: Add support for the RTC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20200427181649.26851-10-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-04hw/arm: versal: Add support for SDEdgar E. Iglesias
Add support for SD. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20200427181649.26851-9-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-04hw/arm: versal: Embed the APUs into the SoC typeEdgar E. Iglesias
Embed the APUs into the SoC type. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20200427181649.26851-8-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-04hw/arm: versal: Embed the ADMAs into the SoC typeEdgar E. Iglesias
Embed the ADMAs into the SoC type. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20200427181649.26851-7-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-04hw/arm: versal: Embed the GEMs into the SoC typeEdgar E. Iglesias
Embed the GEMs into the SoC type. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-04hw/arm: versal: Embed the UARTs into the SoC typeEdgar E. Iglesias
Embed the UARTs into the SoC type. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20200427181649.26851-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-04-30msf2: Add EMAC block to SmartFusion2 SoCSubbaraya Sundeep
With SmartFusion2 Ethernet MAC model in place this patch adds the same to SoC. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1587048891-30493-3-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-29acpi: add acpi=OnOffAuto machine property to x86 and arm virtGerd Hoffmann
Remove the global acpi_enabled bool and replace it with an acpi OnOffAuto machine property. qemu throws an error now if you use -no-acpi while the machine type you are using doesn't support acpi in the first place. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20200320100136.11717-1-kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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