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2018-01-26xlnx-zynqmp: Connect the IPI device to the ZynqMP SoCAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22Replace all occurances of __FUNCTION__ with __func__Alistair Francis
Replace all occurs of __FUNCTION__ except for the check in checkpatch with the non GCC specific __func__. One line in hcd-musb.c was manually tweaked to pass checkpatch. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> [THH: Removed hunks related to pxa2xx_mmci.c (fixed already)] Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-01-11imx_fec: Reserve full FSL_IMX25_FEC_SIZE page for the register fileAndrey Smirnov
Some i.MX SoCs (e.g. i.MX7) have FEC registers going as far as offset 0x614, so to avoid getting aborts when accessing those on QEMU, extend the register file to cover FSL_IMX25_FEC_SIZE(16K) of address space instead of just 1K. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-12-13xlnx-zcu102: Add support for the ZynqMP QSPIFrancisco Iglesias
Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20171126231634.9531-14-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-12arm: fix armv7m_init() declaration to match definitionIgor Mammedov
s/cpu_model/cpu_type/ that has been forgotten during conversion (ba1ba5cc), while touching the line also fixup alignment. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1507710805-221721-1-git-send-email-imammedo@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-23Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* Speed up AddressSpaceDispatch creation (Alexey) * Fix kvm.c assert (David) * Memory fixes and further speedup (me) * Persistent reservation manager infrastructure (me) * virtio-serial: add enable_backend callback (Pavel) * chardev GMainContext fixes (Peter) # gpg: Signature made Fri 22 Sep 2017 20:07:33 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (32 commits) chardev: remove context in chr_update_read_handler chardev: use per-dev context for io_add_watch_poll chardev: add Chardev.gcontext field chardev: new qemu_chr_be_update_read_handlers() scsi: add persistent reservation manager using qemu-pr-helper scsi: add multipath support to qemu-pr-helper scsi: build qemu-pr-helper scsi, file-posix: add support for persistent reservation management memory: Share special empty FlatView memory: seek FlatView sharing candidates among children subregions memory: trace FlatView creation and destruction memory: Create FlatView directly memory: Get rid of address_space_init_shareable memory: Rework "info mtree" to print flat views and dispatch trees memory: Do not allocate FlatView in address_space_init memory: Share FlatView's and dispatch trees between address spaces memory: Move address_space_update_ioeventfds memory: Alloc dispatch tree where topology is generared memory: Store physical root MR in FlatView memory: Rename mem_begin/mem_commit/mem_add helpers ... # Conflicts: # configure
2017-09-22memory: Get rid of address_space_init_shareableAlexey Kardashevskiy
Since FlatViews are shared now and ASes not, this gets rid of address_space_init_shareable(). This should cause no behavioural change. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20170921085110.25598-17-aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-09-21msf2: Add Smartfusion2 SoCSubbaraya Sundeep
Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-5-f4bug@amsat.org [PMD: drop cpu_model to directly use cpu type, check m3clk non null] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-19arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directlyIgor Mammedov
there are 2 use cases to deal with: 1: fixed CPU models per board/soc 2: boards with user configurable cpu_model and fallback to default cpu_model if user hasn't specified one explicitly For the 1st drop intermediate cpu_model parsing and use const cpu type directly, which replaces: typename = object_class_get_name( cpu_class_by_name(TYPE_ARM_CPU, cpu_model)) object_new(typename) with object_new(FOO_CPU_TYPE_NAME) or cpu_generic_init(BASE_CPU_TYPE, "my cpu model") with cpu_create(FOO_CPU_TYPE_NAME) as result 1st use case doesn't have to invoke not necessary translation and not needed code is removed. For the 2nd 1: set default cpu type with MachineClass::default_cpu_type and 2: use generic cpu_model parsing that done before machine_init() is run and: 2.1: drop custom cpu_model parsing where pattern is: typename = object_class_get_name( cpu_class_by_name(TYPE_ARM_CPU, cpu_model)) [parse_features(typename, cpu_model, &err) ] 2.2: or replace cpu_generic_init() which does what 2.1 does + create_cpu(typename) with just create_cpu(machine->cpu_type) as result cpu_name -> cpu_type translation is done using generic machine code one including parsing optional features if supported/present (removes a bunch of duplicated cpu_model parsing code) and default cpu type is defined in an uniform way within machine_class_init callbacks instead of adhoc places in boadr's machine_init code. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1505318697-77161-6-git-send-email-imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-14xlnx-zcu102: Add a machine level virtualization propertyAlistair Francis
Add a machine level virtualization property. This defaults to false and can be set to true using this machine command line argument: -machine xlnx-zcu102,virtualization=on This follows what the ARM virt machine does. This property only applies to the ZCU102 machine. The EP108 machine does not have this property. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-04armv7m_nvic.h: Move from include/hw/arm to include/hw/intcPeter Maydell
The armv7m_nvic.h header file was accidentally placed in include/hw/arm; move it to include/hw/intc to match where its corresponding .c file lives. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1501692241-23310-15-git-send-email-peter.maydell@linaro.org
2017-07-11aspeed: Register all watchdogsJoel Stanley
The ast2400 contains two and the ast2500 contains three watchdogs. Add this information to the AspeedSoCInfo and realise the correct number of watchdogs for that each SoC type. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-13hw/arm/exynos: Move DRAM initialization next boardsKrzysztof Kozlowski
Before QOM-ifying the Exynos4 SoC model, move the DRAM initialization from exynos4210.c to exynos4_boards.c because DRAM is board specific, not SoC. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-25aspeed: add a FTGMAC100 nicCédric Le Goater
There is a second NIC but we do not use it for the moment. We use the 'aspeed' property to tune the definition of the end of ring buffer bit for the Aspeed SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-02-28bcm2835: add sdhost and gpio controllersClement Deschamps
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform. For supporting the SD controller selection (alternate function of GPIOs 48-53), the bcm2835_gpio now exposes an sdbus. It also has a link to both the sdbus of sdhci and sdhost controllers, and the card is reparented from one bus to another when the alternate function of GPIOs 48-53 is modified. Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1488293711-14195-5-git-send-email-peter.maydell@linaro.org Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28stm32f205: Create armv7m object without using armv7m_init()Peter Maydell
Switch the stm32f205 SoC to create the armv7m object directly rather than via the armv7m_init() wrapper. This fits better with the SoC model's very QOMified design. In particular this means we can push loading the guest image out to the top level board code where it belongs, rather than the SoC object having a QOM property for the filename to load. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-11-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Split systick out from NVICPeter Maydell
The SysTick timer isn't really part of the NVIC proper; we just modelled it that way back when we couldn't easily have devices that only occupied a small chunk of a memory region. Split it out into its own device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Make bitband device take the address space to accessPeter Maydell
Instead of the bitband device doing a cpu_physical_memory_read/write, make it take a MemoryRegion which specifies where it should be accessing, and use address_space_read/write to access the corresponding AddressSpace. Since this entails pretty much a rewrite, convert away from old_mmio in the process. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Make ARMv7M object take memory region linkPeter Maydell
Make the ARMv7M object take a memory region link which it uses to wire up the bitband rather than having them always put themselves in the system address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-6-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: QOMify the armv7m containerPeter Maydell
Create a proper QOM object for the armv7m container, which holds the CPU, the NVIC and the bitband regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Move NVICState struct definition into headerPeter Maydell
Move the NVICState struct definition into a header, so we can embed it into other QOM objects like SoCs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Abstract out the "load kernel" codePeter Maydell
Abstract the "load kernel" code out of armv7m_init() into its own function. This includes the registration of the CPU reset function, to parallel how we handle this for A profile cores. We make the function public so that boards which choose to directly instantiate an ARMv7M device object can call it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
2017-02-28hw/arm/virt: Add a user option to disallow ITS instantiationEric Auger
In 2.9 ITS will block save/restore and migration use cases. As such, let's introduce a user option that allows to turn its instantiation off, along with GICv3. With the "its" option turned false, migration will be possible, obviously at the expense of MSI support (with GICv3). Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1487681108-14452-1-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28target-arm: Implement BCM2835 hardware RNGMarcin Chojnacki
Recent vanilla Raspberry Pi kernels started to make use of the hardware random number generator in BCM2835 SoC. As a result, those kernels wouldn't work anymore under QEMU but rather just freeze during the boot process. This patch implements a trivial BCM2835 compatible RNG, and adds it as a peripheral to BCM2835 platform, which allows to boot a vanilla Raspberry Pi kernel under Qemu. Changes since v1: * Prevented guest from writing [31..20] bits in rng_status * Removed redundant minimum_version_id_old * Added field entries for the state * Changed realize function to reset Signed-off-by: Marcin Chojnacki <marcinch7@gmail.com> Message-id: 20170210210857.47893-1-marcinch7@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-07aspeed: add a watchdog controllerCédric Le Goater
This enables reboot of a guest from U-Boot and Linux. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 1485452251-1593-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27char: rename CharDriverState ChardevMarc-André Lureau
Pick a uniform chardev type name. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-20hw/arm/virt: Add board property to enable EL2Peter Maydell
Add a board level property to the virt board which will enable EL2 on the CPU if the user asks for it. The default is not to provide EL2. If EL2 is enabled then we will use SMC as our PSCI conduit, and report the virtualization support in the GICv3 device tree node and the ACPI tables. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-19-git-send-email-peter.maydell@linaro.org
2017-01-20hw/arm/virt: Support using SMC for PSCIPeter Maydell
If we are giving the guest a CPU with EL2, it is likely to want to use the HVC instruction itself, for instance for providing PSCI to inner guest VMs. This makes using HVC as the PSCI conduit for the outer QEMU a bad idea. We will want to use SMC instead is this case: this makes sense because QEMU's PSCI implementation is effectively an emulation of functionality provided by EL3 firmware. Add code to support selecting the PSCI conduit to use, rather than hardcoding use of HVC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1483977924-14522-15-git-send-email-peter.maydell@linaro.org
2017-01-20hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPUPeter Maydell
Wire the new VIRQ, VFIQ and maintenance interrupt lines from the GIC to each CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-5-git-send-email-peter.maydell@linaro.org
2017-01-09hw/arm/virt: remove VirtGuestInfoAndrew Jones
by moving VirtGuestInfo.fw_cfg to VirtMachineState. This is the mach-virt equivalent of "pc: Move PcGuestInfo.fw_cfg to PCMachineState" and "pc: Eliminate PcGuestInfo struct" combined. Signed-off-by: Andrew Jones <drjones@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-14-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: remove redundant members from VirtGuestInfoAndrew Jones
Now that we pass VirtMachineState, and guest-info is just part of that state, we can remove all the redundant members and access the VirtMachineState directly. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-12-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: pass VirtMachineState instead of VirtGuestInfoAndrew Jones
Only two functions take VirtGuestInfo parameters. Now that guest-info is part of VirtMachineState, and VirtMachineState is defined in the virt header, pass that instead. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-11-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: move VirtMachineState/Class to virt.hAndrew Jones
In preparation to share more Virt machine state than just guest-info with other mach-virt source files, move the State and Class structures to virt.h Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-10-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: remove include/hw/arm/virt-acpi-build.hAndrew Jones
include/hw/arm/virt-acpi-build.h is only used for VirtGuestInfo, which doesn't even necessarily have to be ACPI specific. Move VirtGuestInfo to include/hw/arm/virt.h, allowing us to remove include/hw/arm/virt-acpi-build.h, and to prepare for even more code motion. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-9-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: eliminate struct VirtGuestInfoStateAndrew Jones
Instead of allocating a new struct just for VirtGuestInfo and the machine_done Notifier, place them inside VirtMachineState. This is the mach-virt equivalent of "pc: Eliminate struct PcGuestInfoState" Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-8-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriatelyAndrew Jones
Also move the enabled flag definition from mach-virt code to acpi common. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20170102200153.28864-3-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: add a memory region for SRAMCédric Le Goater
The size of the SRAM depends on the SoC model, so use a per-soc definition when creating the region. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-9-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: QOMify the CPU object and attach it to the SoCCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-10-17hw/arm/virt: no ITS on older machine typesAndrew Jones
We should avoid exposing new hardware (through DT and ACPI) on older machine types. This patch keeps 2.7 and older from changing, despite the introduction of ITS support for 2.8. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 1476117341-32690-3-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-17aspeed: add support for the AST2500 SoC SMC controllersCédric Le Goater
The SMC controllers on the Aspeed AST2500 SoC are very similar to the ones found on the AST2400. The differences are on the number of supported flash modules and their default mappings in the SoC address space. The Aspeed AST2500 has one SPI controller for the BMC firmware and two for the host firmware. All controllers have now the same set of registers compatible with the AST2400 FMC controller and the legacy 'SMC' controller is fully gone. We keep the FMC object to act as the BMC SPI controller and add a new SPI controller for the host. We also have to introduce new type names to handle the differences in the flash modules memory mappping. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-5-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-17aspeed: extend the number of host SPI controllersCédric Le Goater
The AST2500 SoC has two. Let's prepare ground for the next changes which will add the required definitions for the second host SPI controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-17aspeed: rename the smc object to fmcCédric Le Goater
The Aspeed SoC has three different types of SMC (Static Memory Controller) controllers: the SMC (legacy), the FMC (the new one) and the SPI for the host PNOR. The FMC and the SPI models are now converging on the AST2500 SoC and the SMC, which was still available on the AST2400 SoC, was removed. The Aspeed SoC does not provide support for the legacy SMC controller. So, let's rename the 'smc' object to 'fmc' to clarify its nature. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F205: Connect the SPI devicesAlistair Francis
Connect the SPI devices to the STM32F205 SoC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: d05849120420f8db0d9aa053bd23134c33cd9180.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F205: Connect the ADC devicesAlistair Francis
Connect the ADC devices to the STM32F205 SoC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Message-id: 6214eda399da7b47014f6f895be25323d52dbc9e.1474742262.git.alistair@alistair23.me Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22aspeed-soc: provide a framework to add new SoCsCédric Le Goater
Let's define an object class for each Aspeed SoC we support. A AspeedSoCInfo struct gathers the SoC specifications which can later be used by an instance of the class or by a board using the SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1473438177-26079-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22ast2400: replace ast2400 with aspeed_socCédric Le Goater
This is a name replacement to prepare ground for other SoCs. Let's also remove the AST2400_SMC_BASE definition from the address space mappings, as it is not used. This controller was removed from the Aspeed SoC AST2500, so this provides us a better common base for the address space mapping on both SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22ast2400: rename the Aspeed SoC files to aspeed_socCédric Le Goater
Let's prepare for new Aspeed SoCs and rename the ast2400 file to a more generic one. There are no changes in the code apart from the header file include. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-15Remove unused function declarationsLadi Prosek
Unused function declarations were found using a simple gcc plugin and manually verified by grepping the sources. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2016-09-06ast2400: add a memory controller device modelCédric Le Goater
The uboot in the previous release of the SDK was using a hardcoded value for memory size. This is not true anymore, the value is now retrieved from the memory controller. Below is a model for this device, only supporting unlock and configuration. Without it, we endup running a guest with 64MB, which is a bit low nowdays. It uses a 'silicon-rev' property and ram_size to build a default value. Some bits should be linked to SCU strapping registers but it seems a bit complex to add for the current need. The model is ready for the AST2500 SOC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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