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2014-05-15Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-s390-20140515' into ↵Peter Maydell
staging tcg/s390 updates # gpg: Signature made Thu 15 May 2014 17:24:40 BST using RSA key ID 4DD0279B # gpg: Can't check signature: public key not found * remotes/rth/tags/pull-tcg-s390-20140515: tcg-s390: Implement direct chaining of TBs tcg-s390: Don't force -march=z990 tcg-s390: Improve setcond tcg-s390: Allow immediate operands to add2 and sub2 tcg-s390: Implement tcg_register_jit tcg-s390: Use more risbg in the tlb sequence tcg-s390: Move ldst helpers out of line tcg-s390: Convert to new ldst opcodes tcg-s390: Integrate endianness into TCGMemOp tcg-s390: Convert to TCGMemOp tcg-s390: Fix off-by-one in wraparound andi Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-15tcg-s390: Implement direct chaining of TBsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-15Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell
* remotes/kvm/uq/master: pc: port 92 reset requires a low->high transition cpu: make CPU_INTERRUPT_RESET available on all targets apic: do not accept SIPI on the bootstrap processor target-i386: preserve FPU and MSR state on INIT target-i386: fix set of registers zeroed on reset kvm: forward INIT signals coming from the chipset kvm: reset state from the CPU's reset method target-i386: the x86 CPL is stored in CS.selector - auto update hflags accordingly. target-i386: set eflags prior to calling cpu_x86_load_seg_cache() in seg_helper.c target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.c pci-assign: limit # of msix vectors pci-assign: Fix a bug when map MSI-X table memory failed kvm: make one_reg helpers available for everyone target-i386: Remove unused data from local array Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-13exec-all.h: Use stl_le_p instead of stl_p patching x86Richard Henderson
We got the wrong version of stl_p, the one that bswaps as appropriate for the target. Since x86 is always little-endian, the "_le_" routine will resolve to what we want. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-13cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini
On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-12tcg: Define tcg_insn_unit for code pointersRichard Henderson
To be defined by the tcg backend based on the elemental unit of the ISA. During the transition, allow TCG_TARGET_INSN_UNIT_SIZE to be undefined, which allows us to default tcg_insn_unit to the current uint8_t. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12exec-all.h: Use stl_p to avoid undefined behaviour patching x86 jumpsPeter Maydell
The code which patches x86 jump instructions assumes it can do an unaligned write of a uint32_t. This is actually safe on x86, but it's still undefined behaviour. We have infrastructure for doing efficient unaligned accesses which doesn't engage in undefined behaviour, so use it. This is technically fractionally less efficient, at least with gcc 4.6; instead of one instruction: 7b2: 89 3e mov %edi,(%rsi) we get an extra spurious store to the stack slot: 7b2: 89 7c 24 64 mov %edi,0x64(%rsp) 7b6: 89 3e mov %edi,(%rsi) Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-07docs/memory.txt: Fix document on MMIO operationsFam Zheng
.impl.valid should be .impl.unaligned and the description needs some fixes. .old_portio is removed since commit b40acf99b (ioport: Switch dispatching to memory core layer). Signed-off-by: Fam Zheng <famz@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-04-28tcg: Fix missed pointer size != TCG_TARGET_REG_BITS changesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell
Implement the DC ZVA instruction, which clears a block of memory. The fast path obtains a pointer to the underlying RAM via the TCG TLB data structure so we can do a direct memset(), with fallback to a simple byte-store loop in the slow path. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-03-17exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoderPeter Maydell
The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change memory_region_section_get_iotlb() argument to CPUStateAndreas Färber
It no longer needs CPUArchState since moving watchpoints to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cputlb: Change tlb_unprotect_code_phys() argument to CPUStateAndreas Färber
Note that the argument is unused. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu-exec: Change cpu_resume_from_signal() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_breakpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber
Use CPUState. Allows to clean up CPUArchState in gdbstub. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber
Use CPUState. This lets us drop a few local env usages. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13translate-all: Change tb_flush_jmp_cache() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13translate-all: Change tb_gen_code() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13translate-all: Change cpu_io_recompile() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber
This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber
Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move opaque field from CPU_COMMON to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move jmp_env field from CPU_COMMON to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move tb_jmp_cache field from CPU_COMMON to CPUStateAndreas Färber
Clear it on reset. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move icount_decr field from CPU_COMMON to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move icount_extra field from CPU_COMMON to CPUStateAndreas Färber
Reset it. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move can_do_io field from CPU_COMMON to CPUStateAndreas Färber
Rename can_do_io() to cpu_can_do_io() and change argument to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move mem_io_{pc,vaddr} fields from CPU_COMMON to CPUStateAndreas Färber
Reset them. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20140310' into staging target-arm queue: * implement WFE as yield (improves performance with emulated SMP) * fixes to avoid undefined behaviour shifting left into sign bit * libvixl format string fixes for 32 bit hosts * fix build error when intptr_t and tcg_target_long are different sizes (eg x32) * implement PMCCNTR register * fix incorrect setting of E bit in CPSR (broke booting under KVM on ARM) # gpg: Signature made Mon 10 Mar 2014 15:05:25 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140310: target-arm: Implement WFE as a yield operation hw/arm/musicpal: Avoid shifting left into sign bit hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit hw/arm/omap1.c: Avoid shifting left into sign bit pxa2xx: Don't shift into sign bit libvixl: Fix format strings for several int64_t values target-arm: Fix intptr_t vs tcg_target_long target-arm: Implements the ARM PMCCNTR register target-arm: Fix incorrect setting of E bit in CPSR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-10target-arm: Implement WFE as a yield operationPeter Maydell
Implement WFE to yield our timeslice to the next CPU. This avoids slowdowns in multicore configurations caused by one core busy-waiting on a spinlock which can't possibly be unlocked until the other core has an opportunity to run. This speeds up my test case A15 dual-core boot by a factor of three (though it is still four or five times slower than a single-core boot). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393339545-22111-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Richard Henderson <rth@twiddle.net> Tested-by: Rob Herring <rob.herring@linaro.org>
2014-03-09memory_region_present: return false if address is not found in child ↵Igor Mammedov
MemoryRegion Windows XP shows COM2 port as non functional in "Device Manager" although no COM2 port backing device is present in QEMU. This regression is really due to 3bb28b7208b349e7a1b326e3c6ef9efac1d462bf? memory: Provide separate handling of unassigned io ports accesses That is caused by the fact that QEMU reports to OSPM that device is present by setting 5th bit in PII4XPM.pci_conf[0x67] register when COM2 doesn't exist. It happens due to memory_region_present(io_as, 0x2f8) returning false positive since 0x2f8 address eventually translates into catchall io_as address space. Fix memory_region_present(parent, addr) by returning true only if addr maps into a MemoryRegion within parent (excluding parent itself), to match its doc comment. While at it fix copy/paste error in memory_region_present() doc comment. Note: this is a temporary hack: we really need better handling for unassigned regions, we should avoid fallback regions since they are bad for performance (breaking radix tree assumption that the data structure is sparsely populated); for memory we need to fix this to implement PCI master abort properly, anyway. Cc: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-02-11exec: Make cpu_physical_memory_write_rom input an ASEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stb_phys input an AddressSpaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stw_*_phys input an AddressSpaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stl_phys_notdirty input an AddressSpaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stq_*_phys input an AddressSpaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make lduw_*_phys input an AddressSpaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11cpu: Add per-cpu address spaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11memory: Add MemoryListener to typedefs.hEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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