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2024-09-13hw/sensor/tmp105: Lower 4 bit of limit registers are always 0Guenter Roeck
Per datasheet, "HIGH AND LOW LIMIT REGISTERS", the lower 4 bit of the limit registers are unused and always report 0. The lower 4 bit should not be used for temperature comparisons, so mask the unused bits before storing the limits. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20240906154911.86803-6-philmd@linaro.org> [PMD: Update tests/qtest/ files] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/sensor/tmp105: OS (one-shot) bit in config register always returns 0Philippe Mathieu-Daudé
Per datasheet, "ONE-SHOT (OS)", the OS bit always returns 0 when reading the configuration register. Clear the ONE_SHOT bit in the WRITE path. Now than the READ path is simpler, we can also simplify tmp105_alarm_update(). Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20240906154911.86803-5-philmd@linaro.org>
2024-09-13hw/sensor/tmp105: Pass 'oneshot' argument to tmp105_alarm_update()Philippe Mathieu-Daudé
The next commit will clear the ONE_SHOT bit in the WRITE path (to keep the READ path trivial). As a preliminary step, pass the 'oneshot' value as argument to tmp105_alarm_update(). No logical change intended. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Message-Id: <20240906154911.86803-4-philmd@linaro.org>
2024-09-13hw/sensor/tmp105: Use registerfields APIPhilippe Mathieu-Daudé
To improve readability, use the registerfields API. Define the register bits with FIELD(), and use the FIELD_EX8() and FIELD_DP8() macros. Remove the abbreviations in comments. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Message-Id: <20240906154911.86803-3-philmd@linaro.org>
2024-09-13hw/sensor/tmp105: Coding style fixesGuenter Roeck
Coding style asks for no space between variable and "++". The next patch in this series will change one of those assignments. Instead of changing just one with that patch, change all of them for consistency. While at it, also fix other coding style problems reported by checkpatch. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20240906154911.86803-2-philmd@linaro.org>
2024-09-13hw/char/pl011: Rename RX FIFO methodsPhilippe Mathieu-Daudé
In preparation of having a TX FIFO, rename the RX FIFO methods. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240719181041.49545-12-philmd@linaro.org>
2024-09-13hw/char/pl011: Warn when using disabled transmitterPhilippe Mathieu-Daudé
We shouldn't transmit characters when the full UART or its transmitter is disabled. However we don't want to break the possibly incomplete "my first bare metal assembly program"s, so we choose to simply display a warning when this occurs. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240719181041.49545-9-philmd@linaro.org>
2024-09-13hw/char/pl011: Extract pl011_read_rxdata() from pl011_read()Philippe Mathieu-Daudé
To keep MemoryRegionOps read/write handlers with similar logic, factor pl011_read_txdata() out of pl011_read(), similar to what the previous commit did to pl011_write(). No functional change intended. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240719181041.49545-8-philmd@linaro.org>
2024-09-13hw/char/pl011: Extract pl011_write_txdata() from pl011_write()Philippe Mathieu-Daudé
When implementing FIFO, this code will become more complex. Start by factoring it out to a new pl011_write_txdata() function. No functional change intended. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240719181041.49545-7-philmd@linaro.org>
2024-09-13hw/char/pl011: Split RX/TX path of pl011_reset_fifo()Philippe Mathieu-Daudé
To be able to reset the RX or TX FIFO separately, split pl011_reset_fifo() in two. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240719181041.49545-6-philmd@linaro.org>
2024-09-13hw/char/pl011: Move pl011_loopback_enabled|tx() aroundPhilippe Mathieu-Daudé
We'll soon use pl011_loopback_enabled() and pl011_loopback_tx() from functions defined before their declarations. In order to avoid forward-declaring them, move them around. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20240719181041.49545-5-philmd@linaro.org>
2024-09-13hw/char/pl011: Move pl011_put_fifo() earlierPhilippe Mathieu-Daudé
Avoid forward-declaring pl011_put_fifo() by moving it earlier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20240719181041.49545-4-philmd@linaro.org>
2024-09-13hw/char/pl011: Remove unused 'readbuff' fieldPhilippe Mathieu-Daudé
Since its introduction in commit cdbdb648b7 ("ARM Versatile Platform Baseboard emulation.") PL011State::readbuff as never been used. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20240719181041.49545-3-philmd@linaro.org>
2024-09-13hw/timer: Remove TYPE_ETRAX_FS_TIMER devicePhilippe Mathieu-Daudé
We just removed the single machine using it (axis-dev88). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-12-philmd@linaro.org>
2024-09-13hw/dma: Remove ETRAX_FS DMA devicePhilippe Mathieu-Daudé
We just removed the single machine calling etraxfs_dmac_init() (the axis-dev88 machine). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-11-philmd@linaro.org>
2024-09-13hw/net: Remove TYPE_ETRAX_FS_ETH devicePhilippe Mathieu-Daudé
We just removed the single machine using it (axis-dev88). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-10-philmd@linaro.org>
2024-09-13hw/char: Remove TYPE_ETRAX_FS_SERIAL devicePhilippe Mathieu-Daudé
We just removed the single machine using it (axis-dev88). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-9-philmd@linaro.org>
2024-09-13hw/intc: Remove TYPE_ETRAX_FS_PIC devicePhilippe Mathieu-Daudé
We just removed the single machine using it (axis-dev88). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-8-philmd@linaro.org>
2024-09-13hw/cris: Remove image loader helperPhilippe Mathieu-Daudé
No more CRIS machine uses cris_load_image(), remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-7-philmd@linaro.org>
2024-09-13hw/cris: Remove the axis-dev88 machinePhilippe Mathieu-Daudé
This machine was deprecated for the v9.0 release in commit c7bbef4023 ("docs: mark CRIS support as deprecated"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-6-philmd@linaro.org>
2024-09-13hw/sh4: Remove sh7750_register_io_device() helperPhilippe Mathieu-Daudé
sh7750_register_io_device() was only used by the TC58128 NAND EEPROM which has been removed in the previous commit. Remove it as unused code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-ID: <20240903153959.18392-4-philmd@linaro.org>
2024-09-13hw/block: Remove TC58128 NAND EEPROMPhilippe Mathieu-Daudé
The TC58128 NAND EEPROM is not user creatable and needs to be instanciated in the code via tc58128_init(). Only the SHIX machine was using it, and it was removed in the previous commit. Since the TC58128 has no more users, remove it too. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240903153959.18392-3-philmd@linaro.org>
2024-09-13hw/sh4: Remove the deprecated SHIX machinePhilippe Mathieu-Daudé
The SHIX machine is deprecated since v9.0 (commit 322b038c94 "target/sh4: Deprecate the shix machine"). Time to remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-ID: <20240903153959.18392-2-philmd@linaro.org>
2024-09-13hw/intc/loongson_ipi: Remove unused headersPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Tested-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20240718133312.10324-19-philmd@linaro.org>
2024-09-13hw/pci-host/designware: Add 'host_mem' variable for clarityPhilippe Mathieu-Daudé
designware_pcie_root_realize() uses get_system_memory() as the "host side memory region", as opposed to the "PCI side" one. Introduce the 'host_mem' variable for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20231012121857.31873-4-philmd@linaro.org>
2024-09-13hw/pci-host/designware: Declare CPU QOM types using DEFINE_TYPES() macroPhilippe Mathieu-Daudé
When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Remove a pointless structure declaration in "designware.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20231012121857.31873-2-philmd@linaro.org>
2024-09-13hw/intc/arm_gic: fix spurious level triggered interruptsJan Klötzke
On GICv2 and later, level triggered interrupts are pending when either the interrupt line is asserted or the interrupt was made pending by a GICD_ISPENDRn write. Making a level triggered interrupt pending by software persists until either the interrupt is acknowledged or cleared by writing GICD_ICPENDRn. As long as the interrupt line is asserted, the interrupt is pending in any case. This logic is transparently implemented in gic_test_pending() for GICv1 and GICv2. The function combines the "pending" irq_state flag (used for edge triggered interrupts and software requests) and the line status (tracked in the "level" field). However, we also incorrectly set the pending flag on a guest write to GICD_ISENABLERn if the line of a level triggered interrupt was asserted. This keeps the interrupt pending even if the line is de-asserted after some time. This incorrect logic is a leftover of the initial 11MPCore GIC implementation. That handles things slightly differently to the architected GICv1 and GICv2. The 11MPCore TRM does not give a lot of detail on the corner cases of its GIC's behaviour, and historically we have not wanted to investigate exactly what it does in reality, so QEMU's GIC model takes the approach of "retain our existing behaviour for 11MPCore, and implement the architectural standard for later GIC revisions". On that basis, commit 8d999995e45c10 in 2013 is where we added the "level-triggered interrupt with the line asserted" handling to gic_test_pending(), and we deliberately kept the old behaviour of gic_test_pending() for REV_11MPCORE. That commit should have added the "only if 11MPCore" condition to the setting of the pending bit on writes to GICD_ISENABLERn, but forgot it. Add the missing "if REV_11MPCORE" condition, so that our behaviour on GICv1 and GICv2 matches the GIC architecture requirements. Cc: qemu-stable@nongnu.org Fixes: 8d999995e45c10 ("arm_gic: Fix GIC pending behavior") Signed-off-by: Jan Klötzke <jan.kloetzke@kernkonzept.com> Message-id: 20240911114826.3558302-1-jan.kloetzke@kernkonzept.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: expanded comment a little and converted to coding-style form; expanded commit message with the historical backstory] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/net/can/xlnx-versal-canfd: Fix FIFO issuesDoug Brown
The read index should not be changed when storing a new message into the RX or TX FIFO. Changing it at this point will cause the reader to get out of sync. The wrapping of the read index is already handled by the pre-write functions for the FIFO status registers anyway. Additionally, the calculation for wrapping the store index was off by one, which caused new messages to be written to the wrong location in the FIFO. This caused incorrect messages to be delivered. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20240827034927.66659-8-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/net/can/xlnx-versal-canfd: Simplify DLC conversionsDoug Brown
Use QEMU's helper functions can_dlc2len() and can_len2dlc() for translating between the raw DLC value and the SocketCAN length value. This also has the side effect of correctly handling received CAN FD frames with a DLC of 0-8, which was broken previously. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20240827034927.66659-7-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/net/can/xlnx-versal-canfd: Fix byte orderingDoug Brown
The endianness of the CAN data was backwards in each group of 4 bytes. For example, the following data: 00 11 22 33 44 55 66 77 was showing up like this: 33 22 11 00 77 66 55 44 Fix both the TX and RX code to put the data in the correct order. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Message-id: 20240827034927.66659-6-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/net/can/xlnx-versal-canfd: Handle flags correctlyDoug Brown
Add support for QEMU_CAN_FRMF_ESI and QEMU_CAN_FRMF_BRS flags, and ensure frame->flags is always initialized to 0. Note that the Xilinx IP core doesn't allow manually setting the ESI bit during transmits, so it's only implemented for the receive case. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Message-id: 20240827034927.66659-5-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/net/can/xlnx-versal-canfd: Translate CAN ID registersDoug Brown
Previously the emulated CAN ID register was being set to the exact same value stored in qemu_can_frame.can_id. This doesn't work correctly because the Xilinx IP core uses a different bit arrangement than qemu_can_frame for all of its ID registers. Correct this problem for both RX and TX, including RX filtering. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Message-id: 20240827034927.66659-4-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/net/can/xlnx-versal-canfd: Fix CAN FD flag checkDoug Brown
When checking the QEMU_CAN_FRMF_TYPE_FD flag, we need to ignore other potentially set flags. Before this change, received CAN FD frames from SocketCAN weren't being recognized as CAN FD. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20240827034927.66659-3-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/net/can/xlnx-versal-canfd: Fix interrupt levelDoug Brown
The interrupt level should be 0 or 1. The existing code was using the interrupt flags to determine the level. In the only machine currently supported (xlnx-versal-virt), the GICv3 was masking off all bits except bit 0 when applying it, resulting in the IRQ never being delivered. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Message-id: 20240827034927.66659-2-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hvf: arm: Implement and use hvf_get_physical_address_rangeDanny Canter
This patch's main focus is to use the previously added hvf_get_physical_address_range to inform VM creation about the IPA size we need for the VM, so we can extend the default 36b IPA size and support VMs with 64+GB of RAM. This is done by freezing the memory map, computing the highest GPA and then (depending on if the platform supports an IPA size that large) telling the kernel to use a size >= for the VM. In pursuit of this a couple of things related to how we handle the physical address range we expose to guests were altered, but for an explanation of what we were doing: Today, to get the IPA size we were reading id_aa64mmfr0_el1's PARange field from a newly made vcpu. Unfortunately, HVF just returns the hosts PARange directly for the initial value and not the IPA size that will actually back the VM, so we believe we have much more address space than we actually do today it seems. Starting in macOS 13.0 some APIs were introduced to be able to query the maximum IPA size the kernel supports, and to set the IPA size for a given VM. However, this still has a couple of issues on < macOS 15. Up until macOS 15 (and if the hardware supported it) the max IPA size was 39 bits which is not a valid PARange value, so we can't clamp down what we advertise in the vcpu's id_aa64mmfr0_el1 to our IPA size. Starting in macOS 15 however, the maximum IPA size is 40 bits (if it's supported in the hardware as well) which is also a valid PARange value so we can set our IPA size to the maximum as well as clamp down the PARange we advertise to the guest. This allows VMs with 64+ GB of RAM and should fix the oddness of the PARange situation as well. Signed-off-by: Danny Canter <danny_canter@apple.com> Message-id: 20240828111552.93482-4-danny_canter@apple.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/boards: Add hvf_get_physical_address_range to MachineClassDanny Canter
This addition will be necessary for some HVF related work to follow. For HVF on ARM there exists a set of APIs in macOS 13 to be able to adjust the IPA size for a given VM. This is useful as by default HVF uses 36 bits as the IPA size, so to support guests with > 64GB of RAM we'll need to reach for this. To have all the info necessary to carry this out however, we need some plumbing to be able to grab the memory map and compute the highest GPA prior to creating the VM. This is almost exactly like what kvm_type is used for on ARM today, and is also what this will be used for. We will compute the highest GPA and find what IPA size we'd need to satisfy this, and if it's valid (macOS today caps at 40b) we'll set this to be the IPA size in coming patches. This new method is only needed (today at least) on ARM, and obviously only for HVF/macOS, so admittedly it is much less generic than kvm_type today, but it seemed a somewhat sane way to get the information we need from the memmap at VM creation time. Signed-off-by: Danny Canter <danny_canter@apple.com> Message-id: 20240828111552.93482-2-danny_canter@apple.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: removed explicit setting of field to NULL on x86] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/core/resettable: Remove transitional_function machineryPeter Maydell
We used to need the transitional_function machinery to handle bus classes and device classes which still used their legacy reset handling. We have now converted all bus classes to three phase reset, and simplified the device class legacy reset so it is just an adapting wrapper function around registration of a hold phase method. There are therefore no more users of the transitional_function machinery and we can remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240830145812.1967042-12-peter.maydell@linaro.org
2024-09-13hw/core/qdev: Simplify legacy_reset handlingPeter Maydell
Now that all devices which still implement a the legacy reset method register it via device_class_legacy_reset(), we can simplify the handling of these devices. Instead of using the complex Resettable::get_transitional_function machinery, we register a hold phase method which invokes the DeviceClass::legacy_reset method. This will allow us to remove all the get_transitional_function handling from resettable.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240830145812.1967042-11-peter.maydell@linaro.org
2024-09-13hw: Remove device_phases_reset()Peter Maydell
Currently we have transitional machinery between legacy reset and three phase reset that works in two directions: * if you invoke three phase reset on a device which has set the DeviceClass::legacy_reset method, we detect this in device_get_transitional_reset() and arrange that we call the legacy_reset method during the hold phase of reset * if you invoke legacy reset on a device which implements three phase reset, the default legacy_reset method is device_phases_reset(), which does a three-phase reset of the device However, we have now eliminated all the places which could invoke legacy reset on a device, which means that the function device_phases_reset() is never called -- it serves only as the value of DeviceClass::legacy_reset that indicates that the subclass never overrode the legacy reset method. So we can delete it, and instead check for legacy_reset != NULL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-10-peter.maydell@linaro.org
2024-09-13hw: Rename DeviceClass::reset field to legacy_resetPeter Maydell
Rename the DeviceClass::reset field to legacy_reset; this is helpful both in flagging up that it's best not used in new code and in making it easy to search for where it's being used still. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-9-peter.maydell@linaro.org
2024-09-13hw: Use device_class_set_legacy_reset() instead of opencodingPeter Maydell
Use device_class_set_legacy_reset() instead of opencoding an assignment to DeviceClass::reset. This change was produced with: spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/device-reset.cocci \ --keep-comments --smpl-spacing --in-place --dir hw Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
2024-09-13hw: Define new device_class_set_legacy_reset()Peter Maydell
Define a device_class_set_legacy_reset() function which sets the DeviceClass::reset field. This serves two purposes: * it makes it clearer to the person writing code that DeviceClass::reset is now legacy and they should look for the new alternative (which is Resettable) * it makes it easier to rename the reset field (which in turn makes it easier to find places that call it) The Coccinelle script can be used to automatically convert code that was doing an open-coded assignment to DeviceClass::reset to call device_class_set_legacy_reset() instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-7-peter.maydell@linaro.org
2024-09-13hw: Remove device_class_set_parent_reset()Peter Maydell
There are no callers of device_class_set_parent_reset() left in the tree, as they've all been converted to use three-phase reset and the corresponding resettable_class_set_parent_phases() function. Remove device_class_set_parent_reset(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-5-peter.maydell@linaro.org
2024-09-13hw/s390/virtio-ccw: Convert to three-phase resetPeter Maydell
Convert the virtio-ccw code to three-phase reset. This allows us to remove a call to device_class_set_parent_reset(), replacing it with the three-phase equivalent resettable_class_set_parent_phases(). Removing all the device_class_set_parent_reset() uses will allow us to remove some of the glue code that interworks between three-phase and legacy reset. This is a simple conversion, with no behavioural changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-3-peter.maydell@linaro.org
2024-09-13hw/s390/ccw-device: Convert to three-phase resetPeter Maydell
Convert the TYPE_CCW_DEVICE to three-phase reset. This is a device class which is subclassed, so it needs to be three-phase before we can convert the subclass. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-id: 20240830145812.1967042-2-peter.maydell@linaro.org
2024-09-13Merge tag 'pull-loongarch-20240912' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell
staging pull-loongarch-20240912 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZuLmLgAKCRBAov/yOSY+ # 38JNA/9UdorT4a7H+H5PhNeEu2EHDgMPb7+gxyYKw03mOG2MB3KFzkK0LRQShaPt # ADJmIqAFlc9SJLkbo6ELMDl+ZnUU9OdC/P6YU5iBG71zx1PonMwuyJTWhlBwxWcG # +OB8aDBUALoe/Gb4za152I84cR08g58TgLnXNfEkCM8lnPfAug== # =Plwu # -----END PGP SIGNATURE----- # gpg: Signature made Thu 12 Sep 2024 14:01:34 BST # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20240912' of https://gitlab.com/gaosong/qemu: hw/loongarch: Add acpi SPCR table support hw/loongarch: virt: pass random seed to fdt hw/loongarch: virt: support up to 4 serial ports target/loongarch: Support QMP dump-guest-memory target/loongarch/kvm: Add vCPU reset function hw/loongarch: Remove default enable with VIRTIO_VGA device target/loongarch: Add compatible support about VM reboot Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-12Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell
into staging virtio,pc,pci: features, fixes, cleanups i286 acpi speedup by precomputing _PRT by Ricardo Ribalda vhost_net speedup by using MR transactions by Zuo Boqun ich9 gained support for periodic and swsmi timer by Dominic Prinz Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmbhoCUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRptpUH/iR5AmJFpvAItqlPOvJiYDEch46C73tyrSws # Kk/1EbGSL7mFFD5sfdSSV4Rw8CQBsmM/Dt5VDkJKsWnOLjkBQ2CYH0MYHktnrKcJ # LlSk32HnY5p1DsXnJhgm5M7St8T3mV/oFdJCJAFgCmpx5uT8IRLrKETN8+30OaiY # xo35xAKOAS296+xsWeVubKkMq7H4y2tdZLE/22gb8rlA8d96BJIeVLQ3y3IjeUPR # 24q6c7zpObzGhYNZ/PzAKOn+YcVsV/lLAzKRZJTzTUPyG24BcjJTyyr/zNSYAgfk # lLXzIZID3GThBmrCAiDZ1z6sfo3MRg2wNS/FBXtK6fPIuFxed+8= # =ySRy # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Sep 2024 14:50:29 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: hw/acpi/ich9: Add periodic and swsmi timer virtio-mem: don't warn about THP sizes on a kernel without THP support hw/audio/virtio-sound: fix heap buffer overflow hw/cxl: fix physical address field in get scan media results output virtio-pci: Add lookup subregion of VirtIOPCIRegion MR vhost_net: configure all host notifiers in a single MR transaction tests/acpi: pc: update golden masters for DSDT hw/i386/acpi-build: Return a pre-computed _PRT table tests/acpi: pc: allow DSDT acpi table changes intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode intel_iommu: Fix invalidation descriptor type field virtio: rename virtio_split_packed_update_used_idx hw/pci/pci-hmp-cmds: Avoid displaying bogus size in 'info pci' pci: don't skip function 0 occupancy verification for devfn auto assign hw/isa/vt82c686.c: Embed i8259 irq in device state instead of allocating hw: Move declaration of IRQState to header and add init function virtio: Always reset vhost devices virtio: Allow .get_vhost() without vhost_started Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-12hw/loongarch: Add acpi SPCR table supportBibo Mao
Serial port console redirection table can be used for default serial port selection, like chosen stdout-path selection with FDT method. With acpi SPCR table added, early debug console can be parsed from SPCR table with simple kernel parameter earlycon rather than earlycon=uart,mmio,0x1fe001e0 Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240907073037.243353-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-09-12hw/loongarch: virt: pass random seed to fdtJason A. Donenfeld
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This is the same procedure that's done in b91b6b5a2c ("hw/microblaze: pass random seed to fdt"), e4b4f0b71c ("hw/riscv: virt: pass random seed to fdt"), c6fe3e6b4c ("hw/openrisc: virt: pass random seed to fdt"), 67f7e426e5 ("hw/i386: pass RNG seed via setup_data entry"), c287941a4d ("hw/rx: pass random seed to fdt"), 5e19cc68fb ("hw/mips: boston: pass random seed to fdt"), 6b23a67916 ("hw/nios2: virt: pass random seed to fdt") c4b075318e ("hw/ppc: pass random seed to fdt"), and 5242876f37 ("hw/arm/virt: dt: add rng-seed property"). These earlier commits later were amended to rerandomize the RNG seed on snapshot load, but the LoongArch code somehow already does that, despite not having this patch here, presumably due to some lucky copy and pasting. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240905153316.2038769-1-Jason@zx2c4.com> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-09-12hw/loongarch: virt: support up to 4 serial portsJason A. Donenfeld
In order to support additional channels of communication using `-serial`, add several serial ports, up to the standard 4 generally supported by the 8250 driver. Fixed: https://lore.kernel.org/all/20240907143439.2792924-1-Jason@zx2c4.com/ Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Tested-by: Bibo Mao <maobibo@loongson.cn> [gaosong: ACPI uart need't reverse order] Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240907143439.2792924-1-Jason@zx2c4.com>