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2024-09-24hw/net: replace assert(0) with g_assert_not_reached()Pierrick Bouvier
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20240919044641.386068-4-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-24hw/arm: replace assert(0) with g_assert_not_reached()Pierrick Bouvier
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20240919044641.386068-3-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-24hw/acpi: replace assert(0) with g_assert_not_reached()Pierrick Bouvier
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20240919044641.386068-2-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-24virtio-mem: Add support for suspend+wake-up with plugged memoryJuraj Marcin
Before, the virtio-mem device would unplug all the memory with any reset of the device, including during the wake-up of the guest from a suspended state. Due to this, the virtio-mem driver in the Linux kernel disallowed suspend-to-ram requests in the guest when the VIRTIO_MEM_F_PERSISTENT_SUSPEND feature is not exposed by QEMU. This patch adds the code to skip the reset on wake-up and exposes theVIRTIO_MEM_F_PERSISTENT_SUSPEND feature to the guest kernel driver when suspending is possible in QEMU (currently only x86). Message-ID: <20240904103722.946194-5-jmarcin@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Juraj Marcin <jmarcin@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-09-24virtio-mem: Use new Resettable framework instead of LegacyResetJuraj Marcin
LegacyReset does not pass ResetType to the reset callback method, which the new Resettable framework uses. Due to this, virtio-mem cannot use the new RESET_TYPE_WAKEUP to skip the reset during wake-up from a suspended state. This patch adds overrides Resettable interface methods in VirtIOMEMClass to use the new Resettable framework and replaces qemu_[un]register_reset() calls with qemu_[un]register_resettable(). Message-ID: <20240904103722.946194-4-jmarcin@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Juraj Marcin <jmarcin@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-09-24reset: Add RESET_TYPE_WAKEUPJuraj Marcin
Some devices need to distinguish cold start reset from waking up from a suspended state. This patch adds new value to the enum, and updates the i386 wakeup method to use this new reset type. Message-ID: <20240904103722.946194-3-jmarcin@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Juraj Marcin <jmarcin@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-09-24reset: Use ResetType for qemu_devices_reset() and MachineClass::reset()Juraj Marcin
Currently, both qemu_devices_reset() and MachineClass::reset() use ShutdownCause for the reason of the reset. However, the Resettable interface uses ResetState, so ShutdownCause needs to be translated to ResetType somewhere. Translating it qemu_devices_reset() makes adding new reset types harder, as they cannot always be matched to a single ShutdownCause here, and devices may need to check the ResetType to determine what to reset and if to reset at all. This patch moves this translation up in the call stack to qemu_system_reset() and updates all MachineClass children to use the ResetType instead. Message-ID: <20240904103722.946194-2-jmarcin@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Juraj Marcin <jmarcin@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-09-24virtio: kconfig: memory devices are PCI onlyPaolo Bonzini
Virtio memory devices rely on PCI BARs to expose the contents of memory. Because of this they cannot be used (yet) with virtio-mmio or virtio-ccw. In fact the code that is common to virtio-mem and virtio-pmem, which is in hw/virtio/virtio-md-pci.c, is only included if CONFIG_VIRTIO_PCI is set. Reproduce the same condition in the Kconfig file, only allowing VIRTIO_MEM and VIRTIO_PMEM to be defined if the transport supports it. Without this patch it is possible to create a configuration with CONFIG_VIRTIO_PCI=n and CONFIG_VIRTIO_MEM=y, but that causes a linking failure. Message-ID: <20240906101658.514470-1-pbonzini@redhat.com> Reported-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-09-20license: Update deprecated SPDX tag GPL-2.0 to GPL-2.0-onlyPhilippe Mathieu-Daudé
The 'GPL-2.0' license identifier has been deprecated since license list version 3.0 [1] and replaced by the 'GPL-2.0-only' tag [2]. [1] https://spdx.org/licenses/GPL-2.0.html [2] https://spdx.org/licenses/GPL-2.0-only.html Mechanical patch running: $ sed -i -e s/GPL-2.0/GPL-2.0-only/ \ $(git grep -l 'SPDX-License-Identifier: GPL-2.0[ $]' \ | egrep -v '^linux-headers|^include/standard-headers') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-laterPhilippe Mathieu-Daudé
The 'GPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'GPL-2.0-or-later' [2] tag. [1] https://spdx.org/licenses/GPL-2.0+.html [2] https://spdx.org/licenses/GPL-2.0-or-later.html Mechanical patch running: $ sed -i -e s/GPL-2.0+/GPL-2.0-or-later/ \ $(git grep -lP 'SPDX-License-Identifier: \W+GPL-2.0\+[ $]' \ | egrep -v '^linux-headers|^include/standard-headers') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20license: Simplify GPL-2.0-or-later license descriptionsPhilippe Mathieu-Daudé
Since the "2 | 3+" expression can be simplified as "2+", it is pointless to mention the GPLv3 license. Add the corresponding SPDX identifier to remove all doubt. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20hw/sysbus: Remove unused sysbus_mmio_unmapDr. David Alan Gilbert
The last use of sysbus_mmio_unmap was removed by 981b1c6266 ("spapr/xive: rework the mapping the KVM memory regions") Remove it. Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20hw/display: Fix mirrored output in dm163Inès Varhol
DM163 is an emulated 8x8 LED matrix. This commit flips the image horizontally so it's rendered the same way as on the hardware. Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20hw/virtio/Kconfig: Include vhost-user-scmi only on arm targetsThomas Huth
The System Control and Management Interface is specific to arm machines, so don't include this device in non-arm targets. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Milan Zamazal <mzamazal@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20hw/loongarch/virt: Add description for virt machine typeBibo Mao
The description about virt machine type is removed by mistake, add new description here. Here is output result with command "./qemu-system-loongarch64 -M help" Supported machines are: none empty machine virt QEMU LoongArch Virtual Machine (default) x-remote Experimental remote machine Without the patch, it shows as follows: Supported machines are: none empty machine virt (null) (default) x-remote Experimental remote machine Fixes: ef2f11454c(hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI) Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20hw/mips/jazz: fix typo in in-built NIC aliasMark Cave-Ayland
Commit e104edbb9d ("hw/mips/jazz: use qemu_find_nic_info()") contained a typo in the NIC alias which caused initialisation of the in-built dp83932 NIC to fail when using the normal -nic user,model=dp83932 command line. Fixes: e104edbb9d ("hw/mips/jazz: use qemu_find_nic_info()") Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20ppc: fix incorrect spelling of PowerMacTejas Vipin
PowerMac is spelled as PowerMAC (Media Access Control) in some places. This is misleading. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2297 Signed-off-by: Tejas Vipin <tejasvipin76@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20mark <zlib.h> with for-crc32 in a consistent mannerMichael Tokarev
in many cases, <zlib.h> is only included for crc32 function, and in some of them, there's a comment saying that, but in a different way. In one place (hw/net/rtl8139.c), there was another #include added between the comment and <zlib.h> include. Make all such comments to be on the same line as #include, make it consistent, and also add a few missing comments, including hw/nvram/mac_nvram.c which uses adler32 instead. There's no code changes. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-19hw/char/stm32l4x5_usart.c: Enable USART ACK bit responseJacob Abrams
SW modifying USART_CR1 TE bit should cuase HW to respond by altering USART_ISR TEACK bit, and likewise for RE and REACK bit. This resolves some but not all issues necessary for the official STM USART HAL driver to function as is. Fixes: 87b77e6e01ca ("hw/char/stm32l4x5_usart: Enable serial read and write") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2540 Signed-off-by: Jacob Abrams <satur9nine@gmail.com> Message-id: 20240911043255.51966-1-satur9nine@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-18mac_dbdma: Remove leftover `dma_memory_unmap` callsMattias Nissler
These were passing a NULL buffer pointer unconditionally, which happens to behave in a mostly benign way (except for the chance of an excess memory region unref and a bounce buffer leak). Per the function comment, this was never meant to be accepted though, and triggers an assertion with the "softmmu: Support concurrent bounce buffers" change. Given that the code in question never sets up any mappings, just remove the unnecessary dma_memory_unmap calls along with the DBDMA_io struct fields that are now entirely unused. Signed-off-by: Mattias Nissler <mnissler@rivosinc.com> Message-Id: <20240916175708.1829059-1-mnissler@rivosinc.com> Fixes: be1e343995 ("macio: switch over to new byte-aligned DMA helpers") Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-09-17Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into stagingPeter Maydell
Pull request An integer overflow fix for the last zone on a zoned block device whose capacity is not a multiple of the zone size. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmbpa0sACgkQnKSrs4Gr # c8hdAwgAgp6AJVXHiPo43GbhdSsKJ2bq8DIPrsqgwAxD3rgxxRVwsWzENQgzF8O9 # qoXPmU0eqPp0zTsKTxNrlIgCpsJ3X4Oeg89u4N1xUOAJtADZGlbucUQEkAgIhWMl # IFLjtFc7EbhWn57FmQGzANeOJOB+OumfQGeC7wbeAtUCn7g08rXtq+5I5GRKqkkP # u1FlSassd7fyVnlVc+BT2aKANBITKhJGhYqwndvxXzMIi0L54/bQRrarLoy7oJuG # 1k8zYLi6giUINNwYMtzn5ooXNnOSoxHKKfwcFT8hGZixwBBnCnYHjNkfs/QyvZQ7 # ZuR9mY6pqp/lg5127UlpOR7d6HADLQ== # =709Z # -----END PGP SIGNATURE----- # gpg: Signature made Tue 17 Sep 2024 12:43:07 BST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: hw/block: fix uint32 overflow Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-17Merge tag 'pull-vfio-20240917' of https://github.com/legoater/qemu into stagingPeter Maydell
vfio queue: * Support for IGDs of gen 11 and later * Coverity fixes # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmbpWl0ACgkQUaNDx8/7 # 7KFYJhAAu8Dyf96RUr4ucu/VaSlTi/rk/i5sivD4EXiCOf2qpQtyoo+C8DJmjAZg # nC+4IpD2vu2C/xaZoQ4o6uQL7c45dOup59jcbKO+6NekF521Y6aq9OvE5v55CAwu # R38UWI6ZX5qqyU/tA39/s7migIvCtK7VgTzEs2Lpzw8WetCFattvrEiKHt09fNdX # kSPdFVV6FymOowAekQtI2JACr8C5nm8x9npzyL1SjauvWA70aOU9h1iHoIxHGKFF # jlotd6v16c0Z260AUP/RDBwf8wqg2MtwBOI3qVGYD20Xd7tRQkLlFp8X5lNw4pHr # eylqqxW3E4LJ4vSWpi4Jj2tZN5tZl8X927ew79D2gf69R8f1l+5CG/qqynMRbZ0b # gE1E5UNfEkXYX9PMuf2uenoiahMxh7ZHwzJmtFcTLGyHGudSaUu3S7Yu5a1R0ZDf # 8OyzE1E1X/8uCABvSgPphtSfYD9kXKiwNJSPrj3PZ1nXgNoA6BDi5sOeTPm0POBA # IfB10VEXDd61KPFKGQqZ1Qqrvb0LsCTvFTwCHRHBEB/F/ykwTX9dzrTInkTBTiQU # OyDjKZvR2ACjysuFxvpA2fhhF7KCmCwg7M/YsKyVLKq2r3TdBnDS1DHm7Z5ebNu4 # vgV4fsPCnjaQxOHEHZmh+rxG0E2dOGMiCieY9ooJ6jeomKQ+d60= # =cIWS # -----END PGP SIGNATURE----- # gpg: Signature made Tue 17 Sep 2024 11:30:53 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20240917' of https://github.com/legoater/qemu: vfio/igd: correctly calculate stolen memory size for gen 9 and later vfio/igd: don't set stolen memory size to zero vfio/igd: add ID's for ElkhartLake and TigerLake vfio/igd: add new bar0 quirk to emulate BDSM mirror vfio/igd: use new BDSM register location and size for gen 11 and later vfio/igd: support legacy mode for all known generations vfio/igd: return an invalid generation for unknown devices hw/vfio/pci.c: Use correct type in trace_vfio_msix_early_setup() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-17hw/block: fix uint32 overflowDmitry Frolov
The product bs->bl.zone_size * (bs->bl.nr_zones - 1) may overflow uint32. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Dmitry Frolov <frolov@swemel.ru> Message-id: 20240917080356.270576-2-frolov@swemel.ru Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-09-17vfio/igd: correctly calculate stolen memory size for gen 9 and laterCorvin Köhne
We have to update the calculation of the stolen memory size because we've seen devices using values of 0xf0 and above for the graphics mode select field. The new calculation was taken from the linux kernel [1]. [1] https://github.com/torvalds/linux/blob/7c626ce4bae1ac14f60076d00eafe71af30450ba/arch/x86/kernel/early-quirks.c#L455-L460 Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2024-09-17vfio/igd: don't set stolen memory size to zeroCorvin Köhne
The stolen memory is required for the GOP (EFI) driver and the Windows driver. While the GOP driver seems to work with any stolen memory size, the Windows driver will crash if the size doesn't match the size allocated by the host BIOS. For that reason, it doesn't make sense to overwrite the stolen memory size. It's true that this wastes some VM memory. In the worst case, the stolen memory can take up more than a GB. However, that's uncommon. Additionally, it's likely that a bunch of RAM is assigned to VMs making use of GPU passthrough. Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2024-09-17vfio/igd: add ID's for ElkhartLake and TigerLakeCorvin Köhne
ElkhartLake and TigerLake devices were tested in legacy mode with Linux and Windows VMs. Both are working properly. It's likely that other Intel GPUs of gen 11 and 12 like IceLake device are working too. However, we're only adding known good devices for now. Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2024-09-17vfio/igd: add new bar0 quirk to emulate BDSM mirrorCorvin Köhne
The BDSM register is mirrored into MMIO space at least for gen 11 and later devices. Unfortunately, the Windows driver reads the register value from MMIO space instead of PCI config space for those devices [1]. Therefore, we either have to keep a 1:1 mapping for the host and guest address or we have to emulate the MMIO register too. Using the igd in legacy mode is already hard due to it's many constraints. Keeping a 1:1 mapping may not work in all cases and makes it even harder to use. An MMIO emulation has to trap the whole MMIO page. This makes accesses to this page slower compared to using second level address translation. Nevertheless, it doesn't have any constraints and I haven't noticed any performance degradation yet making it a better solution. [1] https://github.com/projectacrn/acrn-hypervisor/blob/5c351bee0f6ae46250eefc07f44b4a31e770f3cf/devicemodel/hw/pci/passthrough.c#L650-L653 Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2024-09-17vfio/igd: use new BDSM register location and size for gen 11 and laterCorvin Köhne
Intel changed the location and size of the BDSM register for gen 11 devices and later. We have to adjust our emulation for these devices to properly support them. Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2024-09-17vfio/igd: support legacy mode for all known generationsCorvin Köhne
We're soon going to add support for legacy mode to ElkhartLake and TigerLake devices. Those are gen 11 and 12 devices. At the moment, all devices identified by our igd_gen function do support legacy mode. This won't change when adding our new devices of gen 11 and 12. Therefore, it makes more sense to accept legacy mode for all known devices instead of maintaining a long list of known good generations. If we add a new generation to igd_gen which doesn't support legacy mode for some reason, it'll be easy to advance the check to reject legacy mode for this specific generation. Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2024-09-17vfio/igd: return an invalid generation for unknown devicesCorvin Köhne
Intel changes it's specification quite often e.g. the location and size of the BDSM register has change for gen 11 devices and later. This causes our emulation to fail on those devices. So, it's impossible for us to use a suitable default value for unknown devices. Instead of returning a random generation value and hoping that everthing works fine, we should verify that different devices are working and add them to our list of known devices. Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2024-09-17hw/vfio/pci.c: Use correct type in trace_vfio_msix_early_setup()Peter Maydell
The tracepoint trace_vfio_msix_early_setup() uses "int" for the type of the table_bar argument, but we use this to print a uint32_t. Coverity warns that this means that we could end up treating it as a negative number. We only use this in printing the value in the tracepoint, so mishandling it as a negative number would be harmless, but it's better to use the right type in the tracepoint. Use uint64_t to match how we print the table_offset in the vfio_msix_relo() tracepoint. Resolves: Coverity CID 1547690 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16aspeed: Add tmp105 in i2c bus 0 for AST2700Jamin Lin
ASPEED SDK add lm75 in i2c bus 0 for AST2700. LM75 is compatible with TMP105 driver. Introduce a new i2c init function and add tmp105 device model in i2c bus 0. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16aspeed/soc: Support I2C for AST2700Jamin Lin
Add I2C model for AST2700 I2C support. The I2C controller registers base address is start at 0x14C0_F000 and its address space is 0x2000. The AST2700 I2C controller has one source INTC per bus. I2C buses interrupt are connected to GICINT130_INTC from bit 0 to bit 15. I2C bus 0 is connected to GICINT130_INTC at bit 0. I2C bus 15 is connected to GICINT130_INTC at bit 15. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16aspeed/soc: Introduce a new API to get the device irqJamin Lin
Currently, users can set the INTC mapping table with enumerated device id and device irq to get the INTC orgate input pins. However, some devices use the continuous source numbers in the same INTC orgate. To reduce the enumerated device id definition, create a new API to get the INTC orgate input pin if users only provide the device id with its bus number index. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Add support for 64 bit addressesJamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address. The AST2700 support the maximum DRAM size is 8 GB. The DRAM physical address range is from "0x4_0000_0000" to "0x5_FFFF_FFFF". The DRAM offset range is from "0x0_0000_0000" to "0x1_FFFF_FFFF" and it is enough to use bits [33:0] saving the dram offset. Therefore, save the high part physical address bit[1:0] of Tx/Rx buffer address as dma_dram_offset bit[33:32]. It does not need to decrease the dram physical high part address for DMA operation. (high part physical address bit[7:0] – 4) Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addressesJamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address. It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)" registers to save the high part physical address of Tx/Rx buffer address for master mode. It has "Slave DMA Mode Tx Buffer Base Address[39:32](0x68)" and "Slave DMA Mode Rx Buffer Base Address[39:32](0x6C)" registers to save the high part physical address of Tx/Rx buffer address for slave mode. Ex: Tx buffer address for master mode [39:0] The "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" bits [7:0] which corresponds the bits [39:32] of the 64 bits address of the Tx buffer address. The "Master DMA Mode Tx Buffer Base Address(0x30)" bits [31:0] which corresponds the bits [31:0] of the 64 bits address of the Tx buffer address. Introduce a new has_dma64 class attribute and new registers for the new mode to support DMA 64 bits dram address. Update new mode register number to 28. The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
2024-09-16hw/i2c/aspeed: Add AST2700 supportJamin Lin
Introduce a new ast2700 class to support AST2700. The I2C bus register memory regions and I2C bus pool buffer memory regions are discontinuous and they do not back compatible AST2600. Add a new ast2700 i2c class init function to match the address of I2C bus register and pool buffer from the datasheet. An I2C controller registers owns 8KB address space. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2CbusJamin Lin
The "Current DMA Operating Address Status(0x50)" register of I2C new mode has been removed in AST2700. This register is used for debugging and it is a read only register. To support AST2700 DMA mode, introduce a new dma_dram_offset class attribute in AspeedI2Cbus to save the current DMA operating address. ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 00000000" which is 64bits address. Set the dma_dram_offset data type to uint64_t for 64 bits dram address DMA support. Both "DMA Mode Buffer Address Register(I2CD24 old mode)" and "DMA Operating Address Status (I2CC50 new mode)" are used for showing the low part dram offset bits [31:0], so change to read/write both register bits [31:0] in bus register read/write functions. The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C busJamin Lin
It only support continuous pool buffer memory region for all I2C bus. However, the pool buffer address of all I2c bus are discontinuous for AST2700. Ex: the pool buffer address of I2C bus for ast2700 as following. 0x1A0 - 0x1BF: Device 0 buffer 0x2A0 - 0x2BF: Device 1 buffer 0x3A0 - 0x3BF: Device 2 buffer 0x4A0 - 0x4BF: Device 3 buffer 0x5A0 - 0x5BF: Device 4 buffer 0x6A0 - 0x6BF: Device 5 buffer 0x7A0 - 0x7BF: Device 6 buffer 0x8A0 - 0x8BF: Device 7 buffer 0x9A0 - 0x9BF: Device 8 buffer 0xAA0 - 0xABF: Device 9 buffer 0xBA0 - 0xBBF: Device 10 buffer 0xCA0 - 0xCBF: Device 11 buffer 0xDA0 - 0xDBF: Device 12 buffer 0xEA0 - 0xEBF: Device 13 buffer 0xFA0 – 0xFBF: Device 14 buffer 0x10A0 – 0x10BF: Device 15 buffer Introduce a new class attribute to make user set each I2C bus pool buffer gap size. Update formula to create all I2C bus pool buffer memory regions. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2CbusJamin Lin
According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500. Only AST2400 utilized a pool buffer share to all I2C bus. Besides, using a share pool buffer only support pool buffer memory regions are continuous for all I2C bus. To make this model more readable and support discontinuous bus pool buffer memory regions, changes to introduce a new bus pool buffer attribute in AspeedI2Cbus and new memops. So, it does not need to calculate the pool buffer offset for different I2C bus. Introduce a new has_share_pool class attribute in AspeedI2CClass and use it to create either a share pool buffer or bus pool buffers in aspeed_i2c_realize. Update each pull buffer size to 0x10 for AST2500 and 0x20 for AST2600 and AST1030. Incrementing the version of aspeed_i2c_bus_vmstate to 6. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Support discontinuous register memory region of I2C busJamin Lin
It only support continuous register memory region for all I2C bus. However, the register address of all I2c bus are discontinuous for AST2700. Ex: the register address of I2C bus for ast2700 as following. 0x100 - 0x17F: Device 0 0x200 - 0x27F: Device 1 0x300 - 0x37F: Device 2 0x400 - 0x47F: Device 3 0x500 - 0x57F: Device 4 0x600 - 0x67F: Device 5 0x700 - 0x77F: Device 6 0x800 - 0x87F: Device 7 0x900 - 0x97F: Device 8 0xA00 - 0xA7F: Device 9 0xB00 - 0xB7F: Device 10 0xC00 - 0xC7F: Device 11 0xD00 - 0xD7F: Device 12 0xE00 - 0xE7F: Device 13 0xF00 – 0xF7F: Device 14 0x1000 – 0x107F: Device 15 Introduce a new class attribute to make user set each I2C bus gap size. Update formula to create all I2C bus register memory regions. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/gpio/aspeed_gpio: Avoid shift into sign bitPeter Maydell
In aspeed_gpio_update() we calculate "mask = 1 << gpio", where gpio can be between 0 and 31. Coverity complains about this because 1 << 31 won't fit in a signed integer. For QEMU this isn't an error because we enable -fwrapv, but we can keep Coverity happy by doing the shift on unsigned numbers. Resolves: Coverity CID 1547742 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-13hw/pci-host: remove break after g_assert_not_reached()Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from some versions of GCC (i.e. using -fsanitize=thread with gcc-12): error: control reaches end of non-void function [-Werror=return-type] default: g_assert_not_reached(); break; | ^^^^^ Solve that by removing the unreachable 'break' statement, unifying the code base on g_assert_not_reached() instead. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910221606.1817478-31-pierrick.bouvier@linaro.org> [PMD: Add description suggested by Eric Blake] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/misc: remove break after g_assert_not_reached()Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from some versions of GCC (i.e. using -fsanitize=thread with gcc-12): error: control reaches end of non-void function [-Werror=return-type] default: g_assert_not_reached(); break; | ^^^^^ Solve that by removing the unreachable 'break' statement, unifying the code base on g_assert_not_reached() instead. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910221606.1817478-29-pierrick.bouvier@linaro.org> [PMD: Add description suggested by Eric Blake] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/gpio: remove break after g_assert_not_reached()Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from some versions of GCC (i.e. using -fsanitize=thread with gcc-12): error: control reaches end of non-void function [-Werror=return-type] default: g_assert_not_reached(); break; | ^^^^^ Solve that by removing the unreachable 'break' statement, unifying the code base on g_assert_not_reached() instead. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910221606.1817478-28-pierrick.bouvier@linaro.org> [PMD: Add description suggested by Eric Blake] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/watchdog: replace assert(0) with g_assert_not_reached()Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from some versions of GCC (i.e. using -fsanitize=thread with gcc-12): error: control reaches end of non-void function [-Werror=return-type] default: assert(0); | } | ^ Solve that by unifying the code base on g_assert_not_reached() instead. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard W.M. Jones <rjones@redhat.com> Message-ID: <20240910221606.1817478-8-pierrick.bouvier@linaro.org> [PMD: Add description suggested by Eric Blake] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/core: replace assert(0) with g_assert_not_reached()Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from some versions of GCC (i.e. using -fsanitize=thread with gcc-12): error: control reaches end of non-void function [-Werror=return-type] default: assert(0); | } | ^ Solve that by unifying the code base on g_assert_not_reached() instead. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910221606.1817478-6-pierrick.bouvier@linaro.org> [PMD: Add description suggested by Eric Blake] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/char: replace assert(0) with g_assert_not_reached()Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from some versions of GCC (i.e. using -fsanitize=thread with gcc-12): error: control reaches end of non-void function [-Werror=return-type] default: assert(0); | } | ^ Solve that by unifying the code base on g_assert_not_reached() instead. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910221606.1817478-5-pierrick.bouvier@linaro.org> [PMD: Add description suggested by Eric Blake] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/input/adb-mouse: convert to use QemuInputHandlerMark Cave-Ayland
Update the ADB mouse implementation to use QemuInputHandler instead of the legacy qemu_add_mouse_event_handler() function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240907173700.348818-1-mark.cave-ayland@ilande.co.uk> [PMD: Add comment about .sync handler] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/char/escc: convert Sun mouse to use QemuInputHandlerMark Cave-Ayland
Update the Sun mouse implementation to use QemuInputHandler instead of the legacy qemu_add_mouse_event_handler() function. Note that this conversion adds extra sunmouse_* members to ESCCChannelState but they are not added to the migration stream (similar to the Sun keyboard members). If this were desired in future, the Sun devices should be split into separate devices and added to the migration stream there instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2518 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Carl Hauser <chauser@pullman.com> Message-ID: <20240904102301.175706-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>