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AgeCommit message (Expand)Author
2024-08-01Revert "pcie_sriov: Allow user to create SR-IOV device"Michael S. Tsirkin
2024-08-01Revert "virtio-pci: Implement SR-IOV PF"Michael S. Tsirkin
2024-08-01Revert "virtio-net: Implement SR-IOV VF"Michael S. Tsirkin
2024-08-01virtio-rng: block max-bytes=0Michael S. Tsirkin
2024-07-31target/i386/cpu: Mask off SGX/SGX_LC feature words for non-PC machineZhao Liu
2024-07-29hw/misc/bcm2835_property: Reduce scope of variables in mbox push functionPeter Maydell
2024-07-29hw/misc/bcm2835_property: Restrict scope of start_num, number, otp_rowPeter Maydell
2024-07-29hw/misc/bcm2835_property: Avoid overflow in OTP access propertiesPeter Maydell
2024-07-29hw/misc/bcm2835_property: Fix handling of FRAMEBUFFER_SET_PALETTEPeter Maydell
2024-07-29hw/arm/smmuv3: Assert input to oas2bits() is validMostafa Saleh
2024-07-29hw/char/bcm2835_aux: Fix assert when receive FIFO fills upFrederik van Hövell
2024-07-26target/ppc: Unexport some functions from mmu-book3s-v3.hBALATON Zoltan
2024-07-26pnv/xive2: Dump more END state with 'info pic'Frederic Barrat
2024-07-26pnv/xive2: Refine TIMA 'info pic' outputFrederic Barrat
2024-07-26pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.cFrederic Barrat
2024-07-26pnv/xive2: Fail VST entry address computation if table has no VSDFrederic Barrat
2024-07-26pnv/xive2: Set Translation Table for the NVC port spaceFrederic Barrat
2024-07-26pnv/xive2: Enable VST NVG and NVC index compressionFrederic Barrat
2024-07-26pnv/xive2: Configure Virtualization Structure Tables through the PCFrederic Barrat
2024-07-26pnv/xive2: Add NVG and NVC to cache watch facilityFrederic Barrat
2024-07-26pnv/xive: Support cache flush and queue sync inject with notificationsNicholas Piggin
2024-07-26pnv/xive2: Structure/define alignment changesMichael Kowal
2024-07-26pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection supportFrederic Barrat
2024-07-26hw/ppc: SPI controller wiring to P10 chipChalapathi V
2024-07-26hw/block: Add Microchip's 25CSM04 to m25p80Chalapathi V
2024-07-26hw/ssi: Extend SPI modelChalapathi V
2024-07-26hw/ssi: Add SPI modelChalapathi V
2024-07-26ppc/pnv: Add an LPAR per core machine optionNicholas Piggin
2024-07-26ppc/pnv: Implement POWER10 PC xscom registers for direct controlsNicholas Piggin
2024-07-26ppc/pnv: Add a CPU nmi and resume functionNicholas Piggin
2024-07-26ppc/pnv: Add big-core machine propertyNicholas Piggin
2024-07-26ppc/pnv: Add POWER10 ChipTOD quirk for big-coreNicholas Piggin
2024-07-26ppc/pnv: Implement big-core PVR for Power9/10Nicholas Piggin
2024-07-26ppc/pnv: Add allow for big-core differences in DT generationNicholas Piggin
2024-07-26ppc/pnv: Add a big-core mode that joins two regular coresNicholas Piggin
2024-07-26ppc: Add has_smt_siblings property to CPUPPCStateNicholas Piggin
2024-07-26ppc: Add a core_index to CPUPPCState for SMT vCPUsNicholas Piggin
2024-07-26ppc/pnv: Extend chip_pir class method to TIR as wellNicholas Piggin
2024-07-26ppc/pnv: use class attribute to limit SMT threads for different machinesNicholas Piggin
2024-07-26ppc/pnv: Move timebase state into PnvCoreNicholas Piggin
2024-07-26ppc/pnv: Add pointer from PnvCPUState to PnvCoreNicholas Piggin
2024-07-26ppc/pnv: Implement ADU access to LPC spaceNicholas Piggin
2024-07-26ppc/pnv: Begin a more complete ADU LPC model for POWER9/10Nicholas Piggin
2024-07-26ppc/pnv: Implement POWER9 LPC PSI serirq outputs and auto-clear functionNicholas Piggin
2024-07-26ppc/pnv: Fix loss of LPC SERIRQ interruptsGlenn Miles
2024-07-26ppc/pnv: Update Power10's cfam id to use Power10 DD2Aditya Gupta
2024-07-26ppc/vof: Fix unaligned FDT property accessAkihiko Odaki
2024-07-26spapr: Free stdout pathAkihiko Odaki
2024-07-26spapr: Migrate ail-mode-3 spapr capNicholas Piggin
2024-07-24Merge tag 'hw-misc-20240723' of https://github.com/philmd/qemu into stagingRichard Henderson
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