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2023-11-21Merge tag 'pull-xenfv-20231121' of git://git.infradead.org/users/dwmw2/qemu ↵Stefan Hajnoczi
into staging Xen fixes for 8.2-rc1 • Disable default serial when xen-console is used • Fix Coverity warning in xen-block # -----BEGIN PGP SIGNATURE----- # # iQJIBAABCAAyFiEEvgfZ/VSAmrLEsP9fY3Ys2mfi81kFAmVcmrAUHGR3bXcyQGlu # ZnJhZGVhZC5vcmcACgkQY3Ys2mfi81njqg/8DFr03kVfwRujIZXDROoq40vjgdOF # MoGgowDNapliXiecVcHzdvFXgRxwr9bhpX5eDEtfgROoH8mbPPd4YZJHdPNM0Yc3 # 0hoSWrIYocsYRAIoozXrtsNw8ep2vSEPNv5+CIVYkkie/mLs02cy43q09cJDzABx # DvmSfC5o5JCs/x3qPLM6ydhnTaUipuPt1wnG9xaJLWgm/U9pK6Ba9w1eNGn8EE7m # ekzpv9lYfCd/KbPogtXAEd7nkCOi/lKQVJmU7auXFi8FKwZNoKOYl3cTVln/EFmT # az3qLSHgOZwElNQEYn0mBa/RgAQ2K9X7n12TgxG30VSUmajxJnl/eKy4ISyaAmwY # vNVhdsXQICqM4OYaD2j8RiXX5YNtIC+MBb7nlUN7invKXE9ZylHbXvOstkUCjQ34 # x9CMVIibPoWk7XGUX+r7KUSwSQnpelVbqBWltkmgNjYuUIShDT6r5cOrYdM2orii # UYOqPJqchbEDNoGwJK45EOSn8Ss5geAWuM7dFL0AuwZAbcKAqGG6vihPnDJyhnWA # EPv2/5h2Vi24fqeWz3W+hckm8LXrc2Ow8A0rY3WAz7CvmBTgYCPx4d4kdTU6Gysn # i8DRoKMhZS9WvHPPxY1v8+ysG1UCCNFe4qH0Wgv+ubSbr5GaK2igWIBQ5bXnuYL8 # R4Ef5pPLpa2jiF4= # =cWon # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Nov 2023 06:55:28 EST # gpg: using RSA key BE07D9FD54809AB2C4B0FF5F63762CDA67E2F359 # gpg: issuer "dwmw2@infradead.org" # gpg: Good signature from "David Woodhouse <dwmw2@infradead.org>" [unknown] # gpg: aka "David Woodhouse <dwmw2@exim.org>" [unknown] # gpg: aka "David Woodhouse <david@woodhou.se>" [unknown] # gpg: aka "David Woodhouse <dwmw2@kernel.org>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: BE07 D9FD 5480 9AB2 C4B0 FF5F 6376 2CDA 67E2 F359 * tag 'pull-xenfv-20231121' of git://git.infradead.org/users/dwmw2/qemu: hw/xen: clean up xen_block_find_free_vdev() to avoid Coverity false positive vl: disable default serial when xen-console is enabled Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-21Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingStefan Hajnoczi
Block layer patches - Fix graph lock related deadlocks with the stream job - ahci: Fix legacy software reset - ide/via: Fix switch between compatibility and native mode # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmVcmYoRHGt3b2xmQHJl # ZGhhdC5jb20ACgkQfwmycsiPL9YDzw/7BD6wZpyCsDbFu9Jbt0L894tYQls7otnR # yeAIaZVqSkDcMK8VBD/xAjV8UgX194oKPi42CDgS73avd0cSHLIM5cNgGkwCrMWS # ry5uuOP6EWVMPPR/129cpH8uGvkl+qwCQf5gB13/8NvMbeN2mHOTC6WW+VA20vb0 # V0DJXhYszVzXa3L1a/m6f4Jwj54tTeZ56JcBblL3wi/soklb45gsnPJaHeGb3rzK # yjPkw+kpVXTVbpacobGmzmjlD3Yqk69NexP2kyU1w2lqPnemYPH+9sa+7RxMspkj # InQvqq6TFtMOrC/65/527p2ENRUOxn7Xwsa1+Hnar2i3BoyGugWE8GPxJDBxAWW4 # INJtpxIpiA7Scd26VBCNVstVe5EuyxkP97T85cgNUMgeE58y3i51i6eHd4GUIR7v # PNc5TsSbnVV8sQ7RsXka4hRyjndIPRB0CBePydDoBz6zaGmcVU6ep0Oppah9gVu9 # CU0dBz2jV0r1dFhU1eZkCbd1ufdR93R/iD3gBD4vj1xSL3l+9OE/FKdrVE66uElL # iAsHp3cimkPuWAx/jZaeAC7BDI0XS6s1TimddqJx90f2mZjkq8cmVp+HoVNP0jRQ # VP6AIQy6is+P4QtDSekgXVJE8K95ngBzsr+ittR8jF4q67QzHVjLmJ9ZBXyrowlz # gtZTy2WPxbM= # =8dXj # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Nov 2023 06:50:34 EST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: hw/ide/via: implement legacy/native mode switching ide/via: don't attempt to set default BAR addresses ide/pci: introduce pci_ide_update_mode() function ide/ioport: move ide_portio_list[] and ide_portio_list2[] definitions to IDE core iotests: Test two stream jobs in a single iothread stream: Fix AioContext locking during bdrv_graph_wrlock() block: Fix deadlocks in bdrv_graph_wrunlock() block: Fix bdrv_graph_wrlock() call in blk_remove_bs() hw/ide/ahci: fix legacy software reset Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-21hw/ide/via: implement legacy/native mode switchingMark Cave-Ayland
Allow the VIA IDE controller to switch between both legacy and native modes by calling pci_ide_update_mode() to reconfigure the device whenever PCI_CLASS_PROG is updated. This patch moves the initial setting of PCI_CLASS_PROG from via_ide_realize() to via_ide_reset(), and removes the direct setting of PCI_INTERRUPT_PIN during PCI bus reset since this is now managed by pci_ide_update_mode(). This ensures that the device configuration is always consistent with respect to the currently selected mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20231116103355.588580-5-mark.cave-ayland@ilande.co.uk> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-21ide/via: don't attempt to set default BAR addressesMark Cave-Ayland
The via-ide device currently attempts to set the default BAR addresses to the values shown in the datasheet, but this doesn't work for 2 reasons: firstly BARS 1-4 do not set the bottom 2 bits to PCI_BASE_ADDRESS_SPACE_IO, and secondly the initial PCI bus reset clears the values of all PCI device BARs after the device itself has been reset. Remove the setting of the default BAR addresses from via_ide_reset() to ensure there is no doubt that these values are never exposed to the guest. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20231116103355.588580-4-mark.cave-ayland@ilande.co.uk> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-21ide/pci: introduce pci_ide_update_mode() functionMark Cave-Ayland
This function reads the value of the PCI_CLASS_PROG register for PCI IDE controllers and configures the PCI BARs and/or IDE ioports accordingly. In the case where we switch to legacy mode, the PCI BARs are set to return zero (as suggested in the "PCI IDE Controller" specification), the legacy IDE ioports are enabled, and the PCI interrupt pin cleared to indicate legacy IRQ routing. Conversely when we switch to native mode, the legacy IDE ioports are disabled and the PCI interrupt pin set to indicate native IRQ routing. The contents of the PCI BARs are unspecified, but this is not an issue since if a PCI IDE controller has been switched to native mode then its BARs will need to be programmed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20231116103355.588580-3-mark.cave-ayland@ilande.co.uk> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-21ide/ioport: move ide_portio_list[] and ide_portio_list2[] definitions to IDE ↵Mark Cave-Ayland
core These definitions are present in ioport.c which is currently only available when CONFIG_IDE_ISA is enabled. Move them to the IDE core so that they can be made available to PCI IDE controllers that support switching to legacy mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20231116103355.588580-2-mark.cave-ayland@ilande.co.uk> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-21hw/ide/ahci: fix legacy software resetNiklas Cassel
Legacy software contains a standard mechanism for generating a reset to a Serial ATA device - setting the SRST (software reset) bit in the Device Control register. Serial ATA has a more robust mechanism called COMRESET, also referred to as port reset. A port reset is the preferred mechanism for error recovery and should be used in place of software reset. Commit e2a5d9b3d9c3 ("hw/ide/ahci: simplify and document PxCI handling") improved the handling of PxCI, such that PxCI gets cleared after handling a non-NCQ, or NCQ command (instead of incorrectly clearing PxCI after receiving anything - even a FIS that failed to parse, which should NOT clear PxCI, so that you can see which command slot that caused an error). However, simply clearing PxCI after a non-NCQ, or NCQ command, is not enough, we also need to clear PxCI when receiving a SRST in the Device Control register. A legacy software reset is performed by the host sending two H2D FISes, the first H2D FIS asserts SRST, and the second H2D FIS deasserts SRST. The first H2D FIS will not get a D2H reply, and requires the FIS to have the C bit set to one, such that the HBA itself will clear the bit in PxCI. The second H2D FIS will get a D2H reply once the diagnostic is completed. The clearing of the bit in PxCI for this command should ideally be done in ahci_init_d2h() (if it was a legacy software reset that caused the reset (a COMRESET does not use a command slot)). However, since the reset value for PxCI is 0, modify ahci_reset_port() to actually clear PxCI to 0, that way we can avoid complex logic in ahci_init_d2h(). This fixes an issue for FreeBSD where the device would fail to reset. The problem was not noticed in Linux, because Linux uses a COMRESET instead of a legacy software reset by default. Fixes: e2a5d9b3d9c3 ("hw/ide/ahci: simplify and document PxCI handling") Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Message-ID: <20231108222657.117984-1-nks@flawful.org> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-21hw/xen: clean up xen_block_find_free_vdev() to avoid Coverity false positiveDavid Woodhouse
Coverity couldn't see that nr_existing was always going to be zero when qemu_xen_xs_directory() returned NULL in the ENOENT case (CID 1523906). Perhaps more to the point, neither could Peter at first glance. Improve the code to hopefully make it clearer to Coverity and human reviewers alike. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-21Merge tag 'pull-target-arm-20231121' of ↵Stefan Hajnoczi
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * enable FEAT_RNG on Neoverse-N2 * hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ * Fix SME FMOPA (16-bit), BFMOPA * hw/core/machine: Constify MachineClass::valid_cpu_types[] * stm32f* machines: Report error when user asks for wrong CPU type * hw/arm/fsl-imx: Do not ignore Error argument # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVchLYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kHMD/47tKxzrsXc6+V9esRQGi2H # 1hAgLBwglEdxLXokF+Di41sh/fvK7wYVXO/hiWlq+9h3kG3D/u1N5r1TdMPMUb9j # 4Sg3rOejn7nzkxVZ6MZ/K/1j84C9bfrt4sboVHZVRvWuvbiyuTuivEr4IqLYO4x3 # AIwhFMQ5gbNrmClZh/DBxj0keO13cp63Fg2JSSICdi+1Dw9rRXTyhJloMu1omeqc # k/BXzjSeNXpLSMyGWBR3uaPcJBaGC1xnz3Z1V7fUY1EYD2Cu1oo5lEZ9aNO5t30d # XW/qVGLa3b1Cb7WuEO247RnU3N2oZotozjFtdj/8IQoYWspM9RHyipEimUlegVdO # 3fpu8QGsN1ljNiwjdk0i6OwS7SGxcPtteFOaqEf/Yogj4EOKTn/Rx5TT4vJ5DhmI # 2w/9J15JWDIE1paNwecuFWbxCOOzSsOtSxzuyLSZDU3GlNfJ4zoF6YboROLYfejy # NXZABFhGd/0ykX7r0VY1GGYXUQ+akv6q+VDmVZCP9gMiRUiqmFPwMLMLlcuHb8G5 # 8UztN5SvOG2EYXj28Zx0BnGCNiGdI15rWMb0veqAtbnn3yEdltW3O475BAhZ0PB7 # OVpLWnXwmWURm/BGlwb1PH5s3kgWgzOebcBgcnCftwFQ8EedQAQDA5FmT+nK5SfV # VoOf89PngTubU6B3BOfeBw== # =thIa # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Nov 2023 05:21:42 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20231121' of https://git.linaro.org/people/pmaydell/qemu-arm: hw/arm/fsl-imx: Do not ignore Error argument hw/arm/stm32f100: Report error when incorrect CPU is used hw/arm/stm32f205: Report error when incorrect CPU is used hw/arm/stm32f405: Report error when incorrect CPU is used hw/core/machine: Constify MachineClass::valid_cpu_types[] target/arm: Fix SME FMOPA (16-bit), BFMOPA hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ target/arm: enable FEAT_RNG on Neoverse-N2 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-21Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingStefan Hajnoczi
# -----BEGIN PGP SIGNATURE----- # Version: GnuPG v1 # # iQEcBAABAgAGBQJlXF+GAAoJEO8Ells5jWIROT0H/RGk64ds4eiKskWxwG9p8K8s # wCLdgadf/PRnKmMLR3i5gMX87Db83nUtX/tEgoNxSGuvTdK/JRuqf2oMLv5AOF27 # 6573reJW1z0Ho9Se5JW+DPI18hX7YzqwyJQ9QslGOSRXJb20O4iC2rICfI8MeFsW # tBTsBcJ4qwsVK4nqY/3Tz57lhZLF2xYZtdgvxS4urqg/PrcbAMq8SSB8cq7tjUUs # sgDMQQx4n/r8wlBJE1nnvF/NxtLyTj/rrS9J1rF7ztp/suea/vHxM3t9vTqjLSlY # TyFORcfSCK2edp2+QwARJTTU9FlnuSwf28Pnm2lMQjp5HjBO20bpCBIWGQl6C9A= # =T88Y # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Nov 2023 02:43:02 EST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [full] # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: net: do not delete nics in net_cleanup() net: Update MemReentrancyGuard for NIC net: Provide MemReentrancyGuard * to qemu_new_nic() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-21net: Provide MemReentrancyGuard * to qemu_new_nic()Akihiko Odaki
Recently MemReentrancyGuard was added to DeviceState to record that the device is engaging in I/O. The network device backend needs to update it when delivering a packet to a device. In preparation for such a change, add MemReentrancyGuard * as a parameter of qemu_new_nic(). Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-11-21ppc/pnv: Fix PNV I2C invalid status after resetGlenn Miles
The PNV I2C Controller was clearing the status register after a reset without repopulating the "upper threshold for I2C ports", "Command Complete" and the SCL/SDA input level fields. Fixed this for resets caused by a system reset as well as from writing to the "Immediate Reset" register. Fixes: 263b81ee15af ("ppc/pnv: Add an I2C controller model") Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-11-21ppc/pnv: PNV I2C engines assigned incorrect XSCOM addressesGlenn Miles
The PNV I2C engines for power9 and power10 were being assigned a base XSCOM address that was off by one I2C engine's address range such that engine 0 had engine 1's address and so on. The xscom address assignment was being based on the device tree engine numbering, which starts at 1. Rather than changing the device tree numbering to start with 0, the addressing was changed to be based on the existing device tree numbers minus one. Fixes: 1ceda19c28a1 ("ppc/pnv: Connect PNV I2C controller to powernv10) Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-11-21ppc/pnv: Fix potential overflow in I2C modelCédric Le Goater
Coverity warns that "i2c_bus_busy(i2c->busses[i]) << i" might overflow because the expression is evaluated using 32-bit arithmetic and then used in a context expecting a uint64_t. While we are at it, introduce a PNV_I2C_MAX_BUSSES constant and check the number of busses at realize time. Fixes: Coverity CID 1523918 Cc: Glenn Miles <milesg@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-11-20hw/arm/fsl-imx: Do not ignore Error argumentPhilippe Mathieu-Daudé
Both i.MX25 and i.MX6 SoC models ignore the Error argument when setting the PHY number. Pick &error_abort which is the error used by the i.MX7 SoC (see commit 1f7197deb0 "ability to change the FEC PHY on i.MX7 processor"). Fixes: 74c1330582 ("ability to change the FEC PHY on i.MX25 processor") Fixes: a9c167a3c4 ("ability to change the FEC PHY on i.MX6 processor") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231120115116.76858-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/arm/stm32f100: Report error when incorrect CPU is usedPhilippe Mathieu-Daudé
The 'stm32vldiscovery' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231117071704.35040-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/arm/stm32f205: Report error when incorrect CPU is usedPhilippe Mathieu-Daudé
The 'netduino2' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-arm -M netduino2 -cpu cortex-a9 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-arm -M netduino2 -cpu cortex-a9 qemu-system-arm: Invalid CPU type: cortex-a9-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231117071704.35040-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/arm/stm32f405: Report error when incorrect CPU is usedPhilippe Mathieu-Daudé
Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M4 CPU: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu The valid types are: cortex-m4-arm-cpu Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231117071704.35040-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/core/machine: Constify MachineClass::valid_cpu_types[]Gavin Shan
Constify MachineClass::valid_cpu_types[i], as suggested by Richard Henderson. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231117071704.35040-2-philmd@linaro.org [PMD: Constify HPPA machines, restrict valid_cpu_types to machine_class_init() handlers] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZBen Dooks
The ICC_PMR_ELx and ICV_PMR_ELx bit masks returned from ic{c,v}_fullprio_mask should technically also remove any bit above 7 as these are marked reserved (read 0) and should therefore should not be written as anything other than 0. This was noted during a run of a proprietary test system and discused on the mailing list [1] and initially thought not to be an issue due to RES0 being technically allowed to be written to and read back as long as the implementation does not use the RES0 bits. It is very possible that the values are used in comparison without masking, as pointed out by Peter in [2], if (cs->hppi.prio >= cs->icc_pmr_el1) may well do the wrong thing. Masking these values in ic{c,v}_fullprio_mask() should fix this and prevent any future problems with playing with the values. [1]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00607.html [2]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00737.html Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Message-id: 20231116172818.792364-1-ben.dooks@codethink.co.uk Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20Merge tag 'pull-error-2023-11-17' of https://repo.or.cz/qemu/armbru into stagingStefan Hajnoczi
Error reporting patches for 2023-11-17 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmVXLq8SHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTBIsP/3vTjS2QJ2JdjgZV7ARGyfAxsPbG4TS2 # JHqFsF37vY5u+gYjcBJsmDY8YBpYWQFkOYJ8RJtCdedOnW2gML88vc3XKcUrUc7T # ebN8KnpA8mx5nr0SMGD+/w72xZl917lGFhXRqazvS2i0dbJvuAsacoo300oIZncx # 5480GiJpNc/QBUdU9ywFWwQOVzJynn32e1OFWLmbL2xH+kcgMbgWgrEMQUb0D99+ # J9PjKCJxVlJFKEjph7iLCahID5V1gjJTzp3iESOWbO7BTFuKJZ8E510oXd1ng86c # JLOEcu4vhC4JNvMx5R31nVz4LXfQD8Hf1pSVL64gTybVq3bEMhv/wLUuG/AcPIuL # t1GxRhGqY2yXbnP3GfP9xNhFps0uLmJF7g5Q/ao2sEwOiPmGmNKcK7xV6OkYJdIr # isbb+bot19NN+B7r1ZWkb7BEhM99PtHZtsrmnPZ7T19CX/cy2k0D0W78nqJE0AJU # sBhwuntou+DvBbLB3KD33OcE0UI93IxICaqR56q4lwydYOQ4p8VCTRI1aoDrZpPx # Q+kMs+sy3q7CGMKEScnb+HeA8KuvKFGqw3XKJwYQsTITRd+NdWnQ7dKAC2J2sRvO # DRGhUEmOiaDv3HdmToV3owfLsH9raK6Oh8KYjxiOoiJ1Tb0+sZvxayemQ97mRVuJ # r+yle/BX1ODY # =7QAS # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Nov 2023 04:13:19 EST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-error-2023-11-17' of https://repo.or.cz/qemu/armbru: target/i386/cpu: Improve error message for property "vendor" balloon: Fix a misleading error message net: Fix a misleading error message ui/qmp-cmds: Improve two error messages qga: Improve guest-exec-status error message hmp: Improve sync-profile error message spapr/pci: Correct "does not support hotplugging error messages Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-17spapr/pci: Correct "does not support hotplugging error messagesMarkus Armbruster
When dynamic-reconfiguration is off, hot plug / unplug can fail with "Bus 'spapr-pci-host-bridge' does not support hotplugging". spapr-pci-host-bridge is a device, not a bus. Report the name of the bus it provides instead: 'pci.0'. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20231031111059.3407803-2-armbru@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-15hw/net/cadence_gem.c: spelling fixes: OctectsMichael Tokarev
Fixes: c755c943aa2e "hw/net/cadence_gem: use REG32 macro for register definitions" Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-15hw/mem/memory-device.c: spelling fix: ontainingMichael Tokarev
Fixes: 6c1b28e9e405 "memory-device: Support empty memory devices" Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-15hw/cxl: spelling fixes: limitaions, potentialy, intializedMichael Tokarev
Fixes: 388d6b574e28 "hw/cxl: Use switch statements for read and write of cachemem registers" Fixes: 3314efd276ad "hw/cxl/mbox: Add Physical Switch Identify command." Fixes: 004e3a93b814 "hw/cxl: Add tunneled command support to mailbox for switch cci." Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-15hw/audio/virtio-snd.c: spelling: initalizeMichael Tokarev
Fixes: eb9ad377bb94 "virtio-sound: handle control messages and streams" Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-15hw/watchdog/wdt_aspeed: Remove unused 'hw/misc/aspeed_scu.h' headerPhilippe Mathieu-Daudé
Aspeed watchdog doesn't use anything from the System Control Unit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-14Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingStefan Hajnoczi
# -----BEGIN PGP SIGNATURE----- # Version: GnuPG v1 # # iQEcBAABAgAGBQJlUt3jAAoJEO8Ells5jWIRX30H/iATyz+77w3Zd2rVfOpyHLhM # lgvhTwVCltsWdZSZLu6zrLYh419NNcAOyb9/Ci7hKR+x4OmWbP6pme772LRH2Mhz # zWzVoMXJeW1unjGvBcA8eAIsu3PUKoHLQ1J2dNwHheupMb2LkrWMaEMj10605aZ9 # WnjCFRIiejq4s2JGhofDTa0GCHcFmq2/Nzghb6MMzdPa99QTFnPmYRdIg2bGWd4L # PmoueuiA/zoDZjx+Y1nC2IzXRq7SvFIAyz91J/zaUtZLD+7QKV/bP+JACTnyzhOY # coUZnVzFc7q0Gv9wjw2oTNQo5CgKDyw7aDUB8oWsQLR1UvqEICbMhhz29YCWhok= # =10qX # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Nov 2023 21:39:31 EST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [full] # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: igb: Add Function Level Reset to PF and VF igb: Add a VF reset handler Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-14Merge tag 'misc-fixes-20231113' of https://github.com/philmd/qemu into stagingStefan Hajnoczi
Misc fixes for 8.2 - Missing Kconfig dependency in hw/mips (Marc-André) - Typo in VMWare model (Alexandra) - New avocado test for x86 processors addressing (Ani) - Fix SyntaxWarnings in avocado (Thomas) - Update virtio-fs mailing list address in MAINTAINERS (Stefan) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVSaAwACgkQ4+MsLN6t # wN7L9RAAvlX5MKJe6d3+gYV8NciEYFQGWzgSjtc0IzRenYf1wvxXubFnmeTJ3kfF # VOugAmeQUx5xvD0iPNrYCFn5fb1ZIFDuES25TsUSN38GCfo1/1+pG+wBWPJRwnQg # LhRHLSzwJOiUSzOEWrVW/4f2TUM1svUM7WKAWB1AbO2Dd3BKzb25/AEdgYWCeQKV # xrBFUH/owNCnWHxIFfLEO8Gt2WGkCLgblvLpeu5Mzds/5JcAi1Fb9lgpvvYxB1Jk # Jgb2ic4Lp6+aTxYxS/+EbQcZciM1M7XXVN57xsQZEcave5CQ9fN8dMbTy3GJxEfJ # OqWzLbwxybQCDA2f2Kd0HEv+U828ZD6/8HDfFk1JmZjE8UJ9vsvdnhQDDJOn5VJu # INyupPsgaG86jaQavzAQJ7Cehe4SdEX0B11mdPfujooy4FvO79O8AzlMM2YG8ARn # YydUzc1RnzE9l67RuEPvqiw1htpjJwV32v7nNZzsoBpqHG5OXAAD732OYnu/30a0 # U73tApRwPDUX3kiS8kUvXLq4/2NxFbX5VDx1bcJPTsweGplr59tPzMRpRxKQGhwa # WEsjjqnDNEjYVzTMVfFRQlvDUkcr5Rrgd51Q3MDbm6inCf2JofT4m7UmvFVmOW3p # w7IAbiguwyxC+Us9AkPTh03FYlzT2B+3XhKbAxcYJZ5/oH1O3x8= # =SFhl # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Nov 2023 13:16:44 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'misc-fixes-20231113' of https://github.com/philmd/qemu: MAINTAINERS: update virtio-fs mailing list address tests/avocado/machine_s390_ccw_virtio.py: Fix SyntaxWarnings from python 3.12 tests/avocado: add test to exercise processor address space memory bound checks hw/display/vmware_vga: fix probably typo hw/mips: LOONGSON3V depends on UNIMP device Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-14Merge tag 'pull-target-arm-20231113' of ↵Stefan Hajnoczi
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm/virt: fix GIC maintenance IRQ registration * target/arm: HVC at EL3 should go to EL3, not EL2 * target/arm: Correct MTE tag checking for reverse-copy MOPS * target/arm/tcg: enable PMU feature for Cortex-A8 and A9 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVSYL0ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3iLND/99dZKHgNJx1k7aeGX8t4lU # MTU0AsFndpx/WjWbviyfrO17B0FIi6kwhggDk2cXrXF26eBFcx5ruJ6sw9R1ZvsV # y6Z1rhjd+skj3PMxGMU/I0XeR3TXJNo2eLAeKyPy4W75+5I0zT4PMEPJ05WylVTs # RXuAhlyCXX9uTT2ILtGRiThpRrgnzGE3DU2Ry32s0+qjYq5U89J0+0kYPg6VFg29 # Lfj4zCwVu3/xX7Me+b84bTDxlQD4LSGdibscd0aCiMyamzfLl/naoDLvFIia/Q7h # 4epcw3Bu+3nTicg70i9k6iNP4nDXPO9V2dbopJVd9wcgPBXicyoDrLA8CQdp+04v # /vHT9+IZ4pFUcUp1+A9s6CcSMDeYOSPrQsd96HwaTtw/RjpxhLKC6EEpswpr5d4q # SBU5I6lUe47HuwLxPpqucwNk/o4/9PZKBDSI1SUKoLPVyOvSS0sxJlTdQCyHCgmU # ogjnFnw9J16X/GOWzS3tUD+9GS8s7WqJHyFl0t5ngvvamFTdquPFSFXQfZMTwAU1 # vVSam4oi51ON2sVjkR7Pn7BrTBE1QnsudB8Sc9If/LGhFSuNUKlj13+pWrGMty+n # q9fFS5MuNlvVehX3mr+i4PA6WWYCZ0wHzTvXtYxKkyu1CZi53r9H1pZPwb6URjUt # ceyJngaQH5dgtkVgCNSoRQ== # =4D8I # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Nov 2023 12:45:33 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20231113' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm/tcg: enable PMU feature for Cortex-A8 and A9 target/arm: Correct MTE tag checking for reverse-copy MOPS target/arm: HVC at EL3 should go to EL3, not EL2 hw/arm/virt: fix GIC maintenance IRQ registration Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-14Merge tag 'pull-pa-20231113' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
target/hppa: Mask reserved PSW bits in expand_sm_imm target/hppa: Fix calculation of CR_IIASQ back register target/hppa: Fix possible overflow in TLB size calculation target/hppa: Fix probe instruction target/hppa: Split MMU_PHYS_IDX to MMU_ABS_IDX, MMU_ABS_W_IDX target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40 hw/pci-host/astro: Translate 32-bit pci onto 40-bit runway bus hw/hppa: Update SeaBIOS-hppa to version 12 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVSXR4dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV87qwf+MkEuvMiwqx9YB2qa # Yhn4m4H1DrQcqGJ2egGuiYrS45JCAUZUcXnmBxL//w3AW7hoeoZwmuFSj+I3EOhI # y6ykMjMAe8d0VpWEvdkRh7SAWPBKvCJiAclkNyZkYhhagXryiFxqo9tL6nNQQEyz # HaYzrDwqL+Qgh7/ahkA9XdVLdeTsMtXoLm1cCXpY+TL0MiQonBa1mc17vbyWN8hs # qWQFBtik0lBIuEN0cB0bUgvV1oH9B8KVUYKbx/RhQORQAiU/O2SaSZ0fxU+F8ynB # xIyQH6aik0pzgwSo25T/AMxxgUoDydvLDyLCu/R85eNmdgvOj+n4XGIiNEJKEltT # 1OwGSQ== # =Qcsh # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Nov 2023 12:30:06 EST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-pa-20231113' of https://gitlab.com/rth7680/qemu: hw/hppa: Require at least SeaBIOS-hppa version 12 target/hppa: Update to SeaBIOS-hppa from version 10 to 12 hw/hppa: Move software power button address to page zero hw/pci-host/astro: Fix boot for C3700 machine target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40 target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX target/hppa: Introduce MMU_IDX_MMU_DISABLED target/hppa: Fix possible overflow in TLB size calculation target/hppa: Fix calculation of CR_IIASQ back register target/hppa: Use PRIV_P_TO_MMU_IDX in helper_probe target/hppa: Use only low 2 immediate bits for PROBEI target/hppa: Mask reserved PSW bits in expand_sm_imm Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-13hw/hppa: Require at least SeaBIOS-hppa version 12Helge Deller
The new SeaBIOS-hppa version 12 includes the necessary fixes to support emulated PA2.0 CPUs and which allows starting 64-bit Linux kernels in the guest. To boot a 64-bit machine use the "-machine C3700" qemu option. Signed-off-by: Helge Deller <deller@gmx.de> Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13hw/hppa: Move software power button address to page zeroHelge Deller
Something appears to be off between the 64-bit CPU, the 32-bit PDC (SeaBIOS-hppa firmware), and the 64-bit kernel in addressing the power button address in high-mapped firmware memory. Use a 32-bit value at PAGE0->pad0[4] instead. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13hw/pci-host/astro: Fix boot for C3700 machineHelge Deller
Apply the "32-bit PCI addressing on 40-bit Runway" as the default iommu transformation. This allows PCI devices to dma PDC memory. Signed-off-by: Helge Deller <deller@gmx.de> Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13hw/display/vmware_vga: fix probably typoAlexandra Diupina
When calling trace_vmware_verify_rect_greater_than_bound() replace "y" with "h" and y with h Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 02218aedb1 ("hw/display/vmware_vga: replace fprintf calls with trace events") Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231110174104.13280-1-adiupina@astralinux.ru> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-13hw/mips: LOONGSON3V depends on UNIMP deviceMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Cc: qemu-stable@nongnu.org Fixes: c76b409fef ("hw/mips: Add Loongson-3 machine support") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231107140615.3034763-1-marcandre.lureau@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-13hw/arm/virt: fix GIC maintenance IRQ registrationJean-Philippe Brucker
Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"), GIC maintenance IRQ registration fails on arm64: [ 0.979743] kvm [1]: Cannot register interrupt 9 That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case where the maintenance IRQ is actually referred by its PPI index. Just like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there shouldn't be more similar issues. Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20231110090557.3219206-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-13Merge tag 'pull-request-2023-11-13' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi
staging * Fix compilation with Clang 17 on s390x hosts * Two small s390x PCI fixes * Update MAINTAINERS file with more entries * Fix NetBSD VM test * Clean up some bad wordings # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVSAoIRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVXBg//VVZS5CXEfOFV91I1kqQnLCvgwmuAyqEg # PI2/HBxuhzeBx+F1t7uR0n15tUPi1zkFFBOpyBDBubvWcp4vGvFwLQoiBCUvNzBA # +b1vMySP+K0OO1X5yT3cFHXF9q0o0V5WADwemf5RglIPjlTOIiz9qhD4EYqd2QHC # EUd9Y45DP4Y0V5raHLjY990f/zr3PuSAB6MASFTUnKdgGkRqonLWdLDdIZNDrZuL # oGwx1ALXgBOMV3yNyQx9jZBT24git/ai1vd9AU/d3JRKDPsd+4vC39+PTI9NH4h6 # oQglvo399f64cir1f1JJ3MN4ZtwXZpwUkjeTMcR9XZxk7GibU7P2arG5M3TERdmE # VLqylYsnbJojWOeCH+TViJapRhg1CzUveVlQofr7GHvf2N3oy3BrKaV715gauEyW # zpjbhSPpIQu9WFXt8+tSquqbvpAP/VlLrOV73D4LzJ7WdTa9CHmSek8D0zoRQDZR # 8OixrgoBKS+pmBDmTve5gFsIKhZIz9CrmaAKKYdskC8blENxCng8LOFp7sg2PK3M # U0lWYoDS7qZ85761Bl+QaBdFocdahQqkO/LUQuhoSt2OvA1EGAz2FdVSKkmPDdSS # P/homr4hOXIqJFSsZj0YNUTIXsXwLBvKjvcJPAWYgbXZhim0LtPQTQO3+ignwGyu # RXjaVkvkf/s= # =+2rp # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Nov 2023 06:03:30 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-11-13' of https://gitlab.com/thuth/qemu: hw/audio/es1370: Clean up comment tests/tsan: Rename the file with the entries that should be ignored test-resv-mem: Fix CID 1523911 tests/vm/netbsd: Use Python v3.11 MAINTAINERS: Add a general architecture section for x86 MAINTAINERS: Extend the Stellaris section MAINTAINERS: Add hw/display/sii9022.c to the Versatile Express section MAINTAINERS: Add hw/input/ads7846.c to the PXA2XX section MAINTAINERS: Add include/hw/input/pl050.h to the PrimeCell/CMSDK section s390x/pci: only limit DMA aperture if vfio DMA limit reported s390x/pci: bypass vfio DMA counting when using cdev host/include/generic/host/atomic128: Fix compilation problem with Clang 17 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-13hw/audio/es1370: Clean up commentPeter Maydell
Replace a sweary comment with one that's a bit more helpful to future readers of the code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Volker Rümelin <vr_qemu@t-online.de> Message-ID: <20231110164318.2197569-1-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-13s390x/pci: only limit DMA aperture if vfio DMA limit reportedMatthew Rosato
If the host kernel lacks vfio DMA limit reporting, do not attempt to shrink the guest DMA aperture. Fixes: df202e3ff3 ("s390x/pci: shrink DMA aperture to be bound by vfio DMA limit") Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Message-ID: <20231110175108.465851-3-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-13s390x/pci: bypass vfio DMA counting when using cdevMatthew Rosato
The current code assumes that there is always a vfio group, but that's no longer guaranteed with the iommufd backend when using cdev. In this case, we don't need to track the vfio dma limit anyway. Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Message-ID: <20231110175108.465851-2-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-13virtio-mem: fix division by zero in virtio_mem_activate_memslots_to_plug()David Hildenbrand
When running with "dynamic-memslots=off", we enter virtio_mem_activate_memslots_to_plug() to return immediately again because "vmem->dynamic_memslots == false". However, the compiler might not optimize out calculating start_idx+end_idx, where we divide by vmem->memslot_size. In such a configuration, the memslot size is 0 and we'll get a division by zero: (qemu) qom-set vmem0 requested-size 3G (qemu) q35.sh: line 38: 622940 Floating point exception(core dumped) The same is true for virtio_mem_deactivate_unplugged_memslots(), however we never really reach that code without a prior virtio_mem_activate_memslots_to_plug() call. Let's fix it by simply calling these functions only with "dynamic-memslots=on". This was found when using a debug build of QEMU. Message-ID: <20231023111341.219317-1-david@redhat.com> Reprted-by: Mario Casquero <mcasquer@redhat.com> Fixes: 177f9b1ee464 ("virtio-mem: Expose device memory dynamically via multiple memslots if enabled") Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Tested-by: Mario Casquero <mcasquer@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2023-11-13igb: Add Function Level Reset to PF and VFCédric Le Goater
The Intel 82576EB GbE Controller say that the Physical and Virtual Functions support Function Level Reset. Add the capability to the PF device model using device property "x-pcie-flr-init" which is "on" by default and "off" for machines <= 8.1 to preserve compatibility. The FLR capability of the VF model is defined according to the FLR property of the PF, this to avoid adding an extra compatibility property. Cc: Sriram Yagnaraman <sriram.yagnaraman@est.tech> Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-11-13igb: Add a VF reset handlerCédric Le Goater
Export the igb_vf_reset() helper routine from the PF model to let the IGBVF model implement its own device reset. Cc: Akihiko Odaki <akihiko.odaki@daynix.com> Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-11-10qdev: Rework array properties based on list visitorKevin Wolf
Until now, array properties are actually implemented with a hack that uses multiple properties on the QOM level: a static "foo-len" property and after it is set, dynamically created "foo[i]" properties. In external interfaces (-device on the command line and device_add in QMP), this interface was broken by commit f3558b1b ('qdev: Base object creation on QDict rather than QemuOpts') because QDicts are unordered and therefore it could happen that QEMU tried to set the indexed properties before setting the length, which fails and effectively makes array properties inaccessible. In particular, this affects the 'ports' property of the 'rocker' device, which used to be configured like this: -device rocker,len-ports=2,ports[0]=dev0,ports[1]=dev1 This patch reworks the external interface so that instead of using a separate top-level property for the length and for each element, we use a single true array property that accepts a list value. In the external interfaces, this is naturally expressed as a JSON list and makes array properties accessible again. The new syntax looks like this: -device '{"driver":"rocker","ports":["dev0","dev1"]}' Creating an array property on the command line without using JSON format is currently not possible. This could be fixed by switching from QemuOpts to a keyval parser, which however requires consideration of the compatibility implications. All internal users of devices with array properties go through qdev_prop_set_array() at this point, so updating it takes care of all of them. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1090 Fixes: f3558b1b763683bb877f7dd5b282469cdadc65c3 Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20231109174240.72376-12-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-10qdev: Make netdev properties work as list elementsKevin Wolf
The 'name' parameter of QOM setters is primarily used to specify the name of the currently parsed input element in the visitor interface. For top-level qdev properties, this is always set and matches 'prop->name'. However, for list elements it is NULL, because each element of a list doesn't have a separate name. Passing a non-NULL value runs into assertion failures in the visitor code. Therefore, using 'name' in error messages is not right for property types that are used in lists, because "(null)" (or even a segfault) isn't very helpful to identify what QEMU is complaining about. Change netdev properties to use 'prop->name' instead, which will contain the name of the array property after switching array properties to lists in the external interface. (This is still not perfect, as it doesn't identify which element in the list caused the error, but strictly better than before.) Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20231109174240.72376-11-kwolf@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-10hw/rx/rx62n: Use qdev_prop_set_array()Kevin Wolf
Instead of manually setting "foo-len" and "foo[i]" properties, build a QList and use the new qdev_prop_set_array() helper to set the whole array property with a single call. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231109174240.72376-9-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-10hw/arm/xlnx-versal: Use qdev_prop_set_array()Kevin Wolf
Instead of manually setting "foo-len" and "foo[i]" properties, build a QList and use the new qdev_prop_set_array() helper to set the whole array property with a single call. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20231109174240.72376-8-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-10hw/arm/virt: Use qdev_prop_set_array()Kevin Wolf
Instead of manually setting "foo-len" and "foo[i]" properties, build a QList and use the new qdev_prop_set_array() helper to set the whole array property with a single call. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20231109174240.72376-7-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-10hw/arm/vexpress: Use qdev_prop_set_array()Kevin Wolf
Instead of manually setting "foo-len" and "foo[i]" properties, build a QList and use the new qdev_prop_set_array() helper to set the whole array property with a single call. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20231109174240.72376-6-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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