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2021-03-06hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board typePeter Maydell
In the mps2-tz board code, we handle devices whose interrupt lines must be wired to all CPUs by creating IRQ splitter devices for the AN521, because it has 2 CPUs, but wiring the device IRQ directly to the SSE/IoTKit input for the AN505, which has only 1 CPU. We can avoid making an explicit check on the board type constant by instead creating and using the IRQ splitters for any board with more than 1 CPU. This avoids having to add extra cases to the conditionals every time we add new boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-9-peter.maydell@linaro.org
2021-03-06hw/arm/mps2-tz: Make FPGAIO switch and LED config per-boardPeter Maydell
Set the FPGAIO num-leds and have-switches properties explicitly per-board, rather than relying on the defaults. The AN505 and AN521 both have the same settings as the default values, but the AN524 will be different. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-8-peter.maydell@linaro.org
2021-03-06hw/misc/mps2-fpgaio: Support SWITCH registerPeter Maydell
MPS3 boards have an extra SWITCH register in the FPGAIO block which reports the value of some switches. Implement this, governed by a property the board code can use to specify whether whether it exists. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-7-peter.maydell@linaro.org
2021-03-06hw/misc/mps2-fpgaio: Make number of LEDs configurable by boardPeter Maydell
The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The FPGAIO device is similar on both sets of boards, but the LED0 register has correspondingly more bits that have an effect. Add a device property for number of LEDs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-6-peter.maydell@linaro.org
2021-03-06hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-boardPeter Maydell
The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-5-peter.maydell@linaro.org
2021-03-06hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511Peter Maydell
We were previously using the default OSCCLK settings, which are correct for the older MPS2 boards (mps2-an385, mps2-an386, mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511 implemented in mps2-tz.c. Now we're setting the values explicitly we can fix them to be correct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-4-peter.maydell@linaro.org
2021-03-06hw/misc/mps2-scc: Support configurable number of OSCCLK valuesPeter Maydell
Currently the MPS2 SCC device implements a fixed number of OSCCLK values (3). The variant of this device in the MPS3 AN524 board has 6 OSCCLK values. Switch to using a PROP_ARRAY, which allows board code to specify how large the OSCCLK array should be as well as its values. With a variable-length property array, the SCC no longer specifies default values for the OSCCLKs, so we must set them explicitly in the board code. This defaults are actually incorrect for the an521 and an505; we will correct this bug in a following patch. This is a migration compatibility break for all the mps boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-3-peter.maydell@linaro.org
2021-03-06hw/arm/mps2-tz: Make SYSCLK frequency board-specificPeter Maydell
The AN524 has a different SYSCLK frequency from the AN505 and AN521; make the SYSCLK frequency a field in the MPS2TZMachineClass rather than a compile-time constant so we can support the AN524. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-2-peter.maydell@linaro.org
2021-03-06hw/display/tcx: Drop unnecessary code for handling BGR format outputsPeter Maydell
For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel, RGB. The TCX code already assumes 32bpp, but it still has some checks of is_surface_bgr() in an attempt to support 32bpp BGR. is_surface_bgr() will always return false for the qemu_console_surface(), unless the display device itself has deliberately created an alternate-format surface via a function like qemu_create_displaysurface_from(). Drop the never-used BGR-handling code, and assert that we have a 32-bit surface rather than just doing nothing if it isn't. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215102149.20513-1-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Delete unnecessary macroPeter Maydell
The macro draw_line_func is used only once; just expand it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-10-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Inline template header into C filePeter Maydell
We only include the template header once, so just inline it into the source file for the device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-9-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Fix coding style issues in template headerPeter Maydell
Fix some minor coding style issues in the template header, so checkpatch doesn't complain when we move the code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-8-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Drop broken bigendian ifdefPeter Maydell
The draw_line16_32() function in the omap_lcdc template header includes an ifdef for the case where HOST_WORDS_BIGENDIAN matches TARGET_WORDS_BIGENDIAN. This is trying to optimise for "source bitmap and destination bitmap format match", but it is broken, because in this function the formats don't match: the source is 16-bit colour and the destination is 32-bit colour, so a memcpy() will produce corrupted graphics output. Drop the bogus ifdef. This bug was introduced in commit ea644cf343129, when we dropped support for DEPTH values other than 32 from the template header. The old #if line was #if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) and this was mistakenly changed to #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) rather than deleting the #if as now having an always-false condition. Fixes: ea644cf343129 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-7-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Expand out macros in template headerPeter Maydell
The omap_lcdc template header is already only included once, for DEPTH==32, but it still has all the macro-driven parameterization for other depths. Expand out all the macros in the header. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-6-peter.maydell@linaro.org
2021-03-06hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsitePeter Maydell
The function tc6393xb_draw_graphic32() is called in exactly one place, so just inline the function body at its callsite. This allows us to drop the template header entirely. The code move includes a single added space after 'for' to fix the coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-5-peter.maydell@linaro.org
2021-03-06hw/display/tc6393xb: Expand out macros in template headerPeter Maydell
Now the template header is included only for BITS==32, expand out all the macros that depended on the BITS setting. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-4-peter.maydell@linaro.org
2021-03-05hw/display/tc6393xb: Remove dead code for handling non-32bpp surfacesPeter Maydell
For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB. Remove the legacy dead code from the tc6393xb display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-3-peter.maydell@linaro.org
2021-03-05hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfacesPeter Maydell
For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB. Remove the legacy dead code from the milkymist display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-2-peter.maydell@linaro.org
2021-03-05virtio-mmio: improve virtio-mmio get_dev_path alogschspa
At the moment the following QEMU command line triggers an assertion failure On xlnx-versal SOC: qemu-system-aarch64 \ -machine xlnx-versal-virt -nographic -smp 2 -m 128 \ -fsdev local,id=shareid,path=${HOME}/work,security_model=none \ -device virtio-9p-device,fsdev=shareid,mount_tag=share \ -fsdev local,id=shareid1,path=${HOME}/Music,security_model=none \ -device virtio-9p-device,fsdev=shareid1,mount_tag=share1 qemu-system-aarch64: ../migration/savevm.c:860: vmstate_register_with_alias_id: Assertion `!se->compat || se->instance_id == 0' failed. This problem was fixed on arm virt platform in commit f58b39d2d5b ("virtio-mmio: format transport base address in BusClass.get_dev_path") It works perfectly on arm virt platform. but there is still there on xlnx-versal SOC. The main difference between arm virt and xlnx-versal is they use different way to create virtio-mmio qdev. on arm virt, it calls sysbus_create_simple("virtio-mmio", base, pic[irq]); which will call sysbus_mmio_map internally and assign base address to subsys device mmio correctly. but xlnx-versal's implements won't do this. However, xlnx-versal can't switch to sysbus_create_simple() to create virtio-mmio device. It's because xlnx-versal's cpu use VersalVirt.soc.fpd.apu.mr as it's memory. which is subregion of system_memory. sysbus_create_simple will add virtio to system_memory, which can't be accessed by cpu. Besides, xlnx-versal can't add sysbus_mmio_map api call too, because this will add memory region to system_memory, and it can't be added to VersalVirt.soc.fpd.apu.mr again. We can solve this by assign correct base address offset on dev_path. This path was test on aarch64 virt & xlnx-versal platform. Signed-off-by: schspa <schspa@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init()Philippe Mathieu-Daudé
The STATUS register will be reset to IDLE in cnpcm7xx_smbus_enter_reset(), no need to preset it in instance_init(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210228224813.312532-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' propertyPhilippe Mathieu-Daudé
We hint the 'has_rpu' property is no longer required since commit 6908ec448b4 ("xlnx-zynqmp: Properly support the smp command line option") which was released in QEMU v2.11.0. Beside, this device is marked 'user_creatable = false', so the only thing that could be setting the property is the board code that creates the device. Since the property is not user-facing, we can remove it without going through the deprecation process. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210219144350.1979905-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05hw/arm: Add npcm7xx emc modelDoug Evans
This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-3-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05hw/net: Add npcm7xx emc modelDoug Evans
This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-2-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05sbsa-ref: add 'max' to list of allowed cpusMarcin Juszkiewicz
Let add 'max' cpu while work goes on adding newer CPU types than Cortex-A72. This allows us to check SVE etc support. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Acked-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210216150122.3830863-3-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05sbsa-ref: remove cortex-a53 from list of supported cpusMarcin Juszkiewicz
Cortex-A53 supports 40bits of address space. sbsa-ref's memory starts above this limit. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Leif Lindholm <leif@nuviainc.com> Message-id: 20210216150122.3830863-2-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging RISC-V PR for 6.0 This PR is a collection of RISC-V patches: - Improvements to SiFive U OTP - Upgrade OpenSBI to v0.9 - Support the QMP dump-guest-memory - Add support for the SiFive SPI controller (sifive_u) - Initial RISC-V system documentation - A fix for the Goldfish RTC - MAINTAINERS updates - Support for high PCIe memory in the virt machine # gpg: Signature made Thu 04 Mar 2021 14:44:31 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210304: hw/riscv: virt: Map high mmio for PCIe hw/riscv: virt: Limit RAM size in a 32-bit system hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() hw/riscv: Drop 'struct MemmapEntry' MAINTAINERS: Add a SiFive machine section goldfish_rtc: re-arm the alarm after migration docs/system: riscv: Add documentation for sifive_u machine docs/system: Add RISC-V documentation docs/system: Sort targets in alphabetical order hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card hw/riscv: sifive_u: Add QSPI0 controller and connect a flash hw/ssi: Add SiFive SPI controller support hw/block: m25p80: Add various ISSI flash information hw/block: m25p80: Add ISSI SPI flash support target-riscv: support QMP dump-guest-memory roms/opensbi: Upgrade from v0.8 to v0.9 hw/misc: sifive_u_otp: Use error_report() when block operation fails target/riscv: Declare csr_ops[] with a known size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng
Some peripherals require 64-bit PCI address, so let's map the high mmio space for PCIe. For RV32, the address is hardcoded to below 4 GiB from the highest accessible physical address. For RV64, the base address depends on top of RAM and is aligned to its size which is using 16 GiB for now. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng
RV32 supports 34-bit physical address hence the maximum RAM size should be limited. Limit the RAM size to 10 GiB, which leaves some room for PCIe high mmio space. For 32-bit host, this is not needed as machine->ram_size cannot represent a RAM size that big. Use a #if size test to only do the size limitation for the 64-bit host. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng
`link_up` is never used in gpex_pcie_init(). Drop it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210220144807.819-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04goldfish_rtc: re-arm the alarm after migrationLaurent Vivier
After a migration the clock offset is updated, but we also need to re-arm the alarm if needed. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201220112615.933036-7-laurent@vivier.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng
This adds the QSPI2 controller to the SoC, and connects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed board. Note subsequent payload is stored in the SD card image. $ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=sdcard.img,if=sd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng
This adds the QSPI0 controller to the SoC, and connects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. Since the direct memory-mapped mode is not supported by the SiFive SPI model, the <reg> property does not populate the second group which represents the memory mapped address of the SPI flash. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to L2LIM, then U-Boot SPL loads the payload from SPI flash that is combined with OpenSBI fw_dynamic firmware and U-Boot proper. Specify machine property `msel` to 6 to allow booting from the SPI flash. U-Boot spl is directly loaded via `-bios`, and subsequent payload is stored in the SPI flash image. Example command line: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/ssi: Add SiFive SPI controller supportBin Meng
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/block: m25p80: Add various ISSI flash informationBin Meng
This updates the flash information table to include various ISSI flashes that are supported by upstream U-Boot and Linux kernel. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/block: m25p80: Add ISSI SPI flash supportBin Meng
This adds the ISSI SPI flash support. The number of dummy cycles in fast read, fast read dual output and fast read quad output commands is currently using the default 8. Likewise, the same default value is used for fast read dual/quad I/O command. Per the datasheet [1], the number of dummy cycles is configurable, but this is not modeled at present. For flash whose size is larger than 16 MiB, the sequence of 3-byte address along with EXTADD bit in the bank address register (BAR) is not supported. We assume that guest software always uses op codes with 4-byte address sequence. Fortunately, this is the case for both U-Boot and Linux spi-nor drivers. QPI (Quad Peripheral Interface) that supports 2-cycle instruction has different default values for dummy cycles of fast read family commands, and is unsupported at the time being. [1] http://www.issi.com/WW/pdf/25LP-WP256.pdf Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/misc: sifive_u_otp: Use error_report() when block operation failsBin Meng
At present when blk_pread() / blk_pwrite() fails, a guest error is logged, but this is not really a guest error. Change to use error_report() instead. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1611026585-29971-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210304-pull-request' ↵Peter Maydell
into staging ui/console: message surface tweaks. ui/cocoa: bugfixes and cleanups. # gpg: Signature made Thu 04 Mar 2021 08:36:53 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20210304-pull-request: virtio-gpu: Do not distinguish the primary console ui/console: Pass placeholder surface to displays ui/console: Add placeholder flag to message surface ui/cocoa: Replace fprintf with error_report configure: Improve OpenGL dependency detections ui/cocoa: Fix stride resolution of pixman image ui/gtk: vte: fix sending multiple characeters ui/cocoa: Remove the uses of full screen APIs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-04virtio-gpu: Do not distinguish the primary consoleAkihiko Odaki
In the past, virtio-gpu set NULL as the surface for the secondary consoles to hide its window. The distinction is now handled in ui/console and the display backends and virtio-gpu does no longer have to do that. Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <20210225101316.83940-3-akihiko.odaki@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-03-04ui/console: Add placeholder flag to message surfaceAkihiko Odaki
The surfaces created with former qemu_create_message_surface did not display the content from the guest and always contained simple messages describing the reason. A display backend may want to hide the window showing such a surface. This change renames the function to qemu_create_placeholder_surface, and adds "placeholder" flag; the display can check the flag to decide to do anything special like hiding the window. Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <20210225101316.83940-1-akihiko.odaki@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-03-03Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
pc,virtio,pci: bug fixes Fixes all over the place. Specifically this fixes a bug which made windows guests lose device config (such as the configured fixed IP) after upgrading to the new QEMU. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 02 Mar 2021 14:19:51 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: vhost: simplify vhost_dev_init() fail_busyloop label hw/pci: Have safer pcie_bus_realize() by checking error path virtio-net: handle zero mac for a vdpa peer i386/acpi: restore device paths for pre-5.1 vms Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-02Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging * fix --enable-fuzzing linker failures (Alexander) * target/i386: Add bus lock debug exception support (Chenyi) * update documentation for preferred boolean option syntax (Daniel) * make SCSI io_timeout configurable (Hannes) * fix handling of guest recoverable SCSI errors (myself) * misc fixes (Pavel, Zheng Zhan Liang, Zihao) * fix installation of binaries with entitlements (Akihiko) # gpg: Signature made Thu 25 Feb 2021 14:41:56 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (29 commits) tcg/i386: rdpmc: fix the the condtions chardev: do not use short form boolean options in non-QemuOpts character device descriptions vl: deprecate -writeconfig target/i386: Add bus lock debug exception support qom/object.c: Fix typo target/i386: update to show preferred boolean syntax for -cpu docs: update to show preferred boolean syntax for -cpu docs: update to show preferred boolean syntax for -vnc docs: update to show preferred boolean syntax for -chardev qemu-options: update to show preferred boolean syntax for -vnc qemu-options: update to show preferred boolean syntax for -incoming qemu-options: update to show preferred boolean syntax for -netdev qemu-options: update to show preferred boolean syntax for -spice qemu-options: update to show preferred boolean syntax for -chardev gdbstub: use preferred boolean option syntax char: don't fail when client is not connected scsi: drop 'result' argument from command_complete callback scsi-disk: pass guest recoverable errors through even for rerror=stop scsi-disk: pass SCSI status to scsi_handle_rw_error scsi: introduce scsi_sense_from_errno() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-02vhost: simplify vhost_dev_init() fail_busyloop labelStefan Hajnoczi
Requiring a conditional for every goto is tedious: if (busyloop_timeout) { goto fail_busyloop; } else { goto fail; } Move the conditional to into the fail_busyloop label so that it's safe to jump to this label unconditionally. This change makes the migrate_add_blocker() error case more consistent. It jumped to fail_busyloop unconditionally whereas the memslots limits error case was conditional. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20210222114931.272308-1-stefanha@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-03-02hw/pci: Have safer pcie_bus_realize() by checking error pathPhilippe Mathieu-Daudé
While pci_bus_realize() currently does not use the Error* argument, it would be an error to leave pcie_bus_realize() setting bus->flags if pci_bus_realize() had failed. Fix by using a local Error* and return early (propagating the error) if pci_bus_realize() failed. Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210201153700.618946-1-philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-03-02virtio-net: handle zero mac for a vdpa peerCindy Lu
Some mlx vdpa devices with kernels at least up to 5.11 currently present 0 as their MAC address. This is because they have not been pre-configured with a MAC: they have a learning bridge and only learn the MAC once guest is up. Kernel patches and tools to allow programming the MAC from host are being developed. For now - since these combinations exist in the field - let's detect zero mac and just try to proceed with the mac from the qemu command line. This makes the guest use this MAC to send packets in turn teaching the MAC to the card, and things work. TODO: report the actual MAC from QEMU commad line in the info message. TODO: detect that a (non-zero) hardware MAC does not match QEMU command line and fail init. Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20210225165506.18321-2-lulu@redhat.com> mst: rewritten code comments, message printed and the commit log. Cc: Eli Cohen <elic@nvidia.com> Cc: Parav Pandit <parav@nvidia.com> Tested-by: Adrian Moreno <amorenoz@redhat.com> Tested-by: Sean Mooney <smooney@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-03-02i386/acpi: restore device paths for pre-5.1 vmsVitaly Cheptsov
After fixing the _UID value for the primary PCI root bridge in af1b80ae it was discovered that this change updates Windows configuration in an incompatible way causing network configuration failure unless DHCP is used. More details provided on the list: https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg08484.html This change reverts the _UID update from 1 to 0 for q35 and i440fx VMs before version 5.2 to maintain the original behaviour when upgrading. Cc: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org Reported-by: Thomas Lamprecht <t.lamprecht@proxmox.com> Suggested-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru> Message-Id: <20210301195919.9333-1-cheptsov@ispras.ru> Tested-by: Thomas Lamprecht <t.lamprecht@proxmox.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Fixes: af1b80ae56c9 ("i386/acpi: fix inconsistent QEMU/OVMF device paths")
2021-02-25scsi: drop 'result' argument from command_complete callbackHannes Reinecke
The command complete callback has a SCSIRequest as the first argument, and the status field of that structure is identical to the 'status' argument. So drop the argument from the callback. Signed-off-by: Hannes Reinecke <hare@suse.de> Message-Id: <20201116184041.60465-3-hare@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi-disk: pass guest recoverable errors through even for rerror=stopPaolo Bonzini
Right now, recoverable sense values are only passed directly to the guest only for rerror=report. However, when rerror/werror are 'stop' we still don't want the host to be involved on every UNIT ATTENTION (especially considered that the QMP event will not have enough information to act on the report). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi-disk: pass SCSI status to scsi_handle_rw_errorPaolo Bonzini
Instead of fishing it from *r->status, just pass the SCSI status as a positive value of the second parameter and an errno as a negative value. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi: introduce scsi_sense_from_errno()Paolo Bonzini
The new function is an extension of the switch statement in scsi-disk.c which also includes the errno cases only found in sg_io_sense_from_errno. This allows us to consolidate the errno handling. Extracted from a patch by Hannes Reinecke <hare@suse.de>. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-15 12:51:48 +0000