aboutsummaryrefslogtreecommitdiff
path: root/hw
AgeCommit message (Collapse)Author
2023-01-08virtio-net: add support for configure interruptCindy Lu
Add functions to support configure interrupt in virtio_net Add the functions to support vhost_net_config_pending and vhost_net_config_mask. Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20221222070451.936503-9-lulu@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08vhost: add support for configure interruptCindy Lu
Add functions to support configure interrupt. The configure interrupt process will start in vhost_dev_start and stop in vhost_dev_stop. Also add the functions to support vhost_config_pending and vhost_config_mask. Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20221222070451.936503-8-lulu@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08virtio: add support for configure interruptCindy Lu
Add the functions to support the configure interrupt in virtio The function virtio_config_guest_notifier_read will notify the guest if there is an configure interrupt. The function virtio_config_set_guest_notifier_fd_handler is to set the fd hander for the notifier Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20221222070451.936503-7-lulu@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08vhost-vdpa: add support for config interruptCindy Lu
Add new call back function in vhost-vdpa, The function vhost_set_config_call can set the event fd to kernel. This function will be called in the vhost_dev_start and vhost_dev_stop Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20221222070451.936503-6-lulu@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08virtio-pci: decouple the single vector from the interrupt processCindy Lu
To reuse the interrupt process in configure interrupt Need to decouple the single vector from the interrupt process. We add new function kvm_virtio_pci_vector_use_one and _release_one. These functions are used for the single vector, the whole process will finish in the loop with vq number. Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20221222070451.936503-4-lulu@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08virtio-pci: decouple notifier from interrupt processCindy Lu
To reuse the notifier process. We add the virtio_pci_get_notifier to get the notifier and vector. The INPUT for this function is IDX, The OUTPUT is the notifier and the vector Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20221222070451.936503-3-lulu@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08virtio: introduce macro VIRTIO_CONFIG_IRQ_IDXCindy Lu
To support configure interrupt for vhost-vdpa Introduce VIRTIO_CONFIG_IRQ_IDX -1 as configure interrupt's queue index, Then we can reuse the functions guest_notifier_mask and guest_notifier_pending. Add the check of queue index in these drivers, if the driver does not support configure interrupt, the function will just return Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20221222070451.936503-2-lulu@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08vhost-user: Fix the virtio features negotiation flawHyman Huang(黄勇)
This patch aims to fix unexpected negotiation features for vhost-user netdev interface. When openvswitch reconnect Qemu after an unexpected disconnection and Qemu therefore start the vhost_dev, acked_features field in vhost_dev is initialized with value fetched from acked_features field in NetVhostUserState, which should be up-to-date at that moment but Qemu could not make it actually during the time window of virtio features negotiation. So we save the acked_features right after being configured by guest virtio driver so it can be used to restore acked_features field in vhost_dev correctly. Signed-off-by: Hyman Huang(黄勇) <huangy81@chinatelecom.cn> Signed-off-by: Guoyi Tu <tugy@chinatelecom.cn> Signed-off-by: Liuxiangdong <liuxiangdong5@huawei.com> Message-Id: <b9f8cf5561a79ea65ea38960e5a5e6d3707eef0a.1671627406.git.huangy81@chinatelecom.cn> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08hw/ppc/Kconfig: Remove unused dependencies from PEGASOS2Bernhard Beschow
Removes the following dependencies from ppc-softmmu: - CONFIG_ACPI_CPU_HOTPLUG - CONFIG_ACPI_CXL - CONFIG_ACPI_HMAT - CONFIG_ACPI_MEMORY_HOTPLUG - CONFIG_ACPI_NVDIMM - CONFIG_ACPI_PCIHP - CONFIG_ACPI_X86 - CONFIG_MEM_DEVICE Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221216130355.41667-8-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-08i386, mips: Resolve redundant ACPI and APM dependenciesBernhard Beschow
Now that all ACPI controllers select the ACPI and APM dependencies themselves, these explicit dependencies became redundant. Remove them. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221216130355.41667-7-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-08hw/isa/Kconfig: Add missing dependency to VT82C686Bernhard Beschow
The ACPIREGS are provided by TYPE_VIA_PM, so needs to select ACPI. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221216130355.41667-6-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-08hw/acpi/Kconfig: Add missing dependencies to ACPI_PIIX4Bernhard Beschow
piix4_pm_realize() uses apm_init() and pm_smbus_init(), so both APM and ACPI_SMBUS are provided by the device model managed by ACPI_PIIX4. The ACPIREGS are also provided by ACPI_PIIX4, so needs to select ACPI. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221216130355.41667-5-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-08hw/acpi/Kconfig: Do not needlessly build TYPE_PIIX4_PM in non-PC/Malta machinesBernhard Beschow
TYPE_PIIX4_PM is only used in machines where PIIX chipsets are used which is currently PC and Malta. There is no point building it for the other ACPI_X86 machines. Note that this also removes unneeded ACPI_PIIX4 from PEGASOS2. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221216130355.41667-4-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
2023-01-08hw/acpi/Kconfig: Add missing dependencies to ACPI_ICH9Bernhard Beschow
ich9_lpc_realize() uses apm_init() and ich9_smbus_realize() uses pm_smbus_init(), so both APM and ACPI_SMBUS are provided by the device models managed by ACPI_ICH9. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216130355.41667-3-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08hw/acpi/Kconfig: Rename ACPI_X86_ICH to ACPI_ICH9Bernhard Beschow
Although the ICH9 ACPI controller may currently be tied to x86 it doesn't have to. Furthermore, the source files this configuration switch manages contain a '9', so this name fits more. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216130355.41667-2-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08virtio_net: copy VIRTIO_NET_S_ANNOUNCE if device model has itEugenio Pérez
Status part of the emulated feature. It will follow device model, so we must copy it as long as NIC device model has it set. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Message-Id: <20221221115015.1400889-3-eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com>
2023-01-08virtio_net: Modify virtio_net_get_config to early returnEugenio Pérez
Next patches introduce more code on vhost-vdpa branch, with already have too much indentation. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221221115015.1400889-2-eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-07Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell
staging pull-loongarch-20230106 # gpg: Signature made Fri 06 Jan 2023 06:21:22 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu: hw/intc/loongarch_pch: Change default irq number of pch irq controller hw/intc/loongarch_pch_pic: add irq number property hw/intc/loongarch_pch_msi: add irq number property Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of ↵Peter Maydell
https://github.com/alistair23/qemu into staging First RISC-V PR for QEMU 8.0 * Fix PMP propagation for tlb * Collection of bug fixes * Bump the OpenTitan supported version * Add smstateen support * Support native debug icount trigger * Remove the redundant ipi-id property in the virt machine * Support cache-related PMU events in virtual mode * Add some missing PolarFire SoC io regions * Fix mret exception cause when no pmp rule is configured * Fix bug where disabling compressed instructions would crash QEMU * Add Zawrs ISA extension support * A range of code refactoring and cleanups # gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits) hw/intc: sifive_plic: Fix the pending register range check hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC hw/intc: sifive_plic: Update "num-sources" property default value hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() hw/intc: sifive_plic: Improve robustness of the PLIC config parser hw/intc: sifive_plic: Drop PLICMode_H hw/riscv: spike: Remove misleading comments hw/riscv: Sort machines Kconfig options in alphabetical order hw/riscv: Fix opentitan dependency to SIFIVE_PLIC hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC RISC-V: Add Zawrs ISA extension support target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ target/riscv: Simplify helper_sret() a little bit target/riscv: Set pc_succ_insn for !rvc illegal insn ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-06Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell
Fix race conditions in new user-only vma tracking. Add tcg backend paired register allocation. Cleanup tcg backend function call abi. # gpg: Signature made Fri 06 Jan 2023 03:12:17 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu: (47 commits) tests/tcg/multiarch: add vma-pthread.c accel/tcg: Handle false negative lookup in page_check_range accel/tcg: Use g_free_rcu for user-exec interval trees accel/tcg: Fix tb_invalidate_phys_page_unwind tcg: Add TCGHelperInfo argument to tcg_out_call tcg/aarch64: Merge tcg_out_callr into tcg_out_call tcg: Move ffi_cif pointer into TCGHelperInfo tcg: Factor init_ffi_layouts() out of tcg_context_init() tcg: Convert typecode_to_ffi from array to function tcg: Reorg function calls tcg: Use output_pref wrapper function tcg: Vary the allocation size for TCGOp tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*() accel/tcg/plugin: Use copy_op in append_{udata,mem}_cb accel/tcg/plugin: Avoid duplicate copy in copy_call accel/tcg/plugin: Don't search for the function pointer index tcg: Use TCG_CALL_ARG_EVEN for TCI special case tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-06hw/intc/loongarch_pch: Change default irq number of pch irq controllerTianrui Zhao
Change the default irq number of pch pic to 32, so that the irq number of pch msi is 224(256 - 32), and move the 'PCH_PIC_IRQ_NUM' macro to pci-host/ls7a.h and add prefix 'VIRT' on it to keep standard format. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230104020518.2564263-4-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-01-06hw/intc/loongarch_pch_pic: add irq number propertyTianrui Zhao
With loongarch 7A1000 manual, irq number supported can be set in PCH_PIC_INT_ID_HI register. This patch adds irq number property for loongarch_pch_pic, so that virt machine can set different irq number when pch_pic intc is added. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230104020518.2564263-3-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-01-06hw/intc/loongarch_pch_msi: add irq number propertyTianrui Zhao
This patch adds irq number property for loongarch msi interrupt controller, and remove hard coding irq number macro. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230104020518.2564263-2-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-01-06hw/intc: sifive_plic: Fix the pending register range checkBin Meng
The pending register upper limit is currently set to plic->num_sources >> 3, which is wrong, e.g.: considering plic->num_sources is 7, the upper limit becomes 0 which fails the range check if reading the pending register at pending_base. Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-16-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initializationBin Meng
"hartid-base" and "priority-base" are zero by default. There is no need to initialize them to zero again. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-15-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng
At present the SiFive PLIC model "priority-base" expects interrupt priority register base starting from source 1 instead source 0, that's why on most platforms "priority-base" is set to 0x04 except 'opentitan' machine. 'opentitan' should have set "priority-base" to 0x04 too. Note the irq number calculation in sifive_plic_{read,write} is correct as the codes make up for the irq number by adding 1. Let's simply update "priority-base" to start from interrupt source 0 and add a comment to make it crystal clear. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <20221211030829.802437-14-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng
Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which is VIRTIO_NDEV and also used as the value of "riscv,ndev" property in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES should include interrupt source 0 but "riscv,ndev" does not. While we are here, we also fix the comments of platform bus irq range which is now "64 to 96", but should be "64 to 95", introduced since commit 1832b7cb3f64 ("hw/riscv: virt: Create a platform bus"). Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-13-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng
At present magic number is used to create "riscv,ndev" property in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that is used to instantiate the PLIC model instead. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-12-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: Update "num-sources" property default valueBin Meng
At present the default value of "num-sources" property is zero, which does not make a lot of sense, as in sifive_plic_realize() we see s->bitfield_words is calculated by: s->bitfield_words = (s->num_sources + 31) >> 5; if the we don't configure "num-sources" property its default value zero makes s->bitfield_words zero too, which isn't true because interrupt source 0 still occupies one word. Let's change the default value to 1 meaning that only interrupt source 0 is supported by default and a sanity check in realize(). While we are here, add a comment to describe the exact meaning of this property that the number should include interrupt source 0. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-9-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ↵Bin Meng
sifive_plic_realize() The realize() callback has an errp for us to propagate the error up. While we are here, correct the wrong multi-line comment format. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221211030829.802437-8-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: Improve robustness of the PLIC config parserBin Meng
At present the PLIC config parser can only handle legal config string like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is given the parser won't get the correct configuration. This commit improves the config parser to make it more robust. Signed-off-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-7-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: Drop PLICMode_HBin Meng
H-mode has been removed since priv spec 1.10. Drop it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-6-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: spike: Remove misleading commentsBin Meng
PLIC is not included in the 'spike' machine. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-5-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: Sort machines Kconfig options in alphabetical orderBin Meng
SHAKTI_C machine Kconfig option was inserted in disorder. Fix it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <20221211030829.802437-4-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: Fix opentitan dependency to SIFIVE_PLICBin Meng
Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build") the IBEX PLIC model was replaced with the SiFive PLIC model in the 'opentitan' machine but we forgot the add the dependency there. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-3-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllersBin Meng
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in both riscv_aplic_realize() and riscv_imsic_realize(). Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221211030829.802437-2-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in sifive_plic_realize(). Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from RISC-V machines. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <20221211030829.802437-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: fix out-of-bound access of source_priority arrayJim Shu
If the number of interrupt is not multiple of 32, PLIC will have out-of-bound access to source_priority array. Compute the number of interrupt in the last word to avoid this out-of-bound access of array. Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-Id: <20221127165753.30533-1-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley
The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for storing FPGA bitstreams and used for In-Application Programming (IAP). Linux has an implementation of the system controller, through which the hwrng is accessed, leading to load/store access faults. Add the QSPI as unimplemented and a very basic (effectively unimplemented) version of the system controller's mailbox. Rather than purely marking the regions as unimplemented, service the mailbox requests by reporting failures and raising the interrupt so a guest can better handle the lack of support. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221117225518.4102575-4-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley
The Fabric Interconnect Controllers provide interfaces between the FPGA fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to the User Crypto Processor and does not show up on the MSS memory map either. FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1 are represented in QEMU, leading to load access violations while booting Linux for Icicle if PCIe is enabled as the root port is connected via either FIC 0 or 1. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-Id: <20221117225518.4102575-3-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/misc: pfsoc: add fabric clocks to ioscbConor Dooley
On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by "Clock Conditioning Circuitry" in the FPGA. The specific clock depends on the FPGA bitstream & can be locked to one particular {D,P}LL - in the Icicle Kit Reference Design v2022.09 or later this is/will be the case. Linux v6.1+ will have a driver for this peripheral and devicetrees that previously relied on "fixed-frequency" clock nodes have been switched over to clock-controller nodes. The IOSCB region is represented in QEMU, but the specific region of it that the CCCs occupy has not so v6.1-rcN kernels fail to boot in QEMU. Add the regions as unimplemented so that the status-quo in terms of boot is maintained. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-Id: <20221117225518.4102575-2-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra
The imsic DT binding[1] has changed and no longer require an ipi-id. The latest IMSIC driver dynamically allocates ipi id if slow-ipi is not defined. Get rid of the unused dt property which may lead to confusion. [1] https://lore.kernel.org/lkml/20221111044207.1478350-5-apatel@ventanamicro.com/ Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221122080529.1692533-1-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: Renumber the S irqs for numa supportFrédéric Pétrot
Commit 40244040a7a changed the way the S irqs are numbered. This breaks when using numa configuration, e.g.: ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \ -m 2G -smp cpus=16 \ -object memory-backend-ram,id=mem0,size=512M \ -object memory-backend-ram,id=mem1,size=512M \ -object memory-backend-ram,id=mem2,size=512M \ -object memory-backend-ram,id=mem3,size=512M \ -numa node,cpus=0-3,memdev=mem0,nodeid=0 \ -numa node,cpus=4-7,memdev=mem1,nodeid=1 \ -numa node,cpus=8-11,memdev=mem2,nodeid=2 \ -numa node,cpus=12-15,memdev=mem3,nodeid=3 leads to: Unexpected error in object_property_find_err() at ../qom/object.c:1304: qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not found This patch makes the nubering of the S irqs identical to what it was before. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Message-Id: <20221114135122.1668703-1-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa
Adds the updated `aon_timer` base as an unimplemented device. This is used by TockOS, patch ensures the guest doesn't hit load faults. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221025043335.339815-3-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa
This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes any references to Padctrl. Note: OpenTitan doc [2] has not yet specified much detail regarding this, except for a note that states `TODO: this section needs to be updated to reflect the pinmux/padctrl merger` [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06i386: SGX: remove deprecated member of SGXInfoPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-06KVM: remove support for kernel-irqchip=offPaolo Bonzini
-machine kernel-irqchip=off is broken for many guest OSes; kernel-irqchip=split is the replacement that works, so remove the deprecated support for the former. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-06ide: Add "ide-cf" driver, a CompactFlash cardLubomir Rintel
This allows attaching IDE_CFATA device to an IDE bus. Behaves like a CompactFlash card in True IDE mode. Tested with: qemu-system-i386 \ -device driver=ide-cf,drive=cf,bus=ide.0 \ -drive id=cf,index=0,format=raw,if=none,file=cf.img Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Message-Id: <20221130120319.706885-1-lkundrak@v3.sk> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-06ide: Add 8-bit data modeLubomir Rintel
CompactFlash uses features 0x01 and 0x81 to enable/disable 8-bit data path. Implement them. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Message-Id: <20221130120238.706717-1-lkundrak@v3.sk> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-06hw: Reduce "qemu/accel.h" inclusionPhilippe Mathieu-Daudé
Move "qemu/accel.h" include from the heavily included "hw/boards.h" to hw/core/machine.c, the single file using the AccelState definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-Id: <20221130135641.85328-3-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-17 15:07:50 +0000