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2023-03-06hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADTSunil V L
Add Multiple APIC Description Table (MADT) with the RINTC structure for each cpu. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-6-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Enable basic ACPI infrastructureSunil V L
Add basic ACPI infrastructure for RISC-V with below tables. 1) DSDT with below basic objects - CPUs - fw_cfg 2) FADT revision 6 with HW_REDUCED flag 3) XSDT 4) RSDP Add this functionality in a new file virt-acpi-build.c and enable building this infrastructure. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-5-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Add memmap pointer to RiscVVirtStateSunil V L
memmap needs to be exported outside of virt.c so that modules like acpi can use it. Hence, add a pointer field in RiscVVirtState structure and initialize it with the memorymap. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-4-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Add a switch to disable ACPISunil V L
ACPI will be enabled by default. Add a switch to turn off for testing and debug purposes. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-3-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fieldsSunil V L
ACPI needs OEM_ID and OEM_TABLE_ID for the machine. Add these fields in the RISCVVirtState structure and initialize with default values. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-2-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Correctly set the device-tree entry 'mmu-type'Alexandre Ghiti
The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230303131252.892893-6-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw: arm: allwinner-h3: Fix and complete H3 i2c devicesqianfan Zhao
Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi. The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear control register's INT_FLAG bit. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06hw/nvme: flexible data placement emulationJesper Devantier
Add emulation of TP4146 ("Flexible Data Placement"). Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Jesper Devantier <j.devantier@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw/nvme: basic directives supportGollu Appalanaidu
Add support for the Directive Send and Recv commands and the Identify directive. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw/nvme: add basic endurance group supportKlaus Jensen
Add the mandatory Endurance Group identify data structures and log pages. For now, all namespaces in a subsystem belongs to a single Endurance Group. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw/nvme: store a pointer to the NvmeSubsystem in the NvmeNamespaceNiklas Cassel
Each NvmeNamespace can be used by serveral controllers, but a NvmeNamespace can at most belong to a single NvmeSubsystem. Store a pointer to the NvmeSubsystem, if the namespace was realized with a NvmeSubsystem. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw/nvme: move adjustment of data_units{read,written}Joel Granados
Move the rounding of bytes read/written into nvme_smart_log which reports in units of 512 bytes, rounded up in thousands. This is in preparation for adding the Endurance Group Information log page which reports in units of billions, rounded up. Reviewed-by: Keith Busch <kbusch@kernel.org> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Joel Granados <j.granados@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCsqianfan Zhao
TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect) register on SUN6i based SoCs, we should lower interrupt when the guest set this bit. The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no device connected on the i2c bus, next is the trace log: allwinner_i2c_write write CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN allwinner_i2c_write write CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN allwinner_i2c_read read STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE ... Fix it. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06hw: arm: Support direct boot for Linux/arm64 EFI zboot imagesArd Biesheuvel
Fedora 39 will ship its arm64 kernels in the new generic EFI zboot format, using gzip compression for the payload. For doing EFI boot in QEMU, this is completely transparent, as the firmware or bootloader will take care of this. However, for direct kernel boot without firmware, we will lose the ability to boot such distro kernels unless we deal with the new format directly. EFI zboot images contain metadata in the header regarding the placement of the compressed payload inside the image, and the type of compression used. This means we can wire up the existing gzip support without too much hassle, by parsing the header and grabbing the payload from inside the loaded zboot image. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Message-id: 20230303160109.3626966-1-ardb@kernel.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked comment formatting, fixed checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06hw/xen/xen_pt: fix uninitialized variableMarek Marczykowski-Górecki
xen_pt_config_reg_init() reads only that many bytes as the size of the register that is being initialized. It uses xen_host_pci_get_{byte,word,long} and casts its last argument to expected pointer type. This means for smaller registers higher bits of 'val' are not initialized. Then, the function fails if any of those higher bits are set. Fix this by initializing 'val' with zero. Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <20230127050815.4155276-1-marmarek@invisiblethingslab.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2023-03-06xen/pt: reserve PCI slot 2 for Intel igd-passthruChuck Zmudzinski
Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus, as noted in docs/igd-assign.txt in the Qemu source code. Currently, when the xl toolstack is used to configure a Xen HVM guest with Intel IGD passthrough to the guest with the Qemu upstream device model, a Qemu emulated PCI device will occupy slot 2 and the Intel IGD will occupy a different slot. This problem often prevents the guest from booting. The only available workarounds are not good: Configure Xen HVM guests to use the old and no longer maintained Qemu traditional device model available from xenbits.xen.org which does reserve slot 2 for the Intel IGD or use the "pc" machine type instead of the "xenfv" machine type and add the xen platform device at slot 3 using a command line option instead of patching qemu to fix the "xenfv" machine type directly. The second workaround causes some degredation in startup performance such as a longer boot time and reduced resolution of the grub menu that is displayed on the monitor. This patch avoids that reduced startup performance when using the Qemu upstream device model for Xen HVM guests configured with the igd-passthru=on option. To implement this feature in the Qemu upstream device model for Xen HVM guests, introduce the following new functions, types, and macros: * XEN_PT_DEVICE_CLASS declaration, based on the existing TYPE_XEN_PT_DEVICE * XEN_PT_DEVICE_GET_CLASS macro helper function for XEN_PT_DEVICE_CLASS * typedef XenPTQdevRealize function pointer * XEN_PCI_IGD_SLOT_MASK, the value of slot_reserved_mask to reserve slot 2 * xen_igd_reserve_slot and xen_igd_clear_slot functions Michael Tsirkin: * Introduce XEN_PCI_IGD_DOMAIN, XEN_PCI_IGD_BUS, XEN_PCI_IGD_DEV, and XEN_PCI_IGD_FN - use them to compute the value of XEN_PCI_IGD_SLOT_MASK The new xen_igd_reserve_slot function uses the existing slot_reserved_mask member of PCIBus to reserve PCI slot 2 for Xen HVM guests configured using the xl toolstack with the gfx_passthru option enabled, which sets the igd-passthru=on option to Qemu for the Xen HVM machine type. The new xen_igd_reserve_slot function also needs to be implemented in hw/xen/xen_pt_stub.c to prevent FTBFS during the link stage for the case when Qemu is configured with --enable-xen and --disable-xen-pci-passthrough, in which case it does nothing. The new xen_igd_clear_slot function overrides qdev->realize of the parent PCI device class to enable the Intel IGD to occupy slot 2 on the PCI bus since slot 2 was reserved by xen_igd_reserve_slot when the PCI bus was created in hw/i386/pc_piix.c for the case when igd-passthru=on. Move the call to xen_host_pci_device_get, and the associated error handling, from xen_pt_realize to the new xen_igd_clear_slot function to initialize the device class and vendor values which enables the checks for the Intel IGD to succeed. The verification that the host device is an Intel IGD to be passed through is done by checking the domain, bus, slot, and function values as well as by checking that gfx_passthru is enabled, the device class is VGA, and the device vendor in Intel. Signed-off-by: Chuck Zmudzinski <brchuckz@aol.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <b1b4a21fe9a600b1322742dda55a40e9961daa57.1674346505.git.brchuckz@aol.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2023-03-05hw: intc: Use cpu_by_arch_id to fetch CPU stateMayuresh Chitale
Qemu_get_cpu uses the logical CPU id assigned during init to fetch the CPU state. However APLIC, IMSIC and ACLINT contain registers and states which are specific to physical hart Ids. The hart Ids in any given system might be sparse and hence calls to qemu_get_cpu need to be replaced by cpu_by_arch_id which performs lookup based on the sparse physical hart IDs. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230303065055.915652-3-mchitale@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05hw/riscv/virt.c: add cbo[mz]-block-size fdt propertiesAnup Patel
The cbom-block-size fdt property property is used to inform the OS about the blocksize in bytes for the Zicbom cache operations. Linux documents it in Documentation/devicetree/bindings/riscv/cpus.yaml as: riscv,cbom-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: The blocksize in bytes for the Zicbom cache operations. cboz-block-size has the same role but for the Zicboz extension, i.e. informs the size in bytes for Zicboz cache operations. Linux support for it is under review/approval in [1]. Patch 3 of that series describes cboz-block-size as: riscv,cboz-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: The blocksize in bytes for the Zicboz cache operations. [1] https://lore.kernel.org/all/20230224162631.405473-1-ajones@ventanamicro.com/ Cc: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-ID: <20230302091406.407824-2-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-04Merge tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu into stagingPeter Maydell
ppc patch queue for 2023-03-03: This queue includes a stub implementation for the dcblc instruction to avoid an illegal instrunction exception when using u-boot with mpc85xx. It also includes a PHB fix with user-created pnv-phb devices and Skiboot. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZAJllhYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFk02YA/2YnJl0aRw6hgiayI2rLbcwQcVfp # oGAhh4QmqFL2UJw2AQDra0kh9sxBSEcqhltNnOa08tBnHPts3W/A8nmFtCd4Cw== # =VRNM # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 21:24:38 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu: pnv_phb4_pec: Simplify/align code to parent user-created PHBs pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful file pnv_phb4_pec: Only export existing PHBs to the device tree pnv_phb4_pec: Keep track of instantiated PHBs target/ppc/translate: Add dummy implementation for dcblc instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03pnv_phb4_pec: Simplify/align code to parent user-created PHBsFrederic Barrat
When instantiating a user-created PHB on P9/P10, we don't really have a reason any more to go through an indirection in pnv_chip_add_phb() in pnv.c, we can go straight to the right function in pnv_phb4_pec.c. That way, default PHBs and user-created PHBs are all handled in the same file. This patch also renames pnv_phb4_get_pec() to pnv_pec_add_phb() to better reflect that it "hooks" a PHB to a PEC. For P8, the PHBs are parented to the chip directly, so it makes sense to keep calling pnv_chip_add_phb() in pnv.c, to also be consistent with where default PHBs are handled. The only change here is that, since that function is now only used for P8, we can refine the return type. So overall, the PnvPHB front-end now has a pnv_phb_user_get_parent() function which handles the parenting of the user-created PHBs by calling the right function in the right file based on the processor version. It's also easily extensible if we ever need to support a different parent object. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-5-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful fileFrederic Barrat
The function pnv_phb4_get_pec() exposes some internals of the PEC and PHB logic, yet it was in the higher level hw/ppc/pnv.c file for historical reasons: P8 implements the PHBs from pnv.c directly, but on P9/P10, it's done through the CEC model, which has its own file. So move pnv_phb4_get_pec() to hw/pci-host/pnv_phb4_pec.c, where it fits naturally. While at it, replace the PnvPHB4 parameter by the PnvPHB front-end, since it has all the information needed and simplify it a bit. No functional changes. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-4-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Only export existing PHBs to the device treeFrederic Barrat
So far, we were always exporting all possible PHBs to the device tree. It works well when using the default config but it potentially adds non-existing devices when using '-nodefaults' and user-created PHBs, causing the firmware (skiboot) to report errors when probing those PHBs. This patch only exports PHBs which have been realized to the device tree. Fixes: d786be3fe746 ("ppc/pnv: enable user created pnv-phb for powernv9") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-3-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Keep track of instantiated PHBsFrederic Barrat
Add an array on the PEC object to keep track of the PHBs which are instantiated. The array can be sparsely populated when using user-created PHBs. It will be useful for the next patch to only export instantiated PHBs in the device tree. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-2-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03Merge tag 'pull-aspeed-20230302' of https://github.com/legoater/qemu into ↵Peter Maydell
staging aspeed queue: * fix for the Aspeed I2C slave mode * a new I2C echo device from Klaus and its associated test in avocado. * initial SoC cleanups to allow the use of block devices instead of drives on the command line. * new facebook machines and eeprom fixes for the Fuji * readline fix # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmQAnrQACgkQUaNDx8/7 # 7KGIvQ//Te2eSxlZNxAXHb3HSVFRaBW+2EkJzNlalX75olFSzCLe8BnAHK5xPlYv # JjU0aPjWaPohPLdbNbAsJY2B8AwMGbUTjSv+ORRWF6s97LTVD9WcAYHgOTCz6d2X # ZrArJ5msEQAFEySOLmBqTcuyW3t4w8XeII+B09HZIS8Gn3F9kX5+4JCw9E4sX8fS # n9ayclMmrXCPbkGA4bfwJp3KI1Tc/WXNRyG0AmPEmepid7ECr5tVvQoXRMF1Sy/D # 10qbHEcmQXvZDy85M2ED1niOac4oU+EY8Wvjzkgc36uXcjqf0jIUfw56cwGSNVkW # MhPXSMiH4tEjgxmtzld3LeA6TGfrFcCvRXYiCuYWHjBS3gptlqY6Q0580vxoQVXL # lTYui57LB1YStNLcLG9toP0d4/fRfeqEx7ddCQKlopnW/K392eoJo0aYoVGVJhIC # 3QhN525EFUwMm4FDpdSW29Gfbk/ytpf0u4hQ6JPeBl8psirRKqCGuwr5NOnPYTaN # yErlsq2eL83t9kLo+2YIqgWic85wNP3kqAjIaE6lminqX7sWFH3V1g9HqUQZVG1g # msatZMiCCvwSFuz3DPkSfnuhqwaHuhvCATZloCtguCmnbUK9qUVVzvodKw62sZrd # GdS2XvRNyoOwezz0tDEvPipyZ7RpcaatryHNuzGwRsE5Lvr73dg= # =ExnJ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Mar 2023 13:03:48 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20230302' of https://github.com/legoater/qemu: aspeed/smc: Replace SysBus IRQs with GPIO lines aspeed: Add a boot_rom overlap region in the SoC spi_boot container aspeed: Introduce a spi_boot region under the SoC aspeed/fuji : correct the eeprom size hw/at24c : modify at24c to support 1 byte address mode hw/arm/aspeed: Adding new machine Tiogapass in QEMU hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU tests/avocado/machine_aspeed.py: Add an I2C slave test hw/misc: add a toy i2c echo device hw/i2c: only schedule pending master when bus is idle readline: fix hmp completion issue Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03Merge tag 'pull-loongarch-20230303' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell
staging pull-loongarch-20230303 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZAFb5wAKCRBAov/yOSY+ # 35hmA/sHIGXU5zQV6p6DBILFGEE6x91sPtV8WKY3zujVY0hsfD4SF6bKTaKJYisZ # EztZZ5/EunQcu/vfgO46YtYysEWzrzGiinbZ5lAjxk6sdlBYlfcTQLAQEEW3zPbP # qB3SiiGmGQ0iYFHIlkyi1tCF5OEmqqQKrHYrNVk6cGBoJle2PA== # =giPH # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 02:31:03 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230303' of https://gitlab.com/gaosong/qemu: hw/loongarch/virt: add system_powerdown hmp command support target/loongarch: Implement Chip Configuraiton Version Register(0x0000) docs/system/loongarch: update loongson3.rst and rename it to virt.rst loongarch: Add smbios command line option. hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell
into staging virtio,pc,pci: features, cleanups, fixes vhost-user support without ioeventfd word replacements in vhost user spec shpc improvements cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmQBO8QPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpMUMH/3/FVp4qaF4CDwCHn7xWFRJpOREIhX/iWfUu # lGkwxnB7Lfyqdg7i4CAfgMf2emWKZchEE2DamfCo5bIX0IgRU3DWcOdR9ePvJ29J # cKwIYpxZcB4RYSoWL5OUakQLCT3JOu4XWaXeVjyHABjQhf3lGpwN4KmIOBGOy/N6 # 0YHOQScW2eW62wIOwhAEuYQceMt6KU32Uw3tLnMbJliiBf3a/hPctVNM9TFY9pcd # UYHGfBx/zD45owf1lTVEQFDg0eqPZKWW29g5haiOd5oAyXHHolzu+bt3bU7lH46b # f7iP12LqDudyrgoF5YWv3NJ4HaGm5V3kPqNqLLF/mjF7alxG+N8= # =hN3h # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 00:13:56 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (53 commits) tests/data/acpi/virt: drop (most) duplicate files. hw/cxl/mailbox: Use new UUID network order define for cel_uuid qemu/uuid: Add UUID static initializer qemu/bswap: Add const_le64() tests: acpi: Update q35/DSDT.cxl for removed duplicate UID hw/i386/acpi: Drop duplicate _UID entry for CXL root bridge tests/acpi: Allow update of q35/DSDT.cxl hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL hw/pci-bridge/cxl_downstream: Fix type naming mismatch hw/mem/cxl_type3: Improve error handling in realize() MAINTAINERS: Add Fan Ni as Compute eXpress Link QEMU reviewer intel-iommu: send UNMAP notifications for domain or global inv desc smmu: switch to use memory_region_unmap_iommu_notifier_range() memory: introduce memory_region_unmap_iommu_notifier_range() intel-iommu: fail DEVIOTLB_UNMAP without dt mode intel-iommu: fail MAP notifier without caching mode memory: Optimize replay of guest mapping chardev/char-socket: set s->listener = NULL in char_socket_finalize hw/pci: Trace IRQ routing on PCI topology ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of ↵Peter Maydell
https://gitlab.com/palmer-dabbelt/qemu into staging Fifth RISC-V PR for QEMU 8.0 * Experimantal support for writable misa. * Support for Svadu extension. * Support for the Zicond extension. * Fixes to gdbstub, CSR accesses, dependencies between the various floating-point exceptions, and XTheadMemPair. * Many cleanups. # -----BEGIN PGP SIGNATURE----- # # iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmQBrrUTHHBhbG1lckBk # YWJiZWx0LmNvbQAKCRAuExnzX7sYicHrD/9dHBDOYNwyT/C2Q31NHMcEsVN6J0kW # 0sVyDb2/TUFoXmClMwS6jZYQQwWD7tjjB7BDcvPJ0QKLblDoZFX5JyxpQypIKWcs # It/E6mk7aG0epH1GoB/mbHFDbeCm4tbo7Vf6cQGpV/vGWBUaOS67c5nenUK7Tlqw # NTr9qak+9NYVswvMHZ0lUKtO12W1g/1EVkict2/90P2snWbPZ+foWomifGNljmhy # 5WtCNp27uBKF/uuD9xubLOxSEcqtZFTuKJy7U3azV4I0IKfd6Is83Kd0IwBOrTgT # MYkFdtQE1jgbkXYVZjft6ymLuqJrcLFYwD8C2zdNAXJLk1Y+MCtGafgW6f6SkT6B # FrNaSOqQ9xXiaNStF2FwYdmZ476zcY+eEg2rH1grTwCMewZ9r7m3+H8iat/tR0pt # 9scYAre1oaL33LB6DGZi3JkssNYyj42sutcNao2hQXRHcsh+vv1dLR+Di2mO6Ji5 # MNfvEgCrWWZjNVSwvhwCXdJPqqpyTbkRf8HJEp0gWvjk6VoF8sWidDw/8oMLj+wW # qZur7GNe+piJNvly85aFSL9J3SX7RyNeDzX/yK3b4k+g6I/ZziQaNgQtB9gYcm6w # mj3snCwRbEMEhdhPH0+Chm0Wb97knHJS14Vq9wCe2xh16o3HM5FspboLFkGZMjDV # tRDPFb7pitwdlA== # =FMkl # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 08:24:21 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt/qemu: (59 commits) target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig target/riscv/vector_helper.c: create vext_set_tail_elems_1s() target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers target/riscv/csr.c: simplify mctr() target/riscv/csr.c: use env_archcpu() in ctr() target/riscv: Export Svadu property target/riscv: Add *envcfg.HADE related check in address translation target/riscv: Add *envcfg.PBMTE related check in address translation target/riscv: Add csr support for svadu target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions hw/riscv: Move the dtb load bits outside of create_fdt() hw/riscv: Skip re-generating DT nodes for a given DTB target/riscv: Add support for Zicond extension RISC-V: XTheadMemPair: Remove register restrictions for store-pair target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages target/riscv: Group all predicate() routines together target/riscv: Drop priv level check in mseccfg predicate() target/riscv: Allow debugger to access sstc CSRs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03hw/loongarch/virt: add system_powerdown hmp command supportSong Gao
For loongarch virt machine, add powerdown notification callback and send ACPI_POWER_DOWN_STATUS event by acpi ged. Also add acpi dsdt table for ACPI_POWER_BUTTON_DEVICE device in this patch. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230303010548.295580-1-gaosong@loongson.cn>
2023-03-03hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASEBibo Mao
In theory gsi base can start from 0 on loongarch virt machine, however gsi base is hard-coded in linux kernel loongarch system, else system fails to boot. This patch renames macro PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE, keeps value unchanged. GSI base is common concept in acpi spec and easy to understand. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20221228030719.991878-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-03-02hw/cxl/mailbox: Use new UUID network order define for cel_uuidIra Weiny
The cel_uuid was programatically generated previously because there was no static initializer for network order UUIDs. Use the new network order initializer for cel_uuid. Adjust cxl_initialize_mailbox() because it can't fail now. Update specification reference. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-11-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/i386/acpi: Drop duplicate _UID entry for CXL root bridgeJonathan Cameron
Noticed as this prevents iASL disasembling the DSDT table. Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-7-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/cxl: Add CXL_CAPACITY_MULTIPLIER definitionGregory Price
Remove usage of magic numbers when accessing capacity fields and replace with CXL_CAPACITY_MULTIPLIER, matching the kernel definition. Signed-off-by: Gregory Price <gregory.price@memverge.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-5-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXLGregory Price
Current code sets to STORAGE_EXPRESS and then overrides it. Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-4-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron
Fix capitalization difference between struct name and typedef. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-3-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/mem/cxl_type3: Improve error handling in realize()Jonathan Cameron
msix_init_exclusive_bar() can fail, so if it does cleanup the address space. Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-2-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02intel-iommu: send UNMAP notifications for domain or global inv descPeter Xu
We don't send UNMAP notification upon domain or global invalidation which will lead the notifier can't work correctly. One example is to use vhost remote IOTLB without enabling device IOTLB. Fixing this by sending UNMAP notification. Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230223065924.42503-6-jasowang@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02smmu: switch to use memory_region_unmap_iommu_notifier_range()Jason Wang
Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230223065924.42503-5-jasowang@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02intel-iommu: fail DEVIOTLB_UNMAP without dt modeJason Wang
Without dt mode, device IOTLB notifier won't work since guest won't send device IOTLB invalidation descriptor in this case. Let's fail early instead of misbehaving silently. Reviewed-by: Laurent Vivier <lvivier@redhat.com> Tested-by: Laurent Vivier <lvivier@redhat.com> Tested-by: Viktor Prutyanov <viktor@daynix.com> Buglink: https://bugzilla.redhat.com/2156876 Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230223065924.42503-3-jasowang@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02intel-iommu: fail MAP notifier without caching modeJason Wang
Without caching mode, MAP notifier won't work correctly since guest won't send IOTLB update event when it establishes new mappings in the I/O page tables. Let's fail the IOMMU notifiers early instead of misbehaving silently. Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Viktor Prutyanov <viktor@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230223065924.42503-2-jasowang@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02memory: Optimize replay of guest mappingZhenzhong Duan
On x86, there are two notifiers registered due to vtd-ir memory region splitting the whole address space. During replay of the address space for each notifier, the whole address space is scanned which is unnecessory. We only need to scan the space belong to notifier montiored space. Assert when notifier is used to monitor beyond iommu memory region's address space. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Message-Id: <20230215065238.713041-1-zhenzhong.duan@intel.com> Acked-by: Peter Xu <peterx@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/pci: Trace IRQ routing on PCI topologyPhilippe Mathieu-Daudé
Trace how IRQ are rooted from EP to RC. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230211152239.88106-3-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02vhost: avoid a potential use of an uninitialized variable in vhost_svq_poll()Carlos López
In vhost_svq_poll(), if vhost_svq_get_buf() fails due to a device providing invalid descriptors, len is left uninitialized and returned to the caller, potentally leaking stack data or causing undefined behavior. Fix this by initializing len to 0. Found with GCC 13 and -fanalyzer (abridged): ../hw/virtio/vhost-shadow-virtqueue.c: In function ‘vhost_svq_poll’: ../hw/virtio/vhost-shadow-virtqueue.c:538:12: warning: use of uninitialized value ‘len’ [CWE-457] [-Wanalyzer-use-of-uninitialized-value] 538 | return len; | ^~~ ‘vhost_svq_poll’: events 1-4 | | 522 | size_t vhost_svq_poll(VhostShadowVirtqueue *svq) | | ^~~~~~~~~~~~~~ | | | | | (1) entry to ‘vhost_svq_poll’ |...... | 525 | uint32_t len; | | ~~~ | | | | | (2) region created on stack here | | (3) capacity: 4 bytes |...... | 528 | if (vhost_svq_more_used(svq)) { | | ~ | | | | | (4) inlined call to ‘vhost_svq_more_used’ from ‘vhost_svq_poll’ (...) | 528 | if (vhost_svq_more_used(svq)) { | | ^~~~~~~~~~~~~~~~~~~~~~~~~ | | || | | |(8) ...to here | | (7) following ‘true’ branch... |...... | 537 | vhost_svq_get_buf(svq, &len); | | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | | | (9) calling ‘vhost_svq_get_buf’ from ‘vhost_svq_poll’ | +--> ‘vhost_svq_get_buf’: events 10-11 | | 416 | static VirtQueueElement *vhost_svq_get_buf(VhostShadowVirtqueue *svq, | | ^~~~~~~~~~~~~~~~~ | | | | | (10) entry to ‘vhost_svq_get_buf’ |...... | 423 | if (!vhost_svq_more_used(svq)) { | | ~ | | | | | (11) inlined call to ‘vhost_svq_more_used’ from ‘vhost_svq_get_buf’ | (...) | ‘vhost_svq_get_buf’: event 14 | | 423 | if (!vhost_svq_more_used(svq)) { | | ^ | | | | | (14) following ‘false’ branch... | ‘vhost_svq_get_buf’: event 15 | |cc1: | (15): ...to here | <------+ | ‘vhost_svq_poll’: events 16-17 | | 537 | vhost_svq_get_buf(svq, &len); | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | | | (16) returning to ‘vhost_svq_poll’ from ‘vhost_svq_get_buf’ | 538 | return len; | | ~~~ | | | | | (17) use of uninitialized value ‘len’ here Note by Laurent Vivier <lvivier@redhat.com>: The return value is only used to detect an error: vhost_svq_poll vhost_vdpa_net_cvq_add vhost_vdpa_net_load_cmd vhost_vdpa_net_load_mac -> a negative return is only used to detect error vhost_vdpa_net_load_mq -> a negative return is only used to detect error vhost_vdpa_net_handle_ctrl_avail -> a negative return is only used to detect error Fixes: d368c0b052ad ("vhost: Do not depend on !NULL VirtQueueElement on vhost_svq_flush") Signed-off-by: Carlos López <clopez@suse.de> Message-Id: <20230213085747.19956-1-clopez@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02pcie: set power indicator to off on reset by defaultVladimir Sementsov-Ogievskiy
It should not be zero, the only valid values are ON, OFF and BLINK. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Anton Kuchin <antonkuchin@yandex-team.ru> Message-Id: <20230216180356.156832-13-vsementsov@yandex-team.ru> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02aspeed/smc: Replace SysBus IRQs with GPIO linesCédric Le Goater
It's cleaner and removes the curious '+ 1' required to skip the DMA IRQ line of the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-02aspeed: Add a boot_rom overlap region in the SoC spi_boot containerCédric Le Goater
To avoid the SPI transactions fetching instructions from the FMC CE0 flash device and speed up boot, a ROM can be created if a drive is available. Reverse the logic to allow a machine to boot without a drive, using a block device instead : -blockdev node-name=fmc0,driver=file,filename=/path/to/flash.img \ -device mx66u51235f,bus=ssi.0,drive=fmc0 Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-02aspeed: Introduce a spi_boot region under the SoCCédric Le Goater
The default boot address of the Aspeed SoCs is 0x0. For this reason, the FMC flash device contents are remapped by HW on the first 256MB of the address space. In QEMU, this is currently done in the machine init with the setup of a region alias. Move this code to the SoC and introduce an extra container to prepare ground for the boot ROM region which will overlap the FMC flash remapping. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-02aspeed/fuji : correct the eeprom sizeSittisak Sinprem
Device 24C64 the size is 64 kilobits = 8kilobyte Device 24C02 the size is 2 kilobits = 256byte Signed-off-by: Sittisak Sinprem <ssinprem@celestica.com> Reviewed-by: Peter Delevoryas <peter@pjd.dev> [ clg: checkpatch issues ] Message-Id: <167660539263.10409.9736070122710923479-2@git.sr.ht> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-02hw/at24c : modify at24c to support 1 byte address modeSittisak Sinprem
Signed-off-by: Sittisak Sinprem <ssinprem@celestica.com> Reviewed-by: Peter Delevoryas <peter@pjd.dev> [ clg: checkpatch issues ] Message-Id: <167660539263.10409.9736070122710923479-1@git.sr.ht> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-02hw/arm/aspeed: Adding new machine Tiogapass in QEMUKarthikeyan Pasupathi
This patch support Tiogapass in QEMU environment. and introduced EEPROM BMC FRU data support "add tiogapass_bmc_fruid data" along with the machine support. Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - commit log topic update - checkpatch issues - Documentation update ] Message-Id: <20230216184342.253868-1-pkarthikeyan1509@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-02hw/arm/aspeed: Adding new machine Yosemitev2 in QEMUKarthikeyan Pasupathi
This patch support Yosemitev2 in QEMU environment. and introduced EEPROM BMC FRU data support "add fbyv2_bmc_fruid data" along with the machine support. Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - commit log topic update - Documentation update ] Message-Id: <20230216133326.216017-1-pkarthikeyan1509@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 12:39:22 +0000