aboutsummaryrefslogtreecommitdiff
path: root/hw
AgeCommit message (Collapse)Author
2023-01-06hw/riscv: Fix opentitan dependency to SIFIVE_PLICBin Meng
Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build") the IBEX PLIC model was replaced with the SiFive PLIC model in the 'opentitan' machine but we forgot the add the dependency there. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-3-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllersBin Meng
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in both riscv_aplic_realize() and riscv_imsic_realize(). Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221211030829.802437-2-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in sifive_plic_realize(). Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from RISC-V machines. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <20221211030829.802437-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: fix out-of-bound access of source_priority arrayJim Shu
If the number of interrupt is not multiple of 32, PLIC will have out-of-bound access to source_priority array. Compute the number of interrupt in the last word to avoid this out-of-bound access of array. Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-Id: <20221127165753.30533-1-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley
The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for storing FPGA bitstreams and used for In-Application Programming (IAP). Linux has an implementation of the system controller, through which the hwrng is accessed, leading to load/store access faults. Add the QSPI as unimplemented and a very basic (effectively unimplemented) version of the system controller's mailbox. Rather than purely marking the regions as unimplemented, service the mailbox requests by reporting failures and raising the interrupt so a guest can better handle the lack of support. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221117225518.4102575-4-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley
The Fabric Interconnect Controllers provide interfaces between the FPGA fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to the User Crypto Processor and does not show up on the MSS memory map either. FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1 are represented in QEMU, leading to load access violations while booting Linux for Icicle if PCIe is enabled as the root port is connected via either FIC 0 or 1. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-Id: <20221117225518.4102575-3-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/misc: pfsoc: add fabric clocks to ioscbConor Dooley
On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by "Clock Conditioning Circuitry" in the FPGA. The specific clock depends on the FPGA bitstream & can be locked to one particular {D,P}LL - in the Icicle Kit Reference Design v2022.09 or later this is/will be the case. Linux v6.1+ will have a driver for this peripheral and devicetrees that previously relied on "fixed-frequency" clock nodes have been switched over to clock-controller nodes. The IOSCB region is represented in QEMU, but the specific region of it that the CCCs occupy has not so v6.1-rcN kernels fail to boot in QEMU. Add the regions as unimplemented so that the status-quo in terms of boot is maintained. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-Id: <20221117225518.4102575-2-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra
The imsic DT binding[1] has changed and no longer require an ipi-id. The latest IMSIC driver dynamically allocates ipi id if slow-ipi is not defined. Get rid of the unused dt property which may lead to confusion. [1] https://lore.kernel.org/lkml/20221111044207.1478350-5-apatel@ventanamicro.com/ Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221122080529.1692533-1-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: Renumber the S irqs for numa supportFrédéric Pétrot
Commit 40244040a7a changed the way the S irqs are numbered. This breaks when using numa configuration, e.g.: ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \ -m 2G -smp cpus=16 \ -object memory-backend-ram,id=mem0,size=512M \ -object memory-backend-ram,id=mem1,size=512M \ -object memory-backend-ram,id=mem2,size=512M \ -object memory-backend-ram,id=mem3,size=512M \ -numa node,cpus=0-3,memdev=mem0,nodeid=0 \ -numa node,cpus=4-7,memdev=mem1,nodeid=1 \ -numa node,cpus=8-11,memdev=mem2,nodeid=2 \ -numa node,cpus=12-15,memdev=mem3,nodeid=3 leads to: Unexpected error in object_property_find_err() at ../qom/object.c:1304: qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not found This patch makes the nubering of the S irqs identical to what it was before. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Message-Id: <20221114135122.1668703-1-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa
Adds the updated `aon_timer` base as an unimplemented device. This is used by TockOS, patch ensures the guest doesn't hit load faults. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221025043335.339815-3-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa
This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes any references to Padctrl. Note: OpenTitan doc [2] has not yet specified much detail regarding this, except for a note that states `TODO: this section needs to be updated to reflect the pinmux/padctrl merger` [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06i386: SGX: remove deprecated member of SGXInfoPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-06KVM: remove support for kernel-irqchip=offPaolo Bonzini
-machine kernel-irqchip=off is broken for many guest OSes; kernel-irqchip=split is the replacement that works, so remove the deprecated support for the former. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-06ide: Add "ide-cf" driver, a CompactFlash cardLubomir Rintel
This allows attaching IDE_CFATA device to an IDE bus. Behaves like a CompactFlash card in True IDE mode. Tested with: qemu-system-i386 \ -device driver=ide-cf,drive=cf,bus=ide.0 \ -drive id=cf,index=0,format=raw,if=none,file=cf.img Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Message-Id: <20221130120319.706885-1-lkundrak@v3.sk> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-06ide: Add 8-bit data modeLubomir Rintel
CompactFlash uses features 0x01 and 0x81 to enable/disable 8-bit data path. Implement them. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Message-Id: <20221130120238.706717-1-lkundrak@v3.sk> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-06hw: Reduce "qemu/accel.h" inclusionPhilippe Mathieu-Daudé
Move "qemu/accel.h" include from the heavily included "hw/boards.h" to hw/core/machine.c, the single file using the AccelState definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-Id: <20221130135641.85328-3-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-01-05Merge tag 'pull-target-arm-20230105' of ↵Peter Maydell
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Implement AArch32 ARMv8-R support * Add Cortex-R52 CPU * fix handling of HLT semihosting in system mode * hw/timer/ixm_epit: cleanup and fix bug in compare handling * target/arm: Coding style fixes * target/arm: Clean up includes * nseries: minor code cleanups * target/arm: align exposed ID registers with Linux * hw/arm/smmu-common: remove unnecessary inlines * i.MX7D: Handle GPT timers * i.MX7D: Connect IRQs to GPIO devices * i.MX6UL: Add a specific GPT timer instance * hw/net: Fix read of uninitialized memory in imx_fec # gpg: Signature made Thu 05 Jan 2023 16:43:18 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230105' of https://git.linaro.org/people/pmaydell/qemu-arm: (34 commits) hw/net: Fix read of uninitialized memory in imx_fec. i.MX7D: Connect IRQs to GPIO devices. i.MX6UL: Add a specific GPT timer instance for the i.MX6UL i.MX7D: Compute clock frequency for the fixed frequency clocks. i.MX7D: Connect GPT timers to IRQ hw/arm/smmu-common: Avoid using inlined functions with external linkage hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope target/arm: align exposed ID registers with Linux hw/arm/nseries: Silent -Wmissing-field-initializers warning hw/arm/nseries: Constify various read-only arrays hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg target/arm: cleanup cpu includes target/arm: Remove unused includes from helper.c target/arm: Remove unused includes from m_helper.c target/arm: Fix checkpatch brace errors in helper.c target/arm: Fix checkpatch space errors in helper.c target/arm: Fix checkpatch comment style warnings in helper.c hw/timer/imx_epit: fix compare timer handling hw/timer/imx_epit: remove explicit fields cnt and freq hw/timer/imx_epit: factor out register write handlers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05accel/tcg: Set cflags_next_tb in cpu_common_initfnRichard Henderson
While we initialize this value in cpu_common_reset, that isn't called during startup, so set it as well in init. This fixes -singlestep versus the very first TB. Fixes: 04f5b647ed07 ("accel/tcg: Handle -singlestep in curr_cflags") Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05hw/net: Fix read of uninitialized memory in imx_fec.Stephen Longfield
Size is used at lines 1088/1188 for the loop, which reads the last 4 bytes from the crc_ptr so it does need to get increased, however it shouldn't be increased before the buffer is passed to CRC computation, or the crc32 function will access uninitialized memory. This was pointed out to me by clg@kaod.org during the code review of a similar patch to hw/net/ftgmac100.c Change-Id: Ib0464303b191af1e28abeb2f5105eb25aadb5e9b Signed-off-by: Stephen Longfield <slongfield@google.com> Reviewed-by: Patrick Venture <venture@google.com> Message-id: 20221221183202.3788132-1-slongfield@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05i.MX7D: Connect IRQs to GPIO devices.Jean-Christophe Dubois
IRQs were not associated to the various GPIO devices inside i.MX7D. This patch brings the i.MX7D on par with i.MX6. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 20221226101418.415170-1-jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05i.MX6UL: Add a specific GPT timer instance for the i.MX6ULJean-Christophe Dubois
The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05i.MX7D: Compute clock frequency for the fixed frequency clocks.Jean-Christophe Dubois
CCM derived clocks will have to be added later. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05i.MX7D: Connect GPT timers to IRQJean-Christophe Dubois
So far the GPT timers were unable to raise IRQs to the processor. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/arm/smmu-common: Avoid using inlined functions with external linkagePhilippe Mathieu-Daudé
When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)") and building with -Wall we get: hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_by_asid_iova' is used in an inline function with external linkage [-Wstatic-in-inline] hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 'smmu_iotlb_inv_iova' internal linkage void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, ^ static None of our code base require / use inlined functions with external linkage. Some places use internal inlining in the hot path. These two functions are certainly not in any hot path and don't justify any inlining, so these are likely oversights rather than intentional. Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20221216214924.4711-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scopePhilippe Mathieu-Daudé
This function is not used anywhere outside this file, so we can make the function "static void". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20221216214924.4711-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/arm/nseries: Silent -Wmissing-field-initializers warningPhilippe Mathieu-Daudé
Silent when compiling with -Wextra: ../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer [-Wmissing-field-initializers] { NULL } ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221220142520.24094-4-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/arm/nseries: Constify various read-only arraysPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221220142520.24094-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo argPhilippe Mathieu-Daudé
The pointed MouseTransformInfo structure is accessed read-only. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221220142520.24094-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05Merge tag 'mem-2023-01-02' of https://github.com/davidhildenbrand/qemu into ↵Peter Maydell
staging Hi, "Host Memory Backends" and "Memory devices" queue ("mem"): - virtio-mem fixes - Use new MPOL_PREFERRED_MANY mbind() policy for memory backends if possible # gpg: Signature made Mon 02 Jan 2023 11:22:04 GMT # gpg: using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A # gpg: issuer "david@redhat.com" # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [marginal] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] # gpg: aka "David Hildenbrand <hildenbr@in.tum.de>" [unknown] # Primary key fingerprint: 1BD9 CAAD 735C 4C3A 460D FCCA 4DDE 10F7 00FF 835A * tag 'mem-2023-01-02' of https://github.com/davidhildenbrand/qemu: hostmem: Honor multiple preferred nodes if possible virtio-mem: Fix typo in function name virtio-mem: Fix the iterator variable in a vmem->rdl_list loop virtio-mem: Fix the bitmap index of the section offset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/timer/imx_epit: fix compare timer handlingAxel Heider
- fix #1263 for CR writes - rework compare time handling - The compare timer has to run even if CR.OCIEN is not set, as SR.OCIF must be updated. - The compare timer fires exactly once when the compare value is less than the current value, but the reload values is less than the compare value. - The compare timer will never fire if the reload value is less than the compare value. Disable it in this case. Signed-off-by: Axel Heider <axel.heider@hensoldt.net> [PMM: fixed minor style nits] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/timer/imx_epit: remove explicit fields cnt and freqAxel Heider
The CNT register is a read-only register. There is no need to store it's value, it can be calculated on demand. The calculated frequency is needed temporarily only. Note that this is a migration compatibility break for all boards types that use the EPIT peripheral. Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/timer/imx_epit: factor out register write handlersAxel Heider
Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/timer/imx_epit: hard reset initializes CR with 0Axel Heider
Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/timer/imx_epit: update interrupt state on CR write accessAxel Heider
The interrupt state can change due to: - reset clears both SR.OCIF and CR.OCIE - write to CR.EN or CR.OCIE Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/timer/imx_epit: define SR_OCIFAxel Heider
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/timer/imx_epit: cleanup CR definesAxel Heider
remove unused defines, add needed defines Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/timer/imx_epit: improve commentsAxel Heider
Fix typos, add background information Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04hw/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_set_irqRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04hw/mips: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_mips_irq_requestRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-28virtio-mem: Fix typo in function namePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221228130956.80515-1-philmd@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2022-12-28virtio-mem: Fix the iterator variable in a vmem->rdl_list loopChenyi Qiang
It should be the variable rdl2 to revert the already-notified listeners. Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager interface") Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20221228090312.17276-1-chenyi.qiang@intel.com> Cc: qemu-stable@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2022-12-28virtio-mem: Fix the bitmap index of the section offsetChenyi Qiang
vmem->bitmap indexes the memory region of the virtio-mem backend at a granularity of block_size. To calculate the index of target section offset, the block_size should be divided instead of the bitmap_size. Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager interface") Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20221216062231.11181-1-chenyi.qiang@intel.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-stable@nongnu.org Signed-off-by: David Hildenbrand <david@redhat.com>
2022-12-23hw/9pfs: Replace the direct call to xxxat() APIs with a wrapperBin Meng
xxxat() APIs are only available on POSIX platforms. For future extension to Windows, let's replace the direct call to xxxat() APIs with a wrapper. Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20221219102022.2167736-4-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23hw/9pfs: Drop unnecessary *xattr wrapper API declarationsBin Meng
These are not used anywhere in the source tree. Drop them. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20221219102022.2167736-3-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-239pfs: Fix some return statements in the synth backendGreg Kurz
The qemu_v9fs_synth_mkdir() and qemu_v9fs_synth_add_file() functions currently return a positive errno value on failure. This causes checkpatch.pl to spit several errors like the one below: ERROR: return of an errno should typically be -ve (return -EAGAIN) + return EAGAIN; Simply change the sign. This has no consequence since callers assert() the returned value to be equal to 0. Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <166930551818.827792.10663674346122681963.stgit@bahia> [C.S.: - Resolve conflict with 66997c42e02c. ] Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-21Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into stagingPeter Maydell
ppc patch queue for 2022-12-21: This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC, the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of them for the e500 board). # gpg: Signature made Wed 21 Dec 2022 17:18:53 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu: target/ppc: Check DEXCR on hash{st, chk} instructions target/ppc: Implement the DEXCR and HDEXCR hw/ppc/e500: Move comment to more appropriate place hw/ppc/e500: Resolve variable shadowing hw/ppc/e500: Prefer local variable over qdev_get_machine() hw/ppc/virtex_ml507: Prefer local over global variable target/ppc/mmu_common: Fix table layout of "info tlb" HMP command target/ppc/mmu_common: Log which effective address had no TLB entry found hw/ppc/spapr: Reduce "vof.h" inclusion hw/ppc/vof: Do not include the full "cpu.h" target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h" hw/ppc/e500: Add Freescale eSDHC to e500plat hw/sd/sdhci: Support big endian SD host controller interfaces MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes' Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-21hw/ppc/e500: Move comment to more appropriate placeBernhard Beschow
The TLB entries are set up in mmubooke_create_initial_mapping(), not in booke206_page_size_to_tlb(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20221216145709.271940-7-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/e500: Resolve variable shadowingBernhard Beschow
Assign to the outer variable instead which even saves some code. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20221216145709.271940-6-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/e500: Prefer local variable over qdev_get_machine()Bernhard Beschow
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-5-shentey@gmail.com> [danielhb: remove linebreak in object_property_add_child()] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/virtex_ml507: Prefer local over global variableBernhard Beschow
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-4-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-17 16:40:02 +0000