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2012-02-22jazz-led: convert to QOMHervé Poussineau
Some simplifications in I/O functions are possible because Jazz LED only registers one byte of I/O. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22jazz-led: use trace frameworkHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22pci: set memory type for memory behind the bridgeMichael S. Tsirkin
As we make upper bits in IO and prefetcheable memory registers writeable, we should declare support for 64 bit prefetcheable memory and 32 bit io in the bridge. This changes the default for apb, dec, but I'm guessing they got the defaults wrong by accident. Alternatively, we could let bridges declare lack of 64 bit support and make the upper bits read-only zero. With this applied, we can drop these bits from express code. Reported-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Could someone familiar with apb,dec ack this please? Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22pci: add accessors to get/set registers by maskMichael S. Tsirkin
pci_regs.h specifies many registers by mask + shifted register values. There's always some duplication when using such: for example to override device type, we would need: pci_word_test_and_clear_mask(cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_TYPE); pci_word_test_and_set_mask(cap + PCI_EXP_FLAGS, PCI_EXP_TYPE_ENDPOINT << (ffs(PCI_EXP_FLAGS_TYPE) - 1)); Getting such registers also uses some duplication: word = pci_get_word(cap + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_TYPE; if ((word >> ffs((PCI_EXP_FLAGS_TYPE) - 1)) == PCI_EXP_TYPE_ENDPOINT) Add API to access such registers in one line: pci_set_word_by_mask(cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ENDPOINT) and word = pci_get_word_by_mask(cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_TYPE) if (word == PCI_EXP_TYPE_ENDPOINT) Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22pc_piix/pc_sysfw: enable flash by defaultJordan Justen
Now, the pc-sysfw:rom_only property will default to false which enables flash by default. All pc types below pc-1.1 set rom_only to true. This prevents flash from being enabled on these pc machine types. For pc-1.1 rom_only will use the default (false), which will allow flash to be used for pc-1.1. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22hw/pc_piix: add pc-1.1Jordan Justen
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22hw/pc_piix: remove is_default for pc-0.15Jordan Justen
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22hw/pc_sysfw: support system flash memory with pflashJordan Justen
Flash can be enabled by calling pc_system_firmware_init with the system_flash_enabled parameter being non-zero. If system_flash_enabled is zero, then the older qemu rom creation method will be used. If flash is enabled and a pflash image is found, then it is used for the system firmware image. If flash is enabled and a pflash image is not initially found, then a read-only pflash device is created using the -bios filename. KVM cannot execute from a pflash region currently. Therefore, when KVM is enabled, the old rom based initialization method is used. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22hw/pc_sysfw: enable pc-sysfw as a qdevJordan Justen
Setup a pc-sysfw device type. It contains a single property of 'rom_only' which is defaulted to enabled. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22hw/pc: move rom init to pc_sysfw.cJordan Justen
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22vl: make find_default_machine externally visibleJordan Justen
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22pflash_cfi01/02: support read-only pflash devicesJordan Justen
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22Merge remote-tracking branch 'bonzini/qdev-props-for-anthony' into stagingAnthony Liguori
* bonzini/qdev-props-for-anthony: qdev: drop unnecessary parse/print methods qdev: use built-in QOM string parser qdev: accept hex properties only if prefixed by 0x qdev: accept both strings and integers for PCI addresses qom: add generic string parsing/printing qapi: add tests for string-based visitors qapi: add string-based visitors qapi: drop qmp_input_end_optional qapi: allow sharing enum implementation across visitors
2012-02-22qdev: drop unnecessary parse/print methodsPaolo Bonzini
More qdev printers could have been removed in the previous series, and object_property_parse also made several parsers unnecessary. In fact, the new code is even more robust with respect to overflows, so clean them up! Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-02-22qdev: use built-in QOM string parserPaolo Bonzini
object_property_parse lets us drop the legacy setters when their task is done just as well by the string visitors. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-02-22qdev: accept hex properties only if prefixed by 0xPaolo Bonzini
Hex properties are an obstacle to removal of old qdev string parsing, but even here we can lay down the foundations for future simplification. In general, they are rarely used and their printed form is more interesting than the parsing. For example you'd usually set isa-serial.index instead of isa-serial.iobase. And luckily our main client, libvirt only cares about few of these, and always sets them with a 0x prefix. So the series stops accepting bare hexadecimal numbers, preparing for making legacy properties read-only in 1.3 or so. The read side will stay as long as "info qtree" is with us. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-02-22qdev: accept both strings and integers for PCI addressesPaolo Bonzini
Visitors allow a limited form of polymorphism. Exploit it to support setting the non-legacy PCI address property both as a DD.F string and as an 8-bit integer. The 8-bit integer form is just too clumsy, it is unlikely that we will ever drop it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-02-21qxl: add user-friendly bar size propertiesGerd Hoffmann
Add two properties to specify bar sizes in megabytes instead of bytes, which is alot more user-friendly. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-02-21qxl: move ram size init to new functionGerd Hoffmann
Factor memory bar sizing bits out to a separate function. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-02-21qxl: drop vram bar minimum sizeGerd Hoffmann
There is no reason to require a minimum size of 16 MB for the vram. Lower the limit to 4096 (one page). Make it disapper completely would break guests.
2012-02-21qxl: make sure primary surface is saved on migration also in compat modeYonit Halperin
RHBZ #790083 Signed-off-by: Yonit Halperin <yhalperi@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-02-21qxl: set only off-screen surfaces dirty instead of the whole vramYonit Halperin
We used to assure the guest surfaces were saved before migration by setting the whole vram dirty. This patch sets dirty only the areas that are actually used in the vram. Signed-off-by: Yonit Halperin <yhalperi@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-02-21qxl: don't render stuff when the vm is stopped.Gerd Hoffmann
This patch fixes the local qxl renderer to not kick spice-server in case the vm is stopped. First it is largely pointless because we ask spice-server to process all not-yet processed commands when the vm is stopped, so there isn't much do do anyway. Second we avoid triggering an assert in spice-server. The patch makes sure we still honor redraw requests, even if we don't ask spice-server for updates. This is needed to handle displaysurface changes with a stopped vm correctly. With this patch applied it is possible to take screen shots (via screendump monitor command) from a qxl gpu even in case the guest is stopped. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-02-21qxl: fix warnings on 32bitGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-02-17i8259: Do not clear level-triggered lines in IRR on initJan Kiszka
When an input line is handled as level-triggered, it will immediately raise an IRQ on the output of a PIC again that goes through an init reset. So only clear the edge-triggered inputs from IRR in that scenario. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17i8254: Factor out pit_get_channel_infoJan Kiszka
Instead of providing 4 individual query functions for mode, gate, output and initial counter state, introduce a service that queries all information at once. This comes with tiny additional costs for pcspk_callback but with a much cleaner interface. Also, it will simplify the implementation of the KVM in-kernel PIT model. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17pcspk: Convert to qdevJan Kiszka
Convert the PC speaker device to a qdev ISA model. Move the public interface to a dedicated header file at this chance. CC: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17i8254: Rework & fix interaction with HPET in legacy modeJan Kiszka
When the HPET enters legacy mode, the IRQ output of the PIT is suppressed and replaced by the HPET timer 0. But the current code to emulate this was broken in many ways. It reset the PIT state after re-enabling, it worked against a stale static PIT structure, and it did not properly saved/restored the IRQ output mask in the PIT vmstate. This patch solves the PIT IRQ control in a different way. On x86, it both redirects the PIT IRQ to the HPET, just like the RTC. But it also keeps the control line from the HPET to the PIT. This allows to disable the PIT QEMU timer when it is not needed. The PIT's view on the control line state is now saved in the same format that qemu-kvm is already using. Note that, in contrast to the suppressed RTC IRQ line, we do not need to save/restore the PIT line state in the HPET. As we trigger a PIT IRQ update via the control line, the line state is reconstructed on mode switch. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17i8254: Pass alternative IRQ output object on initializationJan Kiszka
HPET legacy emulation will require control over the PIT IRQ output. To enable this, add support for an alternative IRQ output object to the PIT factory function. If the isa_irq number is < 0, this object will be used. This also removes the IRQ number property from the PIT class as we now use a generic GPIO output pin that is connected by the factory function. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17i8254: Factor out interface headerJan Kiszka
Move the public interface of the PIT into its own header file and update all users. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17hpet: Save/restore cached RTC IRQ levelJan Kiszka
In legacy mode, the HPET suppresses the RTC interrupt delivery via IRQ 8 but keeps track of the RTC output level and applies it when legacy mode is turned off again. This value has to be preserved across save/ restore as it cannot be reconstructed otherwise. To document that a raised rtc_irq_level won't survive a vmload without a hpet/rtc_irq_level subsection, add an explicit clearing to the reset handler. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17i8254: Do not raise IRQ level on resetJan Kiszka
Avoid changing the IRQ level to high on reset as it may trigger spurious events. Instead, open-code the effects of pit_load_count(0) in the reset handler. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17qdev: Fix qdev_try_create() semanticsAndreas Färber
Since QOM'ification, qdev_try_create() uses object_new() internally, which asserts "type != NULL" when the type is not registered. This was revealed by the combination of kvmclock's kvm_enabled() check and early QOM type registration. Check whether the class exists before calling object_new(), so that the caller (e.g., qdev_create) can fail gracefully, telling us which device could not be created. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Anthony Liguori <aliguori@codemonkey.ws> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-17Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into stagingAnthony Liguori
* pmaydell/arm-devs.for-upstream: (22 commits) hw/pl031: Actually raise interrupt on timer expiry MAINTAINERS: Add hw/highbank.c maintainer Remove unnecessary includes of primecell.h hw/primecell.h: Remove obsolete pl080_init() declaration hw/arm_sysctl: Drop legacy init function hw/vexpress.c: Add vexpress-a15 machine arm_boot: Pass base address of GIC CPU interface, not whole GIC hw/vexpress.c: Instantiate the motherboard CLCD hw/vexpress.c: Factor out daughterboard-specific initialization hw/vexpress.c: Move secondary CPU boot code to SRAM hw/vexpress.c: Make motherboard peripheral memory map table-driven hw/a15mpcore.c: Add Cortex-A15 private peripheral model MAINTAINERS: Add maintainers for Exynos SOC. Exynos4210: added display controller implementation hw/exynos4210.c: Add LAN support for SMDKC210. hw/lan9118: Add basic 16-bit mode support. ARM: exynos4210: MCT support. ARM: exynos4210: basic Power Management Unit implementation ARM: exynos4210: PWM support. ARM: exynos4210: UART support ...
2012-02-17Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori
* stefanha/trivial-patches: linux-user: brk() debugging virtio: Remove unneeded g_free() check in virtio_cleanup() net: remove extra spaces in help messages fmopl: Fix typo in function name vl.c: Fix typo in variable name ide: fix compilation errors when DEBUG_IDE is set cpu-exec.c: Correct comment about this file and indentation cleanup CODING_STYLE: Clarify style for enum and function type names linux-user: fail execve() if env/args too big
2012-02-17hw/pl031: Actually raise interrupt on timer expiryPeter Maydell
Fix a typo in pl031_interrupt() which meant we were setting a bit in the interrupt mask rather than the interrupt status register and thus not actually raising an interrupt. This fix allows the rtctest program from the kernel's Documentation/rtc.txt to pass rather than hanging. Reported-by: Daniel Forsgren <daniel.forsgren@enea.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-02-17Remove unnecessary includes of primecell.hPeter Maydell
The primecell.h header now only has the definitions of constants indicating the usage of the arm_sysctl GPIO lines; remove obsolete includes of it from source files which don't care about those GPIO lines. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17hw/primecell.h: Remove obsolete pl080_init() declarationPeter Maydell
Remove an obsolete declaration of pl080_init(), which has been incorrect since the conversion of pl080 to qdev back in 2009. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17hw/arm_sysctl: Drop legacy init functionPeter Maydell
Drop the legacy init function arm_sysctl_init(), since it has no users left any more. This allows us to drop the awkward '1' from the actual device init function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-02-17hw/vexpress.c: Add vexpress-a15 machinePeter Maydell
Add the vexpress-a15 machine, and the A-Series memory map it uses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-02-17arm_boot: Pass base address of GIC CPU interface, not whole GICPeter Maydell
The arm_boot secondary boot loader code needs the address of the GIC CPU interface. Obtaining this from the base address of the private peripheral region was possible for A9 and 11MPcore, but the A15 puts the GIC CPU interface in a different place. So make boards pass in the GIC CPU interface address directly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17hw/vexpress.c: Instantiate the motherboard CLCDPeter Maydell
Instantiate the CLCD on the vexpress motherboard as well as one on the daughterboard -- the A15 daughterboard does not have a CLCD and so relies on the motherboard one. At the moment QEMU doesn't provide infrastructure for selecting which display device gets to actually show graphics -- the first one registered is it. Fortunately this works for the major use case (Linux): if the daughterboard has a CLCD it will come first and be used, otherwise we fall back to the motherboard CLCD. So we don't (currently) need to implement the control register which allows software to tell the mux which video output to pass through to the outside world. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-02-17hw/vexpress.c: Factor out daughterboard-specific initializationPeter Maydell
Factor out daughterboard specifics into a data structure and daughterboard initialization function, in preparation for adding vexpress-a15 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17hw/vexpress.c: Move secondary CPU boot code to SRAMPeter Maydell
On real Versatile Express hardware, the boot ROM puts the secondary CPU bootcode/holding pen in SRAM. We can therefore rely on Linux not trashing this memory until secondary CPUs have booted up, and can put our QEMU-specific pen code in the same place. This allows us to drop the odd "hack" RAM page we were using before. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17hw/vexpress.c: Make motherboard peripheral memory map table-drivenPeter Maydell
Pull the addresses used for mapping motherboard peripherals into memory out into a table. This will allow us to simply provide a second table to implement the "Cortex-A Series" memory map used by the A15 variant of Versatile Express, as well as the current "Legacy" map used by A9. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-02-17hw/a15mpcore.c: Add Cortex-A15 private peripheral modelPeter Maydell
Add a model of the Cortex-A15 memory mapped private peripheral space. This is fairly simple because the only memory mapped bit of the A15 is the GIC. Note that we don't currently model a VGIC and therefore don't map the VGIC related bits of the GIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17Exynos4210: added display controller implementationMitsyanko Igor
Exynos4210 display controller (FIMD) has 5 hardware windows with alpha and chroma key blending functions. Signed-off-by: Mitsyanko Igor <i.mitsyanko@samsung.com> Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17hw/exynos4210.c: Add LAN support for SMDKC210.Evgeny Voevodin
SMDKC210 uses lan9215 chip, but lan9118 in 16-bit mode seems to be enough. Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17hw/lan9118: Add basic 16-bit mode support.Evgeny Voevodin
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-02-17ARM: exynos4210: MCT support.Evgeny Voevodin
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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