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2008-12-24Improve PPC device debuggingblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6126 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-23Implement hw/eccmemctl.c version differences (Robert Reif)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6124 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-23Implement tick interrupt disable bitsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6122 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc
Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-21hw/slavio_misc.c remove address from debug trace (Robert Reif)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6119 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-21add Arbiter Enable Register support to sparc iommu (Robert Reif)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6118 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-20target-ppc: modify hw/ppc_oldword.c to use qemu_ram_alloc()aurel32
This patch uses qemu_ram_alloc() to allocate RAM, VGA RAM and VGA BIOS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Laurent Vivier <Laurent@lvivier.info> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6114 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-20target-ppc: default to a G3 cpu when emulating a G3 PowerMacaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6113 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19ETRAX: Correct the frequency of the free-running counter.edgar_igl
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6101 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-18PCI: Mask writes to RO bits in the command reg of PCI config spaceaurel32
The Command register in the PCI config space has some read-only bits. Any writes to those bits should be masked out. Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6092 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-18PCI: Mask writes to RO bits in the status reg of PCI config spaceaurel32
The Status register in the PCI config space has some read-only bits. Any writes to those bits should be masked out. Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6091 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-18Remove trailing spaces introduced by commit 6081aurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6085 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-18Fix warnings introduced by commit 6081aurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6084 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-17Add HPET emulation to qemu (Beth Kon)aliguori
This patch adds HPET emulation. It can be disabled with -disable-hpet. An hpet provides a more finely granular clocksource than otherwise available on PC. This means that latency-dependent applications (e.g. multimedia) will generally be smoother when using the HPET. Signed-off-by: Beth Kon <eak@us.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6081 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-17Handle suspend in qemu (Gleb Natapov)aliguori
Reset a PC and tell BIOS that resume from ram is required on the next boot. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6080 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-17Use saner types for virtio-netaliguori
This was spotted by malc Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6075 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-17virtio-net supportaliguori
This adds virtio-net support. This is based on the virtio-net driver that exists in kvm-userspace. This also adds a new qemu_sendv_packet which virtio-net requires. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6073 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-16target-ppc: IBM PowerPC 440EP Bamboo reference board emulationaurel32
Since most IO devices are integrated into the 440EP chip, "Bamboo support" mostly entails implementing the -kernel, -initrd, and -append options. These options are implemented by loading the guest as if u-boot had done it, i.e. loading a flat device tree, updating it to hold initrd addresses, ram size, and command line, and passing the FDT address in r3. Since we use it with KVM, we enable the virtio block driver and include hooks necessary for KVM support. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6067 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-16target-ppc: PowerPC 440EP SoC emulationaurel32
Wire up the system-on-chip devices present on 440EP chips. This patch is a little unusual in that qemu doesn't actually emulate the 440 core, but we use this board code with KVM (which does). If/when 440 core emulation is supported, the kvm_enabled() hack can be removed. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6066 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15target-ppc: create a helper function to allow more flexible RAM allocation ↵aurel32
for PPC 4xx The 4xx SDRAM controller supports a small number of banks, and each bank must be one of a small set of sizes. The number of banks and the supported sizes varies by SoC. This function uses the user-specified RAM size to fill in the "ram_bases" and "ram_sizes" arrays required by ppc4xx_sdram_init(). Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6063 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15target-ppc: rename ppc405_sdram_init() to ppc4xx_sdram_init()aurel32
The SDRAM controller is shared across almost all 405 and 440 embedded processors, with some slight differences such as the sizes supported for each memory bank. Rename only; no functional changes. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6062 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15target-ppc: move PPC4xx SDRAM controller emulation from ppc405_uc.c to ↵aurel32
ppc4xx_devs.c The SDRAM controller is shared across almost all 405 and 440 embedded processors, with some slight differences such as the sizes supported for each memory bank. Code movement only; no functional changes. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6061 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15Revert part of r5853blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6057 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15ARM: basic SX1-cellphone sysemu support (Jean-Christophe PLAGNIOL-VILLARD).balrog
The TSC2102 chip is not included in documentation because a patch is pending. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6038 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15Fix the PXA2xx LCD dirty page detection a little more.balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6037 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13Fix PXA2xx framebuffer dirty checking.balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6019 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13Remove unnecessary trailing newlinesblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11PPC405EP: fix fpga write functionaurel32
I'm not familiar with this device, but I'm fairly certain the writel handler is not supposed to recurse. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5995 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11baum: remove 2 warningsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5994 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11pci: virtio: use pci id defines (Gerd Hoffman)aliguori
Use the defines added by the previous patch in the virtio drivers. Also remove the pointless vendor and device args from the virtio_blk_init() function. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5987 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11pci: add default pci subsystem id for all devices (Gerd Hoffman)aliguori
This sets a default PCI subsystem ID for all emulated PCI devices. PCI specs require this, so do it. In many cases it is enougth to know the PCI ID to handle a device correctly. Sometimes a device driver must identify the exact piece of hardware (via PCI Subsystem ID) though. What does this patch to qemu devices: Right now the emulated PCI devices have no PCI subsystem ID, only the PCI ID. The discussed patch sets a default PCI subsystem ID for all emulated devices. Which will make the qemu devices look pretty much like in the laptop case: all PCI subsystem IDs will point to qemu by default. If a driver emulates a very specific piece of hardware where it has to emulate more than just the PCI chip, it can overwrite the PCI subsystem ID without problems. The es1370 driver does that for example. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5986 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11Rename fls to qemu_flsblueswir1
Fix compiler warning on OSX, reported by Andreas Faerber. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5982 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11Allow to register a callback with fw_cfg_add_callback()blueswir1
fw_cfg_add_callback() checks if key has FW_CFG_WRITE_CHANNEL bit set after masking the key with FW_CFG_ENTRY_MASK. But as FW_CFG_ENTRY_MASK is ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL), the bit is never set and function exits. This patch corrects this by checking the bit before masking the value. Signed-by-off: Laurent Vivier <Laurent.Vivier@bull.net> Acked-by: Gleb Natapov <gleb@redhat.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5978 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11Add missing static qualifiermalc
Caught by -Wstrict-prototypes git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5975 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10IDE: Implement SEEK commandaurel32
Signed-off-by: Justin Chevrier <theburner1@yahoo.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5972 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10Add 64-bit Block Move support (Direct & Table Indirect) (Ryan Harper)aliguori
This patch adds support for 64-bit Block Move instructions. There are multiple modes for 64-bit Block moves, direct, indirect, and table indirect. This patch implements Direct and Table indirect moves which are needed by 64-bit windows and SYM_CONF_DMA_ADDRESSING_MODE=2 for the Linux sym53c8xx_2 driver respectively. Two helper functions are included to check which mode the guest is using. For 64-bit direct moves, we fetch a 3rd DWORD and store the value in the DBMS register. For Table Indirect moves, we look into the table for which register contains the upper 32-bits of the 64-bit address. This selector value indicates which register to pull the value from and into dnad64 register. Finally, lsi_do_dma is updated to use the approriate register to build a 64-bit DMA address if required. With this patch, Windows XP x64, 2003 SP2 x64, can now install to scsi devices. Linux SYM_CONF_DMA_ADDRESSING_MODE=2 need a quirk fixup in Patch 4 to function properly. Signed-off-by: Ryan Harper <ryanh@us.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5969 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10LSI53C895A: Rename dmbs register to dbms (Ryan Harper)aliguori
Register name should be: Dynamic Block Move Selector (dbms) according to page 215 of the LSI 53C895A Technical Manual[1]. 1. http://www.lsi.com/DistributionSystem/AssetDocument/files/docs/techdocs/storage_stand_prod/SCSIControllers/lsi53c895a_tech_manual.pdf Signed-off-by: Ryan Harper <ryanh@us.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5968 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10MIPS Magnum: fix memory-mapped i8042aurel32
Current implementation of memory-mapped i8042 controller is atm implemented with an interface shift (it_shift) parameter, like most all memory-mapped devices in Qemu. However, this isn't suitable for MIPS Magnum, where i8042 controller is at 0x80005000 up to 0x80005fff. Thomas Bogendoerfer (from #mipslinux) tested the behaviour of a real machine, and found that odd addresses are for status/command register, and even addresses for data register. Attached patch implements this behaviour by replacing the it_shift parameter by a mask one. Incidentally, keyboard now works on OpenBSD 2.3, which accesses i8042 controller at 0x80005060 and 0x80005061. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5962 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-09KVM: Coalesced MMIO supportaliguori
MMIO exits are more expensive in KVM or Xen than in QEMU because they involve, at least, privilege transitions. However, MMIO write operations can be effectively batched if those writes do not have side effects. Good examples of this include VGA pixel operations when in a planar mode. As it turns out, we can get a nice boost in other areas too. Laurent mentioned a 9.7% performance boost in iperf with the coalesced MMIO changes for the e1000 when he originally posted this work for KVM. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5961 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Move spitz microdrive to PCMCIA socket 0.balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5946 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07MIPS: remove a few warningsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Parallel port resetaurel32
Attached patch adds a reset handler to parallel port, so it gets correct register values after a reset. (Hervé Poussineau) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5942 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07target-ppc: kill a few warningsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: SCI improvementaurel32
This patch simply implement one register of SH4's SCI := Serial Communication Interface. R2D evaluation board uses SCI for SPI connection. So, Linux kernel for R2D with default configuration causes a QEMU assertion failure when it initializes SPI driver. This patch avoids it and reduces the kernel config modification work for QEMU. Completing SCI implementation task is left. Other board support is desirable to confirm this task, which uses SCI for a serial terminal. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5939 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: kill a few warningsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).balrog
Main purpose of this is to delete *physical = address & 0x1fffffff; at target-sh4/helper.c:449, using new mmio rule introduced by #5849 This masking is a nice trick to realize P4/A7 duality of SH registers. But, IMHO, it is logically wrong. Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have one more address called A7 which is usually P4 address with upper 3bits masked. This is an address only appears in TLB's physical address part. Current code use trick writing drivers as if they are really in A7 (that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: improve the way sh7750 registers io memory (Takashi YOSHII).balrog
Fixes to be needed for commit #5849 "Change MMIO callbacks..." hw/sh7750.c: - Divide region of CPU control registers to avoid overlapping to peripheral modules. - Delete unused var "icr", which had moved to hw/sh_intc.c. hw/sm501.c: - Merge non page aligned palette registers into the region of control registers. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5934 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Fix some new warnings introduced after r5022blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5933 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: r2d pci support (Takashi YOSHII).balrog
This patch adds pci support to sh/r2d board. This is the first user of PCIC support I formerly sent. PCIC actually is inside of chip with CPU core on SH7751. But, this code is written as if SH7750 and PCIC are on board. I care little about physical device boundary, but fitting with qemu's design. This patch also adds some BSC (Bus State Controller) registers, because PCI device driver software have to accesses them. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5932 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: Don't subtract bases from access addresses in PCIC.balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5928 c046a42c-6fe2-441c-8c8c-71466251a162
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