aboutsummaryrefslogtreecommitdiff
path: root/hw
AgeCommit message (Expand)Author
2021-09-30spapr/xive: Fix kvm_xive_source_reset trace eventCédric Le Goater
2021-09-30spapr_numa.c: fixes in spapr_numa_FORM2_write_rtas_tables()Daniel Henrique Barboza
2021-09-30hw/intc: openpic: Clean up the stylesBin Meng
2021-09-30hw/intc: openpic: Drop Raven related codesBin Meng
2021-09-30hw/intc: openpic: Correct the reset value of IPIDR for FSL chipsetBin Meng
2021-09-30target/ppc: Fix 64-bit decrementerCédric Le Goater
2021-09-30target/ppc: Convert debug to trace events (decrementer and IRQ)Cédric Le Goater
2021-09-30spapr_numa.c: handle auto NUMA node with no distance infoDaniel Henrique Barboza
2021-09-30spapr_numa.c: FORM2 NUMA affinity supportDaniel Henrique Barboza
2021-09-30spapr: move FORM1 verifications to post CASDaniel Henrique Barboza
2021-09-30spapr_numa.c: rename numa_assoc_array to FORM1_assoc_arrayDaniel Henrique Barboza
2021-09-30spapr_numa.c: parametrize FORM1 macrosDaniel Henrique Barboza
2021-09-30spapr_numa.c: scrap 'legacy_numa' conceptDaniel Henrique Barboza
2021-09-30spapr_numa.c: split FORM1 code into helpersDaniel Henrique Barboza
2021-09-30target/ppc: Replace debug messages by asserts for unknown IRQ pinsCédric Le Goater
2021-09-30memory_hotplug.c: send DEVICE_UNPLUG_GUEST_ERROR in acpi_memory_hotplug_write()Daniel Henrique Barboza
2021-09-30spapr: use DEVICE_UNPLUG_GUEST_ERROR to report unplug errorsDaniel Henrique Barboza
2021-09-29spapr_drc.c: do not error_report() when drc->dev->id == NULLDaniel Henrique Barboza
2021-09-29spapr.c: handle dev->id in spapr_memory_unplug_rollback()Daniel Henrique Barboza
2021-09-29memory_hotplug.c: handle dev->id = NULL in acpi_memory_hotplug_write()Daniel Henrique Barboza
2021-09-29ppc/pnv: Add an assert when calculating the RAM distribution on chipsCédric Le Goater
2021-09-29ppc/pnv: Rename "id" to "quad-id" in PnvQuadCédric Le Goater
2021-09-29ppc/xive: Export xive_tctx_word2() helperCédric Le Goater
2021-09-29ppc/xive: Export priority_to_ipb() helperCédric Le Goater
2021-09-29ppc/pnv: Remove useless variableCédric Le Goater
2021-09-29ppc/pnv: Add a comment on the "primary-topology-index" propertyCédric Le Goater
2021-09-29ppc/spapr: Add a POWER10 DD2 CPUCédric Le Goater
2021-09-29i386/kvm: Replace abs64() with uabs64() from host-utilsLuis Pires
2021-09-27hw/loader: Restrict PC_ROM_* definitions to hw/i386/pcPhilippe Mathieu-Daudé
2021-09-24hw/nvme: Return error for fused operationsPankaj Raghav
2021-09-24hw/nvme: fix verification of select field in namespace attachmentNaveen Nagar
2021-09-24hw/nvme: fix validation of ASQ and ACQKlaus Jensen
2021-09-21Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson
2021-09-21Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921'...Peter Maydell
2021-09-21Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210920' int...Peter Maydell
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis
2021-09-21hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transferFrank Chang
2021-09-21hw/dma: sifive_pdma: allow non-multiple transaction size transactionsGreen Wan
2021-09-21hw/dma: sifive_pdma: claim bit must be set before DMA transactionsFrank Chang
2021-09-21hw/dma: sifive_pdma: reset Next* registers when Control.claim is setFrank Chang
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis
2021-09-21hw/timer: Add SiFive PWM supportAlistair Francis
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: sifive_clint: Use RISC-V CPU GPIO linesAlistair Francis
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-30 20:48:10 +0000