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2022-10-24aspeed/smc: Cache AspeedSMCClassCédric Le Goater
Store a reference on the AspeedSMC class under the flash object and use it when accessing the flash contents. Avoiding the class cast checkers in these hot paths improves performance by 10% when running the aspeed avocado tests. Message-Id: <20220923084803.498337-7-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-10-24ssi: cache SSIPeripheralClass to avoid GET_CLASS()Alex Bennée
Investigating why some BMC models are so slow compared to a plain ARM virt machines I did some profiling of: ./qemu-system-arm -M romulus-bmc -nic user \ -drive file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \ -nographic -serial mon:stdio And saw that object_class_dynamic_cast_assert was dominating the profile times. We have a number of cases in this model of the SSI bus. As the class is static once the object is created we just cache it and use it instead of the dynamic case macros. Profiling against: ./tests/venv/bin/avocado run \ tests/avocado/machine_aspeed.py:test_arm_ast2500_romulus_openbmc_v2_9_0 Before: 35.565 s ± 0.087 s After: 15.713 s ± 0.287 s Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220811151413.3350684-6-alex.bennee@linaro.org> Message-Id: <20220923084803.498337-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-10-24hw/i2c/aspeed: Fix old reg slave receivePeter Delevoryas
I think when Klaus ported his slave mode changes from the original patch series to the rewritten I2C module, he changed the behavior of the first byte that is received by the slave device. What's supposed to happen is that the AspeedI2CBus's slave device's i2c_event callback should run, and if the event is "send_async", then it should populate the byte buffer with the 8-bit I2C address that is being sent to. Since we only support "send_async", the lowest bit should always be 0 (indicating that the master is requesting to send data). This is the code Klaus had previously, for reference. [1] switch (event) { case I2C_START_SEND: bus->buf = bus->dev_addr << 1; bus->buf &= I2CD_BYTE_BUF_RX_MASK; bus->buf <<= I2CD_BYTE_BUF_RX_SHIFT; bus->intr_status |= (I2CD_INTR_SLAVE_ADDR_RX_MATCH | I2CD_INTR_RX_DONE); aspeed_i2c_set_state(bus, I2CD_STXD); break; [1]: https://lore.kernel.org/qemu-devel/20220331165737.1073520-4-its@irrelevant.dk/ Fixes: a8d48f59cd021b25 ("hw/i2c/aspeed: add slave device in old register mode") Signed-off-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Message-Id: <20220820225712.713209-2-peter@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-10-24m68k: write bootinfo as rom section and re-randomize on rebootJason A. Donenfeld
Rather than poking directly into RAM, add the bootinfo block as a proper ROM, so that it's restored when rebooting the system. This way, if the guest corrupts any of the bootinfo items, but then tries to reboot, it'll still be restored back to normal as expected. Then, since the RNG seed needs to be fresh on each boot, regenerate the RNG seed in the ROM when reseting the CPU. Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Message-Id: <20221023191340.36238-1-Jason@zx2c4.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-10-22Drop useless casts from g_malloc() & friends to pointerMarkus Armbruster
These memory allocation functions return void *, and casting to another pointer type is useless clutter. Drop these casts. If you really want another pointer type, consider g_new(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220923120025.448759-3-armbru@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-10-22hw/core: Tidy up unnecessary casting away of constMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220923120025.448759-2-armbru@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-10-21m68k: rework BI_VIRT_RNG_SEED as BI_RNG_SEEDJason A. Donenfeld
Following a change on the kernel side (see link), pass BI_RNG_SEED instead of BI_VIRT_RNG_SEED. This should have no impact on compatibility, as there will simply be no effect if it's an old kernel, which is how things have always been. We then use this as an opportunity to add this to q800, since now we can, which is a nice improvement. Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Laurent Vivier <laurent@vivier.eu> Link: https://lore.kernel.org/lkml/20220923170340.4099226-3-Jason@zx2c4.com/ Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Message-Id: <20220926113900.1256630-1-Jason@zx2c4.com> [lv: s/^I/ /g] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-10-20hw/ide/microdrive: Use device_cold_reset() for self-resetsPeter Maydell
Currently the microdrive code uses device_legacy_reset() to reset itself, and has its reset method call reset on the IDE bus as the last thing it does. Switch to using device_cold_reset(). The only concrete microdrive device is the TYPE_DSCM1XXXX; it is not command-line pluggable, so it is used only by the old pxa2xx Arm boards 'akita', 'borzoi', 'spitz', 'terrier' and 'tosa'. You might think that this would result in the IDE bus being reset automatically, but it does not, because the IDEBus type does not set the BusClass::reset method. Instead the controller must explicitly call ide_bus_reset(). We therefore leave that call in md_reset(). Note also that because the PCMCIA card device is a direct subclass of TYPE_DEVICE and we don't model the PCMCIA controller-to-card interface as a qbus, PCMCIA cards are not on any qbus and so they don't get reset when the system is reset. The reset only happens via the dscm1xxxx_attach() and dscm1xxxx_detach() functions during machine creation. Because our aim here is merely to try to get rid of calls to the device_legacy_reset() function, we leave these other dubious reset-related issues alone. (They all stem from this code being absolutely ancient.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221013174042.1602926-1-peter.maydell@linaro.org
2022-10-20hw/char/pl011: fix baud rate calculationBaruch Siach
The PL011 TRM says that "UARTIBRD = 0 is invalid and UARTFBRD is ignored when this is the case". But the code looks at FBRD for the invalid case. Fix this. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Message-id: 1408f62a2e45665816527d4845ffde650957d5ab.1665051588.git.baruchs-c@neureality.ai Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-18Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi
* configure: don't enable firmware for targets that are not built * configure: don't use strings(1) * scsi, target/i386: switch from device_legacy_reset() to device_cold_reset() * target/i386: AVX support for TCG * target/i386: fix SynIC SINT assertion failure on guest reset * target/i386: Use atomic operations for pte updates and other cleanups * tests/tcg: extend SSE tests to AVX * virtio-scsi: send "REPORTED LUNS CHANGED" sense data upon disk hotplug events # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmNOlOcUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNuvwgAj/Z5pI9KU33XiWKFR3bZf2lHh21P # xmTzNtPmnP1WHDY1DNug/UB+BLg3c+carpTf5n3B8aKI4X3FfxGSJvYlXy4BONFD # XqYMH3OZB5GaR8Wza9trNYjDs/9hOZus/0R6Hqdl/T38PlMjf8mmayULJIGdcFcJ # WJvITVntbcCwwbpyJbRC5BNigG8ZXTNRoKBgtFVGz6Ox+n0YydwKX5qU5J7xRfCU # lW41LjZ0Fk5lonH16+xuS4WD5EyrNt8cMKCGsxnyxhI7nehe/OGnYr9l+xZJclrh # inQlSwJv0IpUJcrGCI4Xugwux4Z7ZXv3JQ37FzsdZcv/ZXpGonXMeXNJ9A== # =o6x7 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 18 Oct 2022 07:58:31 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (53 commits) target/i386: remove old SSE decoder target/i386: move 3DNow to the new decoder tests/tcg: extend SSE tests to AVX target/i386: Enable AVX cpuid bits when using TCG target/i386: implement VLDMXCSR/VSTMXCSR target/i386: implement XSAVE and XRSTOR of AVX registers target/i386: reimplement 0x0f 0x28-0x2f, add AVX target/i386: reimplement 0x0f 0x10-0x17, add AVX target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX target/i386: reimplement 0x0f 0x38, add AVX target/i386: Use tcg gvec ops for pmovmskb target/i386: reimplement 0x0f 0x3a, add AVX target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX target/i386: reimplement 0x0f 0x70-0x77, add AVX target/i386: reimplement 0x0f 0x78-0x7f, add AVX target/i386: reimplement 0x0f 0x50-0x5f, add AVX target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX target/i386: reimplement 0x0f 0x60-0x6f, add AVX target/i386: Introduce 256-bit vector helpers ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-10-18Merge tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu into stagingStefan Hajnoczi
ppc patch queue for 2022-10-18: This queue contains improvements in the e500 and ppc4xx boards, changes in the maintainership of the project, a new QMP/HMP command and bug fixes: - Cedric is stepping back from qemu-ppc maintainership; - ppc4xx_sdram: QOMification and clean ups; - e500: add new types of flash and clean ups; - QMP/HMP: introduce dumpdtb command; - spapr_pci, booke doorbell interrupt and xvcmp* bit fixes; The 'dumpdtb' implementation is also making changes to RISC-V files that were acked by Alistair Francis and are being included in this queue. # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCY02qEgAKCRA82cqW3gMx # ZIadAQCYY9f+NFrSJBm3z4JjUaP+GmbgEjibjZW05diyKwbqzQEAjE1KXFCcd40D # 3Brs2Dm4YruaJCwb68vswVQAYteXaQ8= # =hl94 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 17 Oct 2022 15:16:34 EDT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu: (38 commits) hw/riscv: set machine->fdt in spike_board_init() hw/riscv: set machine->fdt in sifive_u_machine_init() hw/ppc: set machine->fdt in spapr machine hw/ppc: set machine->fdt in pnv_reset() hw/ppc: set machine->fdt in pegasos2_machine_reset() hw/ppc: set machine->fdt in xilinx_load_device_tree() hw/ppc: set machine->fdt in sam460ex_load_device_tree() hw/ppc: set machine->fdt in bamboo_load_device_tree() hw/nios2: set machine->fdt in nios2_load_dtb() qmp/hmp, device_tree.c: introduce dumpdtb hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset() target/ppc: Fix xvcmp* clearing FI bit hw/ppc/e500: Remove if statement which is now always true hw/ppc/mpc8544ds: Add platform bus hw/ppc/mpc8544ds: Rename wrongly named method hw/ppc/e500: Reduce usage of sysbus API docs/system/ppc/ppce500: Add heading for networking chapter hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx hw/ppc/meson: Allow e500 boards to be enabled separately ppc440_uc.c: Remove unneeded parenthesis ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-10-18hyperv: fix SynIC SINT assertion failure on guest resetMaciej S. Szmigiero
Resetting a guest that has Hyper-V VMBus support enabled triggers a QEMU assertion failure: hw/hyperv/hyperv.c:131: synic_reset: Assertion `QLIST_EMPTY(&synic->sint_routes)' failed. This happens both on normal guest reboot or when using "system_reset" HMP command. The failing assertion was introduced by commit 64ddecc88bcf ("hyperv: SControl is optional to enable SynIc") to catch dangling SINT routes on SynIC reset. The root cause of this problem is that the SynIC itself is reset before devices using SINT routes have chance to clean up these routes. Since there seems to be no existing mechanism to force reset callbacks (or methods) to be executed in specific order let's use a similar method that is already used to reset another interrupt controller (APIC) after devices have been reset - by invoking the SynIC reset from the machine reset handler via a new x86_cpu_after_reset() function co-located with the existing x86_cpu_reset() in target/i386/cpu.c. Opportunistically move the APIC reset handler there, too. Fixes: 64ddecc88bcf ("hyperv: SControl is optional to enable SynIc") # exposed the bug Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Message-Id: <cb57cee2e29b20d06f81dce054cbcea8b5d497e8.1664552976.git.maciej.szmigiero@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-18hw/scsi/vmw_pvscsi.c: Use device_cold_reset() to reset SCSI devicesPeter Maydell
Currently the vwm_pvscsi controller resets individual SCSI devices with the device_legacy_reset() function. The only difference between this and device_cold_reset() is that device_legacy_reset() resets the device but not any child qbuses it might have. In this case, no SCSI device has a child qbus, so the functions have the same behaviour. Switch to device_cold_reset() to move away from using the deprecated function, and bring this SCSI controller in to line with what all the others do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20221013160623.1296109-3-peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-18scsi: Use device_cold_reset() and bus_cold_reset()Peter Maydell
In the SCSI subsystem we currently use the legacy functions qdev_reset_all() and qbus_reset_all(). These perform a recursive reset, starting from either a qbus or a qdev. However they do not permit any of the devices in the tree to use three-phase reset, because device reset goes through the device_legacy_reset() function that only calls the single DeviceClass::reset method. Switch to using the device_cold_reset() and bus_cold_reset() functions. These also perform a recursive reset, where first the children are reset and then finally the parent, but they use the new (...in 2020...) Resettable mechanism, which supports both the old style single-reset method and also the new 3-phase reset handling. Since no devices attached to SCSI buses currently try to use 3-phase reset, this should be a no-behaviour-change commit which just reduces the use of a deprecated API. Commit created with: sed -i -e 's/qdev_reset_all/device_cold_reset/g;s/qbus_reset_all/bus_cold_reset/g' hw/scsi/*.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20221013160623.1296109-2-peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-17hw/riscv: set machine->fdt in spike_board_init()Daniel Henrique Barboza
This will enable support for the 'dumpdtb' QMP/HMP command for the spike machine. Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alistair Francis <alistair.francis@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-16-danielhb413@gmail.com>
2022-10-17hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza
This will enable support for 'dumpdtb' QMP/HMP command for the sifive_u machine. Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-15-danielhb413@gmail.com>
2022-10-17hw/ppc: set machine->fdt in spapr machineDaniel Henrique Barboza
The pSeries machine never bothered with the common machine->fdt attribute. We do all the FDT related work using spapr->fdt_blob. We're going to introduce a QMP/HMP command to dump the FDT, which will rely on setting machine->fdt properly to work across all machine archs/types. Let's set machine->fdt in two places where we manipulate the FDT: spapr_machine_reset() and CAS. There are other places where the FDT is manipulated in the pSeries machines, most notably the hotplug/unplug path. For now we'll acknowledge that we won't have the most accurate representation of the FDT, depending on the current machine state, when using this QMP/HMP fdt command. Making the internal FDT representation always match the actual FDT representation that the guest is using is a problem for another day. spapr->fdt_blob is left untouched for now. To replace it with machine->fdt, since we're migrating spapr->fdt_blob, we would need to migrate machine->fdt as well. This is something that we would like to to do keep our code simpler but it's also a work we'll leave for later. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-14-danielhb413@gmail.com>
2022-10-17hw/ppc: set machine->fdt in pnv_reset()Daniel Henrique Barboza
This will enable support for the 'dumpdtb' QMP/HMP command for all powernv machines. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-13-danielhb413@gmail.com>
2022-10-17hw/ppc: set machine->fdt in pegasos2_machine_reset()Daniel Henrique Barboza
We'll introduce a QMP/HMP command that requires machine->fdt to be set properly. Cc: BALATON Zoltan <balaton@eik.bme.hu> Cc: qemu-ppc@nongnu.org Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-12-danielhb413@gmail.com>
2022-10-17hw/ppc: set machine->fdt in xilinx_load_device_tree()Daniel Henrique Barboza
This will enable support for 'dumpdtb' QMP/HMP command for the virtex_ml507 machine. Setting machine->fdt requires a MachineState pointer to be used inside xilinx_load_device_tree(). Let's change the function to receive this pointer from the caller. kernel_cmdline' can be retrieved directly from the 'machine' pointer. 'ramsize' wasn't being used so can be removed. Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-11-danielhb413@gmail.com>
2022-10-17hw/ppc: set machine->fdt in sam460ex_load_device_tree()Daniel Henrique Barboza
This will enable support for 'dumpdtb' QMP/HMP command for the sam460ex machine. Setting machine->fdt requires a MachineState pointer to be used inside sam460ex_load_device_tree(). Let's change the function to receive this pointer from the caller. 'ramsize' and 'kernel_cmdline' can be retrieved directly from the 'machine' pointer. Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-10-danielhb413@gmail.com>
2022-10-17hw/ppc: set machine->fdt in bamboo_load_device_tree()Daniel Henrique Barboza
This will enable support for 'dumpdtb' QMP/HMP command for the bamboo machine. Setting machine->fdt requires a MachineState pointer to be used inside bamboo_load_device_tree(). Let's change the function to receive this pointer from the caller. 'ramsize' and 'kernel_cmdline' can be retrieved directly from the 'machine' pointer. Cc: Cédric Le Goater <clg@kaod.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-9-danielhb413@gmail.com>
2022-10-17hw/nios2: set machine->fdt in nios2_load_dtb()Daniel Henrique Barboza
This will enable support for 'dumpdtb' QMP/HMP command for all nios2 machines that uses nios2_load_dtb(). Cc: Chris Wulff <crwulff@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220926173855.1159396-7-danielhb413@gmail.com>
2022-10-17hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset()Peter Maydell
In spapr_phb_children_reset() we call device_legacy_reset() to reset any QOM children of the SPAPR PCI host bridge device. This will not reset any qbus such a child might own. Switch to device_cold_reset(), which will reset both the device and its buses. (If the child has no qbuses then there will be no change in behaviour.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221014142841.2092784-1-peter.maydell@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17hw/ppc/e500: Remove if statement which is now always trueBernhard Beschow
Now that the MPC8544DS board also has a platform bus, the if statement is always true. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221003203142.24355-8-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17hw/ppc/mpc8544ds: Add platform busBernhard Beschow
Models the real device more closely. Address and size values are taken from mpc8544.dts from the linux-5.17.7 tree. The IRQ range is taken from e500plat.c. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20221003203142.24355-7-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17hw/ppc/mpc8544ds: Rename wrongly named methodBernhard Beschow
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221003203142.24355-6-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17hw/ppc/e500: Reduce usage of sysbus APIBernhard Beschow
PlatformBusDevice has an mmio attribute which gets aliased to SysBusDevice::mmio[0]. So PlatformbusDevice::mmio can be used directly, avoiding the sysbus API. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20221003203142.24355-5-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxxBernhard Beschow
Having a dedicated config switch makes dependency handling cleaner. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221003203142.24355-3-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17hw/ppc/meson: Allow e500 boards to be enabled separatelyBernhard Beschow
Gives users more fine-grained control over what should be compiled into QEMU. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221003203142.24355-2-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_uc.c: Remove unneeded parenthesisBALATON Zoltan
Remove unneeded parenthesis around case labels. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <19db326bea989c03e08f2853f789315bbe806fe9.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_uc.c: Move some macros to ppc4xx.hBALATON Zoltan
These are used by both the SDRAM controller model and system DCRs. In preparation to move SDRAM controller in its own file move these macros to the ppc4xx.h header. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <74d9bf4891e2ccceb52bb6ca6b54fd3f37a9fb04.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_sdram: QOM'ifyBALATON Zoltan
Change the ppc440_sdram model to a QOM class derived from the PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly modelling the DDR2 SDRAM controller found in the 460EX (used on the sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX) may have this controller but we only emulate enough of it for the sam460ex u-boot firmware. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <3e82ae575c7c41e464a0082d55ecb4ebcc4d4329.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_sdram: Move RAM size check to ppc440_sdram_initBALATON Zoltan
Move the check for valid memory sizes from board to sdram controller init. This adds the missing valid memory sizes of 16 and 8 MiB to the DoC and the board now only checks for additional restrictions imposed by its firmware then sdram init checks for valid sizes for SoC. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <41da3797392acaacc7963b79512c8af8005fa4b0.1664021647.git.balaton@eik.bme.hu> [danielhb: avoid 4*GiB size due to 32 bit build problems] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc4xx_sdram: Rename functions to prevent name clashesBALATON Zoltan
Rename functions to avoid name clashes when moving the DDR2 controller model currently called ppc440_sdram to ppc4xx_devs. This also more clearly shows which function belongs to which model. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <9c09d10fbf36940ebbe30d7038d69cf3f2e58371.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_sdram: Rename local variable for readabilityBALATON Zoltan
Rename local sdram variable in ppc440_sdram_init to s for readability. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <7351b80fa321c32a6229e685dfdc940232f8b788.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_sdram: Get rid of the init RAM hackBALATON Zoltan
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM controller from the board. Firmware does this so it may only be needed when booting with -kernel without firmware but we enable SDRAM unconditionally to preserve previous behaviour. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <c2eda8f83c82f655aa7821a5a8c9310484bd6a1d.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_sdram: Implement enable bit in the DDR2 SDRAM controllerBALATON Zoltan
To allow removing the do_init hack we need to improve the DDR2 SDRAM controller model to handle the enable/disable bit that it ignored so far. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <f8900aadb1a4426a6444741e6876c898b3b77f7b.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_sdram: Split off map/unmap of sdram banks for later reuseBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <23560b6a71682d513f3dd8e9ed3852f51d5eb309.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc4xx_sdram: Drop extra zeros for readabilityBALATON Zoltan
Constants that are written zero padded for no good reason are hard to read, it's easier to see what is meant if it's just 0 or 1 instead. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <93974622c3d398c7d3a3488b678b74c3807849de.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc4xx_sdram: QOM'ifyBALATON Zoltan
Change the ppc4xx_sdram model to a QOM class derived from the PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly modelling the DDR SDRAM controller found in the 440EP (used on the bamboo board) but also backward compatible with the older DDR controllers on some 405 SoCs so we also use it for those now. This likely does not cause problems for guests we run as the new features are just not accessed but to model 405 SoC accurately some features may have to be disabled or the model split between 440 and older. Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an updated DDR2 SDRAM controller implemented by the ppc440_sdram model (only partially, enough for the 460EX on the sam460ex) that is not yet QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2 when QOM'ified later. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <8f820487fc9011343032c422ecdf3e8ee74d8c11.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc4xx_sdram: Move size check to ppc4xx_sdram_init()BALATON Zoltan
Instead of checking if memory size is valid in board code move this check to ppc4xx_sdram_init() as this is a restriction imposed by the SDRAM controller. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <39e5129dd095b285676a6267c5753786da1bc30d.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_bamboo: Add missing 4 MiB valid memory sizeBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <05836e38be84729c1c6b5b609e7aa2ea60435033.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()BALATON Zoltan
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead of the separate arrays and adjust ppc4xx_sdram_init() and ppc440_sdram_init() accordingly as well as machines using these. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <e3a1fea51f29779fd6a61be90a29c684f3299544.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc4xx_sdram: Get rid of the init RAM hackBALATON Zoltan
The do_init parameter of ppc4xx_sdram_init() is used to map memory regions that is normally done by the firmware by programming the SDRAM controller. Do this from board code emulating what firmware would do when booting a kernel directly from -kernel without a firmware so we can get rid of this do_init hack. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <d6c44c870befa1a075e21f1a59926dcdaff63f6b.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc4xx: Introduce Ppc4xxSdramBank structBALATON Zoltan
Instead of storing sdram bank parameters in unrelated arrays put them in a struct so it's clear they belong to the same bank and simplify the state struct using this bank type. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <5eb82d0424c584b2b9e6f7bc51560f8189ed21bb.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17ppc440_bamboo: Remove unnecessary memsetsBALATON Zoltan
In ppc4xx_sdram_init() the struct is allocated with g_new0() so no need to clear its elements. In the bamboo machine init memset can be replaced with array initialiser which is shorter. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <529adc7705fb3e3e777439895bdaa136bacb9403.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-17hw/intc: Fix LoongArch ipi device emulationXiaojuan Yang
In ipi_send function, it should not to set irq before writing data to dest cpu iocsr space, as the irq will trigger after data writing. When call this function 'address_space_stl()', it will trigger loongarch_ipi_writel(), the addr arg is 0x1008 ('CORE_SET_OFF'), and qemu_irq_raise will be called in this case. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220930095139.867115-3-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-10-14hw/intc: sifive_plic: change interrupt priority register to WARL fieldJim Shu
PLIC spec [1] requires interrupt source priority registers are WARL field and the number of supported priority is power-of-2 to simplify SW discovery. Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC spec, whose number of supported priority is not power-of-2. Just change each bit of interrupt priority register to WARL field when the number of supported priority is power-of-2. [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Clément Chigot <chigot@adacore.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221003041440.2320-3-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-10-14hw/intc: sifive_plic: fix hard-coded max priority levelJim Shu
The maximum priority level is hard-coded when writing to interrupt priority register. However, when writing to priority threshold register, the maximum priority level is from num_priorities Property which is configured by platform. Also change interrupt priority register to use num_priorities Property in maximum priority level. Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221003041440.2320-2-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 10:52:08 +0000