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2022-03-02ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10)Cédric Le Goater
POWER10 adds support for StoreEOI operation and 64K ESB pages on PSIHB to be consistent with the other interrupt sources of the system. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add a HOMER model to POWER10Cédric Le Goater
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridgeCédric Le Goater
PHB4 and PHB5 are very similar. Use the PHB4 models with some minor adjustements in a subclass for P10. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add POWER10 quadsCédric Le Goater
and use a pnv_chip_power10_quad_realize() helper to avoid code duplication with P9. This still needs some refinements on the XSCOM registers handling in PnvQuad. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add a OCC model for POWER10Cédric Le Goater
Our OCC model is very mininal and POWER10 can simply reuse the OCC model we introduced for POWER9. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add a XIVE2 controller to the POWER10 chipCédric Le Goater
The XIVE2 interrupt controller of the POWER10 processor follows the same logic than on POWER9 but the HW interface has been largely reviewed. It has a new register interface, different BARs, extra VSDs, new layout for the XIVE2 structures, and a set of new features which are described below. This is a model of the POWER10 XIVE2 interrupt controller for the PowerNV machine. It focuses primarily on the needs of the skiboot firmware but some initial hypervisor support is implemented for KVM use (escalation). Support for new features will be implemented in time and will require new support from the OS. * XIVE2 BARS The interrupt controller BARs have a different layout outlined below. Each sub-engine has now own its range and the indirect TIMA access was replaced with a set of pages, one per CPU, under the IC BAR: - IC BAR (Interrupt Controller) . 4 pages, one per sub-engine . 128 indirect TIMA pages - TM BAR (Thread Interrupt Management Area) . 4 pages - ESB BAR (ESB pages for IPIs) . up to 1TB - END BAR (ESB pages for ENDs) . up to 2TB - NVC BAR (Notification Virtual Crowd) . up to 128 - NVPG BAR (Notification Virtual Process and Group) . up to 1TB - Direct mapped Thread Context Area (reads & writes) OPAL does not use the grouping and crowd capability. * Virtual Structure Tables XIVE2 adds new tables types and also changes the field layout of the END and NVP Virtualization Structure Descriptors. - EAS - END new layout - NVT was splitted in : . NVP (Processor), 32B . NVG (Group), 32B . NVC (Crowd == P9 block group) 32B - IC for remote configuration - SYNC for cache injection - ERQ for event input queue The setup is slighly different on XIVE2 because the indexing has changed for some of the tables, block ID or the chip topology ID can be used. * XIVE2 features SCOM and MMIO registers have a new layout and XIVE2 adds a new global capability and configuration registers. The lowlevel hardware offers a set of new features among which : - a configurable number of priorities : 1 - 8 - StoreEOI with load-after-store ordering is activated by default - Gen2 TIMA layout - A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility - increase to 24bit for VP number Other features will have some impact on the Hypervisor and guest OS when activated, but this is not required for initial support of the controller. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/xive2: Introduce a presenter matching routineCédric Le Goater
The VP space is larger in XIVE2 (P10), 24 bits instead of 19bits on XIVE (P9), and the CAM line can use a 7bits or 8bits thread id. For now, we only use 7bits thread ids, same as P9, but because of the change of the size of the VP space, the CAM matching routine is different between P9 and P10. It is easier to duplicate the whole routine than to add extra handlers in xive_presenter_tctx_match() used for P9. We might come with a better solution later on, after we have added some more support for the XIVE2 controller. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/xive2: Introduce a XIVE2 core frameworkCédric Le Goater
The XIVE2 interrupt controller of the POWER10 processor as the same logic as on POWER9 but its SW interface has been largely reworked. The interrupt controller has a new register interface, different BARs, extra VSDs. These will be described when we add the device model for the baremetal machine. The XIVE internal structures for the EAS, END, NVT have different layouts which is a problem for the current core XIVE framework. To avoid adding too much complexity in the XIVE models, a new XIVE2 core framework is introduced. It duplicates the models which are closely linked to the XIVE internal structures : Xive2Router and Xive2ENDSource and reuses the XiveSource, XivePresenter, XiveTCTX models, as they are more generic. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: fix default PHB4 QOM hierarchyDaniel Henrique Barboza
Commit 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s") changed phb4_pec code to create the default PHB4 objects in pnv_pec_default_phb_realize(). In this process the stacks[] PEC array was removed and each PHB4 object is tied together with its PEC via the phb->pec pointer. This change also broke the previous QOM hierarchy - the PHB4 objects are being created and not being parented to their respective chips. This can be verified by 'info pic' in a powernv9 domain with default settings. pnv_chip_power9_pic_print_info() will fail to find the PHBs because object_child_foreach_recursive() won't find any. The solution is to set the parent chip and the parent bus, in the same way done for user created PHB4 devices, for all PHB4 devices. Fixes: 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220218202804.413157-1-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/pnv: Determine ns16550's IRQ number from QOM propertyBernhard Beschow
Determine the IRQ number in the same way as for pnv_dt_ipmi_bt(). This resolves one usage of ISADevice::isairq[] which allows it to be removed eventually. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-6-shentey@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-01Merge remote-tracking branch ↵Peter Maydell
'remotes/thuth-gitlab/tags/pull-request-2022-02-28' into staging * Fix emulation of the SET CLOCK instruction * Fix the s390x avocado test with Fedora * Update the s390x Travis jobs to Focal (instead of Bionic) * Implement the z15 Misc Instruction Extension 3 Facility # gpg: Signature made Mon 28 Feb 2022 10:34:47 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2022-02-28: tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3 s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1 s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x travis.yml: Update the s390x jobs to Ubuntu Focal tests/avocado/machine_s390_ccw_virtio: Adapt test to new default resolution s390x: sck: load into a temporary not into in1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-01Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2022-02-28' into ↵Peter Maydell
staging QAPI patches patches for 2022-02-28 # gpg: Signature made Mon 28 Feb 2022 10:40:22 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2022-02-28: qapi: Belatedly adjust limitations documentation rtc: Have event RTC_CHANGE identify the RTC by QOM path hw/rtc: Compile pl031 once-only qapi: Document some missing details of RTC_CHANGE event qapi: Move RTC_CHANGE back out of target schema qapi/migration: Fix examples document wrong field name for arguments qapi: Fix stale reference to scripts/qapi.py in a comment keyval: Fix grammar comment to cover downstream prefix scripts/qapi: minor delinting Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' ↵Peter Maydell
into staging aspeed queue: * Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups # gpg: Signature made Sun 27 Feb 2022 08:45:45 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20220227: aspeed/sdmc: Add trace events aspeed/smc: Add an address mask on segment registers aspeed: Introduce a create_pca9552() helper aspeed: rainier: Add strap values taken from hardware aspeed: rainier: Add i2c LED devices ast2600: Add Secure Boot Controller model arm: Remove swift-bmc machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFOAlex Bennée
The previous numbers were a guess at best and rather arbitrary without taking into account anything that might be loaded. Instead of using guesses based on the state of registers implement a new function that: a) scans the MemoryRegions for the largest RAM block b) iterates through all "ROM" blobs looking for the biggest gap The "ROM" blobs include all code loaded via -kernel and the various -device loader techniques. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Andrew Strauss <astrauss11@gmail.com> Cc: Keith Packard <keithp@keithp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220225172021.3493923-18-alex.bennee@linaro.org>
2022-02-28rtc: Have event RTC_CHANGE identify the RTC by QOM pathMarkus Armbruster
Event RTC_CHANGE is "emitted when the guest changes the RTC time" (and the RTC supports the event). What if there's more than one RTC? Which one changed? New @qom-path identifies it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <87a6ejnm80.fsf@pond.sub.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-28hw/rtc: Compile pl031 once-onlyPeter Maydell
Now that the RTC_CHANGE event is no longer target-specific, we can move the pl031 back to a compile-once source file rather than a compile-per-target one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220221192123.749970-4-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-02-28qapi: Move RTC_CHANGE back out of target schemaPeter Maydell
This commit effectively reverts commit 183e4281a30962, which moved the RTC_CHANGE event to the target schema. That change was an attempt to make the event target-specific to improve introspection, but the event isn't really target-specific: it's machine or device specific. Putting RTC_CHANGE in the target schema with an ifdef list reduces maintainability (by adding an if: list with a long list of targets that needs to be manually updated as architectures are added or removed or as new devices gain the RTC_CHANGE functionality) and increases compile time (by preventing RTC devices which emit the event from being "compile once" rather than "compile once per target", because qapi-events-misc-target.h uses TARGET_* ifdefs, which are poisoned in "compile once" files.) Move RTC_CHANGE back to misc.json. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Acked-by: Greg Kurz <groug@kaod.org> Message-Id: <20220221192123.749970-2-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-02-28s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1David Miller
TCG implements everything we need to run basic z15 OS+software Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-3-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-26aspeed/sdmc: Add trace eventsCédric Le Goater
This is useful to analyze changes in the U-Boot RAM driver when SDRAM training is performed. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-26aspeed/smc: Add an address mask on segment registersCédric Le Goater
Only a limited set of bits are used for decoding the Start and End addresses of the mapping window of a flash device. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-26aspeed: Introduce a create_pca9552() helperCédric Le Goater
This unifies the way we create the pca9552 devices on the different boards. Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-26aspeed: rainier: Add strap values taken from hardwareJoel Stanley
When time permits, we should introduce defines for the HW strapping registers to cleanly decode the values. SCU500 = 0x00422016 Disable ARM JTAG trusted world debug: 0x1 Disable ARM JTAG debug: 0x1 VGA Memory Size: 0x1 [16MB] Cortex M3: 0x1 [Disabled] Boot device: 0x1 [eMMC] Reserved: 0x1 SCU510 = 0x80000848 Secure Boot Enable: 0x1 Enable boot SPI or eMMC ABR (second boot): 0x1 Enable LPC mode: 0x1 [LPC] Disable LPC SuperIO 0x2e/0x4e: 0x1 Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: rewrote the commit log ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-26aspeed: rainier: Add i2c LED devicesJoel Stanley
This helps quieten booting the current Rainier kernel. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-26ast2600: Add Secure Boot Controller modelJoel Stanley
Just a stub that indicates the system has booted in secure boot mode. Used for testing the driver: https://lore.kernel.org/all/20211019080608.283324-1-joel@jms.id.au/ Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: - Fixed typo - Adjusted Copyright dates ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-26arm: Remove swift-bmc machineJoel Stanley
It was scheduled for removal in 7.0. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-26hw/openrisc/openrisc_sim: Add support for initrd loadingStafford Horne
The initrd passed via the command line is loaded into memory. It's location and size is then added to the device tree so the kernel knows where to find it. Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-26hw/openrisc/openrisc_sim: Add automatic device tree generationStafford Horne
Using the device tree means that qemu can now directly tell the kernel what hardware is configured rather than use having to maintain and update a separate device tree file. This patch adds automatic device tree generation support for the OpenRISC simulator. A device tree is built up based on the state of the configure openrisc simulator. This is then dumped to memory and the load address is passed to the kernel in register r3. Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-25hw/openrisc/openrisc_sim: Increase max_cpus to 4Stafford Horne
Now that we no longer have a limit of 2 CPUs due to fixing the IRQ routing issues we can increase the max. Here we increase the limit to 4, we could go higher, but currently OMPIC has a limit of 4, so we align with that. Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-25hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UARTStafford Horne
Currently the OpenRISC SMP configuration only supports 2 cores due to the UART IRQ routing being limited to 2 cores. As was done in commit 1eeffbeb11 ("hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs") we can use a splitter to wire more than 2 CPUs. This patch moves serial initialization out to it's own function and uses a splitter to connect multiple CPU irq lines to the UART. Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-25hw/openrisc/openrisc_sim: Parameterize initializationStafford Horne
Move magic numbers to variables and enums. These will be reused for upcoming fdt initialization. Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-25hw/openrisc/openrisc_sim: Create machine state for or1ksimStafford Horne
This will allow us to attach machine state attributes like the device tree fdt. Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-22Merge remote-tracking branch ↵Peter Maydell
'remotes/lvivier-gitlab/tags/trivial-branch-for-7.0-pull-request' into staging Trivial branch pull request 20220222 # gpg: Signature made Tue 22 Feb 2022 16:16:01 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/lvivier-gitlab/tags/trivial-branch-for-7.0-pull-request: hid: Implement support for side and extra buttons vdpa: Make ncs autofree qemu-options: fix incorrect description for '-drive index=' hw/nvram: use at24 macro target/rx: Remove unused ENV_OFFSET definition target/avr: Correct AVRCPUClass docstring configure: Disable capstone and slirp in the --without-default-features mode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-22hid: Implement support for side and extra buttonsNoah Bergbauer
Simply set the respective bits and update the descriptor accordingly. Signed-off-by: Noah Bergbauer <noah@statshelix.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20211126140437.79745-1-noah@statshelix.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-02-22Merge remote-tracking branch ↵Peter Maydell
'remotes/thuth-gitlab/tags/pull-request-2022-02-21' into staging * Improve virtio-net failover test * Some small fixes for the qtests * Misc header cleanups by Philippe # gpg: Signature made Mon 21 Feb 2022 11:40:37 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2022-02-21: (25 commits) hw/tricore: Remove unused and incorrect header hw/m68k/mcf: Add missing 'exec/hwaddr.h' header exec/exec-all: Move 'qemu/log.h' include in units requiring it softmmu/runstate: Clean headers linux-user: Add missing "qemu/timer.h" include target: Add missing "qemu/timer.h" include core/ptimers: Remove unnecessary 'sysemu/cpus.h' include exec/ramblock: Add missing includes qtest: Add missing 'hw/qdev-core.h' include hw/acpi/memory_hotplug: Remove unused 'hw/acpi/pc-hotplug.h' header hw/remote: Add missing include hw/tpm: Clean includes scripts: Remove the old switch-timer-api script tests/qtest: failover: migration abort test with failover off tests/qtest: failover: test migration if the guest doesn't support failover tests/qtest: failover: check migration with failover off tests/qtest: failover: check missing guest feature tests/qtest: failover: check the feature is correctly provided tests/qtest: failover: use a macro for check_one_card() tests/qtest: failover: clean up pathname of tests ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging * More Meson conversions (0.59.x now required rather than suggested) * UMIP support for TCG x86 * Fix migration crash * Restore error output for check-block # gpg: Signature made Mon 21 Feb 2022 09:35:59 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (29 commits) configure, meson: move CONFIG_IASL to a Meson option meson, configure: move ntddscsi API check to meson meson: require dynamic linking for VSS support qga/vss-win32: require widl/midl, remove pre-built TLB file meson: do not make qga/vss-win32/meson.build conditional on C++ presence configure, meson: replace VSS SDK checks and options with --enable-vss-sdk qga/vss: use standard windows headers location qga/vss-win32: use widl if available meson: drop --with-win-sdk qga/vss-win32: fix midl arguments meson: refine check for whether to look for virglrenderer configure, meson: move guest-agent, tools to meson configure, meson: move smbd options to meson_options.txt configure, meson: move coroutine options to meson_options.txt configure, meson: move some default-disabled options to meson_options.txt meson: define qemu_cflags/qemu_ldflags configure, meson: move block layer options to meson_options.txt configure, meson: move image format options to meson_options.txt configure, meson: cleanup qemu-ga libraries configure, meson: move TPM check to meson ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21hw/nvram: use at24 macroPatrick Venture
Use the macro for going from I2CSlave to EEPROMState. Signed-off-by: Patrick Venture <venture@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220119214329.2557049-1-venture@google.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-02-21hw/arm: add initial mori-bmc boardPatrick Venture
This is the BMC attached to the OpenBMC Mori board. Signed-off-by: Patrick Venture <venture@google.com> Reviewed-by: Chris Rauer <crauer@google.com> Reviewed-by: Ilkyun Choi <ikchoi@google.com> Message-id: 20220208233104.284425-1-venture@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21hw/timer: fix a9gtimer vmstatePavel Dovgalyuk
A9 gtimer includes global control field and number of per-cpu fields. But only per-cpu ones are migrated. This patch adds a subsection for global control field migration. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-id: 164422345976.2186660.1104517592452494510.stgit@pasha-ThinkPad-X280 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21include: Move hardware version declarations to new qemu/hw-version.hPeter Maydell
The "hardware version" machinery (qemu_set_hw_version(), qemu_hw_version(), and the QEMU_HW_VERSION define) is used by fewer than 10 files. Move it out from osdep.h into a new qemu/hw-version.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-6-peter.maydell@linaro.org
2022-02-21include: Move qemu_madvise() and related #defines to new qemu/madvise.hPeter Maydell
The function qemu_madvise() and the QEMU_MADV_* constants associated with it are used in only 10 files. Move them out of osdep.h to a new qemu/madvise.h header that is included where it is needed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-2-peter.maydell@linaro.org
2022-02-21hw/arm/armv7m: Handle disconnected clock inputsPeter Maydell
In the armv7m object, handle clock inputs that aren't connected. This is always an error for 'cpuclk'. For 'refclk' it is OK for this to be disconnected, but we need to handle it by not trying to connect a sourceless-clock to the systick device. This fixes a bug where on the mps2-an521 and similar boards (which do not have a refclk) the systick device incorrectly reset with SYST_CSR.CLKSOURCE 0 ("use refclk") rather than 1 ("use CPU clock"). Cc: qemu-stable@nongnu.org Reported-by: Richard Petri <git@rpls.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208171643.3486277-1-peter.maydell@linaro.org
2022-02-21Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c busPeter Maydell
For arm boards with an i2c bus which a user could reasonably want to plug arbitrary devices, add 'imply I2C_DEVICES' to the Kconfig stanza. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20220208155911.3408455-3-peter.maydell@linaro.org
2022-02-21Kconfig: Add I2C_DEVICES device groupPeter Maydell
Currently there is no way for a board model's Kconfig stanza to say "I have an i2c bus which the user can plug an i2c device into, build all the free-standing i2c devices". The Kconfig mechanism for this is the "device group". Add an I2C_DEVICES group along the same lines as the existing PCI_DEVICES. Simple free-standing i2c devices which a user might plausibly want to be able to plug in on the QEMU commandline should have default y if I2C_DEVICES and board models which have an i2c bus that is user-accessible should use imply I2C_DEVICES to cause those pluggable devices to be built. In this commit we mark only a fairly conservative set of i2c devices as belonging to the I2C_DEVICES group: the simple sensors and RTCs (not including PMBus devices or devices which need GPIO lines to be connected). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20220208155911.3408455-2-peter.maydell@linaro.org
2022-02-21Mark remaining global TypeInfo instances as constBernhard Beschow
More than 1k of TypeInfo instances are already marked as const. Mark the remaining ones, too. This commit was created with: git grep -z -l 'static TypeInfo' -- '*.c' | \ xargs -0 sed -i 's/static TypeInfo/static const TypeInfo/' Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20220117145805.173070-2-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21configure, meson: move TPM check to mesonPaolo Bonzini
The check is simply for a POSIX system. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-21exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé
Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-21core/ptimers: Remove unnecessary 'sysemu/cpus.h' includePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220207082756.82600-7-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-21hw/acpi/memory_hotplug: Remove unused 'hw/acpi/pc-hotplug.h' headerPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220207082756.82600-4-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-21hw/remote: Add missing includePhilippe Mathieu-Daudé
Currently "qemu/error-report.h" is implicitly included, however if headers in include/ get refactored, we get: hw/remote/proxy-memory-listener.c: In function ‘proxy_memory_listener_commit’: hw/remote/proxy-memory-listener.c:183:9: error: implicit declaration of function ‘error_report’; did you mean ‘error_report_err’? [-Werror=implicit-function-declaration] 183 | error_report("Number of fds is more than %d", REMOTE_MAX_FDS); | ^~~~~~~~~~~~ | error_report_err Add the missing "qemu/error-report.h" header to avoid that. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jagannathan Raman <jag.raman@oracle.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220207082756.82600-3-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-21hw/tpm: Clean includesPhilippe Mathieu-Daudé
"tpm_ppi.h" only requires to include "exec/memory.h" to get the MemoryRegion declaration. tpm_ppi.c requires "hw/qdev-core.h" to use the DEVICE() macro, tpm_crb.c is the only source file requiring "exec/address-spaces.h". Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220207082756.82600-2-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
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