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2020-02-02ppc/pnv: remove useless "core-pir" property alias.Cédric Le Goater
Commit 158e17a65e1a ("ppc/pnv: Link "chip" property to PnvCore::chip pointer") introduced some cleanups of the PnvCore realize handler. Let's continue by reworking a bit the interface of the PnvCore handlers for the CPU threads. These changes make the "core-pir" property alias unused. Remove it. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144154.10170-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02spapr: Don't allow multiple active vCPUs at CASGreg Kurz
According to the description of "ibm,client-architecture-support" that can found in LoPAPR "B.6.2.3 Root Node Methods": If multiple partition processors or threads are active at the time of the ibm,client-architecture-support method call, or an error is detected in the format of the ibm,architecture.vec structure, the err? boolean shall be TRUE; else FALSE. We certainly don't want to temper with the platform or with the PCR of the other vCPUs if they happen to be active. Ensure we have only one active vCPU and fail CAS otherwise. This is just for conformance and robustness, it doesn't fix any known bugs. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157969867170.571404.12117797348882189656.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02spapr: Fail CAS if option vector table cannot be parsedGreg Kurz
Most of the option vector helpers have assertions to check their arguments aren't null. The guest can provide an arbitrary address for the CAS structure that would result in such null arguments. Fail CAS with H_PARAMETER and print a warning instead of aborting QEMU. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <157925255250.397143.10855183619366882459.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOSThomas Huth
It's been deprecated since QEMU v3.1. The 40p machine should be used nowadays instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200114114617.28854-1-thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc:virtex_ml507: remove unused argumentsIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1579100861-73692-71-git-send-email-imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: improve error logging when a PNOR update failsCédric Le Goater
Print out the offset at which the error occured. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200108090348.21224-3-clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: use QEMU unit definition MiBCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200108090348.21224-2-clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-30hw/display/qxl.c: Use trace_event_get_state_backends()Peter Maydell
The preferred way to test whether a trace event is enabled is to use trace_event_get_state_backends(), because this will give the correct answer (allowing expensive computations to be skipped) whether the trace event is compile-time or run-time disabled. Convert the old-style direct use of TRACE_FOO_ENABLED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200120151142.18954-4-peter.maydell@linaro.org Message-Id: <20200120151142.18954-4-peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-01-30target/arm/cpu: Add the kvm-no-adjvtime CPU propertyAndrew Jones
kvm-no-adjvtime is a KVM specific CPU property and a first of its kind. To accommodate it we also add kvm_arm_add_vcpu_properties() and a KVM specific CPU properties description to the CPU features document. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20200120101023.16030-7-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/arm/virt: Add missing 5.0 options call to 4.2 optionsAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20200120101023.16030-3-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bitZenghui Yu
If LPIs are disabled, KVM will just ignore the GICR_PENDBASER.PTZ bit when restoring GICR_CTLR. Setting PTZ here makes littlt sense in "reduce GIC initialization time". And what's worse, PTZ is generally programmed by guest to indicate to the Redistributor whether the LPI Pending table is zero when enabling LPIs. If migration is triggered when the PTZ has just been cleared by guest (and before enabling LPIs), we will see PTZ==1 on the destination side, which is not as expected. Let's just drop this hackish userspace behavior. Also take this chance to refine the comment a bit. Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions") Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Message-id: 20200119133051.642-1-yuzenghui@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/s390x/ipl: replace deprecated qdev_reset_all registrationDamien Hedde
Replace deprecated qdev_reset_all by resettable_cold_reset_fn for the ipl registration in the main reset handlers. This does not impact the behavior for the following reasons: + at this point resettable just call the old reset methods of devices and buses in the same order than qdev/qbus. + resettable handlers registered with qemu_register_reset are serialized; there is no interleaving. + eventual explicit calls to legacy reset API (device_reset or qdev/qbus_reset) inside this reset handler will not be masked out by resettable mechanism; they do not go through resettable api. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200123132823.1117486-12-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/core: deprecate old reset functions and introduce new onesDamien Hedde
Deprecate device_legacy_reset(), qdev_reset_all() and qbus_reset_all() to be replaced by new functions device_cold_reset() and bus_cold_reset() which uses resettable API. Also introduce resettable_cold_reset_fn() which may be used as a replacement for qdev_reset_all_fn and qbus_reset_all_fn(). Following patches will be needed to look at legacy reset call sites and switch to resettable api. The legacy functions will be removed when unused. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-9-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/core/qdev: update hotplug reset regarding resettableDamien Hedde
This commit make use of the resettable API to reset the device being hotplugged when it is realized. Also it ensures it is put in a reset state coherent with the parent it is plugged into. Note that there is a difference in the reset. Instead of resetting only the hotplugged device, we reset also its subtree (switch to resettable API). This is not expected to be a problem because sub-buses are just realized too. If a hotplugged device has any sub-buses it is logical to reset them too at this point. The recently added should_be_hidden and PCI's partially_hotplugged mechanisms do not interfere with realize operation: + In the should_be_hidden use case, device creation is delayed. + The partially_hotplugged mechanism prevents a device to be unplugged and unrealized from qdev POV and unrealized. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-8-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/core/qdev: handle parent bus change regarding resettableDamien Hedde
In qdev_set_parent_bus(), when changing the parent bus of a realized device, if the source and destination buses are not in the same reset state, some adaptations are required. This patch adds needed call to resettable_change_parent() to make sure a device reset state stays coherent with its parent bus. The addition is a no-op if: 1. the device being parented is not realized. 2. the device is realized, but both buses are not under reset. Case 2 means that as long as qdev_set_parent_bus() is called during the machine realization procedure (which is before the machine reset so nothing is in reset), it is a no op. There are 52 call sites of qdev_set_parent_bus(). All but one fall into the no-op case: + 29 trivial calls related to virtio (in hw/{s390x,display,virtio}/ {vhost,virtio}-xxx.c) to set a vdev(or vgpu) composing device parent bus just before realizing the same vdev(vgpu). + hw/core/qdev.c: when creating a device in qdev_try_create() + hw/core/sysbus.c: when initializing a device in the sysbus + hw/i386/amd_iommu.c: before realizing AMDVIState/pci + hw/isa/piix4.c: before realizing PIIX4State/rtc + hw/misc/auxbus.c: when creating an AUXBus + hw/misc/auxbus.c: when creating an AUXBus child + hw/misc/macio/macio.c: when initializing a MACIOState child + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/pmu + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/cuda + hw/net/virtio-net.c: Used for migration when using the failover mechanism to migration a vfio-pci/net. It is a no-op because at this point the device is already on the bus. + hw/pci-host/designware.c: before realizing DesignwarePCIEHost/root + hw/pci-host/gpex.c: before realizing GPEXHost/root + hw/pci-host/prep.c: when initialiazing PREPPCIState/pci_dev + hw/pci-host/q35.c: before realizing Q35PCIHost/mch + hw/pci-host/versatile.c: when initializing PCIVPBState/pci_dev + hw/pci-host/xilinx-pcie.c: before realizing XilinxPCIEHost/root + hw/s390x/event-facility.c: when creating SCLPEventFacility/ TYPE_SCLP_QUIESCE + hw/s390x/event-facility.c: ditto with SCLPEventFacility/ TYPE_SCLP_CPU_HOTPLUG + hw/s390x/sclp.c: Not trivial because it is called on a SLCPDevice just after realizing it. Ok because at this point the destination bus (sysbus) is not in reset; the realize step is before the machine reset. + hw/sd/core.c: Not OK. Used in sdbus_reparent_card(). See below. + hw/ssi/ssi.c: Used to put spi slave on spi bus and connect the cs line in ssi_auto_connect_slave(). Ok because this function is only used in realize step in hw/ssi/aspeed_smc.ci, hw/ssi/imx_spi.c, hw/ssi/mss-spi.c, hw/ssi/xilinx_spi.c and hw/ssi/xilinx_spips.c. + hw/xen/xen-legacy-backend.c: when creating a XenLegacyDevice device + qdev-monitor.c: in device hotplug creation procedure before realize Note that this commit alone will have no effect, right now there is no use of resettable API to reset anything. So a bus will never be tagged as in-reset by this same API. The one place where side-effect will occurs is in hw/sd/core.c in sdbus_reparent_card(). This function is only used in the raspi machines, including during the sysbus reset procedure. This case will be carrefully handled when doing the multiple phase reset transition. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-7-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/core/resettable: add support for changing parentDamien Hedde
Add a function resettable_change_parent() to do the required plumbing when changing the parent a of Resettable object. We need to make sure that the reset state of the object remains coherent with the reset state of the new parent. We make the 2 following hypothesis: + when an object is put in a parent under reset, the object goes in reset. + when an object is removed from a parent under reset, the object leaves reset. The added function avoids any glitch if both old and new parent are already in reset. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-6-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/core: add Resettable support to BusClass and DeviceClassDamien Hedde
This commit adds support of Resettable interface to buses and devices: + ResettableState structure is added in the Bus/Device state + Resettable methods are implemented. + device/bus_is_in_reset function defined This commit allows to transition the objects to the new multi-phase interface without changing the reset behavior at all. Object single reset method can be split into the 3 different phases but the 3 phases are still executed in a row for a given object. From the qdev/qbus reset api point of view, nothing is changed. qdev_reset_all() and qbus_reset_all() are not modified as well as device_legacy_reset(). Transition of an object must be done from parent class to child class. Care has been taken to allow the transition of a parent class without requiring the child classes to be transitioned at the same time. Note that SysBus and SysBusDevice class do not need any transition because they do not override the legacy reset method. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-5-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/core: create Resettable QOM interfaceDamien Hedde
This commit defines an interface allowing multi-phase reset. This aims to solve a problem of the actual single-phase reset (built in DeviceClass and BusClass): reset behavior is dependent on the order in which reset handlers are called. In particular doing external side-effect (like setting an qemu_irq) is problematic because receiving object may not be reset yet. The Resettable interface divides the reset in 3 well defined phases. To reset an object tree, all 1st phases are executed then all 2nd then all 3rd. See the comments in include/hw/resettable.h for a more complete description. The interface defines 3 phases to let the future possibility of holding an object into reset for some time. The qdev/qbus reset in DeviceClass and BusClass will be modified in following commits to use this interface. A mechanism is provided to allow executing a transitional reset handler in place of the 2nd phase which is executed in children-then-parent order inside a tree. This will allow to transition devices and buses smoothly while keeping the exact current qdev/qbus reset behavior for now. Documentation will be added in a following commit. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-4-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/core/qdev: add trace events to help with resettable transitionDamien Hedde
Adds trace events to reset procedure and when updating the parent bus of a device. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-3-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30add device_legacy_reset function to prepare for reset api changeDamien Hedde
Provide a temporary device_legacy_reset function doing what device_reset does to prepare for the transition with Resettable API. All occurrence of device_reset in the code tree are also replaced by device_legacy_reset. The new resettable API has different prototype and semantics (resetting child buses as well as the specified device). Subsequent commits will make the changeover for each call site individually; once that is complete device_legacy_reset() will be removed. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-2-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'Philippe Mathieu-Daudé
Since we enabled parallel TCG code generation for softmmu (see commit 3468b59 "tcg: enable multiple TCG contexts in softmmu") and its subsequent fix (commit 72649619 "add .min_cpus and .default_cpus fields to machine_class"), the raspi machines are restricted to always use their 4 cores: See in hw/arm/raspi2 (with BCM283X_NCPUS set to 4): 222 static void raspi2_machine_init(MachineClass *mc) 223 { 224 mc->desc = "Raspberry Pi 2"; 230 mc->max_cpus = BCM283X_NCPUS; 231 mc->min_cpus = BCM283X_NCPUS; 232 mc->default_cpus = BCM283X_NCPUS; 235 }; 236 DEFINE_MACHINE("raspi2", raspi2_machine_init) We can no longer use the -smp option, as we get: $ qemu-system-arm -M raspi2 -smp 1 qemu-system-arm: Invalid SMP CPUs 1. The min CPUs supported by machine 'raspi2' is 4 Since we can not set the TYPE_BCM283x SOC "enabled-cpus" with -smp, remove the unuseful code. We can achieve the same by using the '-global bcm2836.enabled-cpus=1' option. Reported-by: Laurent Bonnans <laurent.bonnans@here.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200120235159.18510-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30misc/pca9552: Add qom set and getJoel Stanley
Following the pattern of the work recently done with the ASPEED GPIO model, this adds support for inspecting and modifying the PCA9552 LEDs from the monitor. (qemu) qom-set /machine/unattached/device[17] led0 on (qemu) qom-set /machine/unattached/device[17] led0 off (qemu) qom-set /machine/unattached/device[17] led0 pwm0 (qemu) qom-set /machine/unattached/device[17] led0 pwm1 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-6-clg@kaod.org [clg: - removed the "qom-get" examples from the commit log - merged memory leak fixes from Joel ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0Cédric Le Goater
The overhead for the OpenBMC firmware images using the a custom U-Boot is around 2 seconds, which is fine, but with a U-Boot from mainline, it takes an extra 50 seconds or so to reach Linux. A quick survey on the number of reads performed on the flash memory region gives the following figures : OpenBMC U-Boot 922478 (~ 3.5 MBytes) Mainline U-Boot 20569977 (~ 80 MBytes) QEMU must be trashing the TCG TBs and reloading text very often. Some addresses are read more than 250.000 times. Until we find a solution to improve boot time, execution from MMIO is not activated by default. Setting this option also breaks migration compatibility. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200114103433.30534-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30ftgmac100: check RX and TX buffer alignmentCédric Le Goater
These buffers should be aligned on 16 bytes. Ignore invalid RX and TX buffer addresses and log an error. All incoming and outgoing traffic will be dropped because no valid RX or TX descriptors will be available. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-4-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/arm: ast2600: Wire up the eMMC controllerAndrew Jeffery
Initialise another SDHCI model instance for the AST2600's eMMC controller and use the SDHCI's num_slots value introduced previously to determine whether we should create an SD card instance for the new slot. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-3-clg@kaod.org [ clg : - removed ternary operator from sdhci_attach_drive() - renamed SDHCI objects with a '-controller' prefix ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/sd: Configure number of slots exposed by the ASPEED SDHCI modelAndrew Jeffery
The AST2600 includes a second cut-down version of the SD/MMC controller found in the AST2500, named the eMMC controller. It's cut down in the sense that it only supports one slot rather than two, but it brings the total number of slots supported by the AST2600 to three. The existing code assumed that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-2-clg@kaod.org [PMM: fixed up to use device_class_set_props()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINESPeter Maydell
The num-lines property of the TYPE_OR_GATE device sets the number of input lines it has. An assert() in or_irq_realize() restricts this to the maximum supported by the implementation. However we got the condition in the assert wrong: it should be using <=, because num-lines == MAX_OR_LINES is permitted, and means that all entries from 0 to MAX_OR_LINES-1 in the s->levels[] array are used. We didn't notice this previously because no user has so far needed that many input lines. Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200120142235.10432-1-peter.maydell@linaro.org
2020-01-30Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' ↵Peter Maydell
into staging MIPS queue for January 29th, 2020 # gpg: Signature made Wed 29 Jan 2020 18:29:43 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jan-29-2020: target/mips: Add implementation of GINVT instruction target/mips: Amend CP0 WatchHi register implementation hw/core/loader: Let load_elf() populate a field with CPU-specific flags target/mips: semihosting: Remove 'uhi_done' label in helper_do_semihosting() disas: Add a field for target-dependant data to disassemble_info target/mips: Rectify documentation on deprecating MIPS r4k machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30Merge remote-tracking branch ↵Peter Maydell
'remotes/stefanberger/tags/pull-tpm-2020-01-29-1' into staging Merge tpm 2020/01/29 v1 # gpg: Signature made Wed 29 Jan 2020 13:01:37 GMT # gpg: using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * remotes/stefanberger/tags/pull-tpm-2020-01-29-1: tpm-ppi: page-align PPI RAM Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-29hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic
While loading the executable, some platforms (like AVR) need to detect CPU type that executable is built for - and, with this patch, this is enabled by reading the field 'e_flags' of the ELF header of the executable in question. The change expands functionality of the following functions: - load_elf() - load_elf_as() - load_elf_ram() - load_elf_ram_sym() The argument added to these functions is called 'pflags' and is of type 'uint32_t*' (that matches 'pointer to 'elf_word'', 'elf_word' being the type of the field 'e_flags', in both 32-bit and 64-bit variants of ELF header). Callers are allowed to pass NULL as that argument, and in such case no lookup to the field 'e_flags' will happen, and no information will be returned, of course. CC: Richard Henderson <rth@twiddle.net> CC: Peter Maydell <peter.maydell@linaro.org> CC: Edgar E. Iglesias <edgar.iglesias@gmail.com> CC: Michael Walle <michael@walle.cc> CC: Thomas Huth <huth@tuxfamily.org> CC: Laurent Vivier <laurent@vivier.eu> CC: Philippe Mathieu-Daudé <f4bug@amsat.org> CC: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> CC: Aurelien Jarno <aurelien@aurel32.net> CC: Jia Liu <proljc@gmail.com> CC: David Gibson <david@gibson.dropbear.id.au> CC: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> CC: BALATON Zoltan <balaton@eik.bme.hu> CC: Christian Borntraeger <borntraeger@de.ibm.com> CC: Thomas Huth <thuth@redhat.com> CC: Artyom Tarasenko <atar4qemu@gmail.com> CC: Fabien Chouteau <chouteau@adacore.com> CC: KONRAD Frederic <frederic.konrad@adacore.com> CC: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1580079311-20447-24-git-send-email-aleksandar.markovic@rt-rk.com>
2020-01-29tpm-ppi: page-align PPI RAMMarc-André Lureau
post-copy migration fails on destination with error such as: 2019-12-26T10:22:44.714644Z qemu-kvm: ram_block_discard_range: Unaligned start address: 0x559d2afae9a0 Use qemu_memalign() to constrain the PPI RAM memory alignment. Cc: qemu-stable@nongnu.org Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Message-id: 20200103074000.1006389-3-marcandre.lureau@redhat.com
2020-01-28Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into stagingPeter Maydell
Pull request # gpg: Signature made Tue 28 Jan 2020 01:05:19 GMT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full] # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/ide-pull-request: tests/ide-test: Create a single unit-test covering more PRDT cases ide: Fix incorrect handling of some PRDTs in ide_dma_cb() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-27ide: Fix incorrect handling of some PRDTs in ide_dma_cb()Alexander Popov
The commit a718978ed58a from July 2015 introduced the assertion which implies that the size of successful DMA transfers handled in ide_dma_cb() should be multiple of 512 (the size of a sector). But guest systems can initiate DMA transfers that don't fit this requirement. For fixing that let's check the number of bytes prepared for the transfer by the prepare_buf() handler. The code in ide_dma_cb() must behave according to the Programming Interface for Bus Master IDE Controller (Revision 1.0 5/16/94): 1. If PRDs specified a smaller size than the IDE transfer size, then the Interrupt and Active bits in the Controller status register are not set (Error Condition). 2. If the size of the physical memory regions was equal to the IDE device transfer size, the Interrupt bit in the Controller status register is set to 1, Active bit is set to 0. 3. If PRDs specified a larger size than the IDE transfer size, the Interrupt and Active bits in the Controller status register are both set to 1. Signed-off-by: Alexander Popov <alex.popov@linux.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20191223175117.508990-2-alex.popov@linux.com Signed-off-by: John Snow <jsnow@redhat.com>
2020-01-27hw/hppa/machine: Map the PDC memory region with higher priorityPhilippe Mathieu-Daudé
The region in range [0xf0000000 - 0xf1000000] is the PDC area (Processor Dependent Code), where the firmware is loaded. This region has higher priority than the main memory. When the machine has more than 3840MB of RAM, there is an overlap. Since the PDC is closer to the CPU in the bus hierarchy, it gets accessed first, and the CPU does not have access to the RAM in this range. To model the same behavior and keep a simple memory layout, reduce the priority of the RAM region. The PDC region ends overlapping the RAM. Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200109000525.24744-4-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27hw/hppa/machine: Restrict the total memory size to 3GBPhilippe Mathieu-Daudé
The hardware expects DIMM slots of 1 or 2 GB, allowing up to 4 GB of memory. We want to accept the same amount of memory the hardware can deal with. DIMMs of 768MB are not available. However we have to deal with a firmware limitation: currently SeaBIOS only supports 32-bit, and expects the RAM size in a 32-bit register. When using a 4GB configuration, the 32-bit register get truncated and we report a size of 0MB to SeaBIOS, which ends halting the machine: $ qemu-system-hppa -m 4g -serial stdio SeaBIOS: Machine configured with too little memory (0 MB), minimum is 16 MB. SeaBIOS wants SYSTEM HALT. The easiest way is to restrict the machine to 3GB of memory. Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200109000525.24744-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27hw/hppa/machine: Correctly check the firmware is in PDC rangePhilippe Mathieu-Daudé
The firmware has to reside in the PDC range. If the Elf file expects to load it below FIRMWARE_START, it is incorrect, regardless the RAM size. Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200109000525.24744-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27hppa: Add emulation of Artist graphicsSven Schnelle
This adds emulation of Artist graphics good enough to get a text console on both Linux and HP-UX. The X11 server from HP-UX also works. Adjust boot-serial-test to disable graphics, so that SeaBIOS outputs to the serial port, as expected by the test. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20191220211512.3289-6-svens@stackframe.org> [rth: Merge Helge's test for machine->enable_graphics] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27hppa: Switch to tulip NIC by defaultHelge Deller
Most HP PA-RISC machines have a Digital DS21142/43 Tulip network card, only some very latest generation machines have an e1000 NIC. Since qemu now provides an emulated tulip card, use that one instead. Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20191221222530.GB27803@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27hppa: add emulation of LASI PS2 controllersSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20191220211512.3289-5-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27ps2: accept 'Set Key Make and Break' commandsSven Schnelle
HP-UX sends both the 'Set key make and break (0xfc) and 'Set all key typematic make and break' (0xfa). QEMU response with 'Resend' as it doesn't handle these commands. HP-UX than reports an PS/2 max retransmission exceeded error. Add these commands and just reply with ACK. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20191220211512.3289-4-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27hppa: Add support for LASI chip with i82596 NICHelge Deller
LASI is a built-in multi-I/O chip which supports serial, parallel, network (Intel i82596 Apricot), sound and other functionalities. LASI has been used in many HP PARISC machines. This patch adds the necessary parts to allow Linux and HP-UX to detect LASI and the network card. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20191220211512.3289-3-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27hw/hppa/dino.c: Improve emulation of Dino PCI chipHelge Deller
The tests of the dino chip with the Online-diagnostics CD ("ODE DINOTEST") now succeeds. Additionally add some qemu trace events. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191220211512.3289-2-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-27hw/s390x: Add a more verbose comment about get_machine_class() and the wrappersThomas Huth
While working on the "Enable adapter interruption suppression again" recently, I had to discover that the meaning of get_machine_class() and the related *_allowed() wrappers is not very obvious. Add a more verbose comment here to clarify how these should be used. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200123170256.12386-1-thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-01-27s390x/event-facility: fix error propagationCornelia Huck
We currently check (by error) if the passed-in Error pointer errp is non-null and return after realizing the first child of the event facility in that case. Symptom is that 'virsh shutdown' does not work, as the sclpquiesce device is not realized. Fix this by (correctly) checking the local Error err. Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Fixes: 3d508334dd2c ("s390x/event-facility: Fix realize() error API violations") Message-Id: <20200121095506.8537-1-cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-01-27s390x: adapter routes error handlingCornelia Huck
If the kernel irqchip has been disabled, we don't want the {add,release}_adapter_routes routines to call any kvm_irqchip_* interfaces, as they may rely on an irqchip actually having been created. Just take a quick exit in that case instead. If you are trying to use irqfd without a kernel irqchip, we will fail with an error. Also initialize routes->gsi[] with -1 in the virtio-ccw handling, to make sure we don't trip over other errors, either. (Nobody else uses the gsi array in that structure.) Fixes: d426d9fba8ea ("s390x/virtio-ccw: wire up irq routing and irqfds") Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20200117111147.5006-1-cohuck@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-01-27s390x/event-facility.c: remove unneeded labelsDaniel Henrique Barboza
'out' label from write_event_mask() and write_event_data() can be replaced by 'return'. The 'out' label from read_event_data() can also be replaced. However, as suggested by Cornelia Huck, instead of simply replacing the 'out' label, let's also change the code flow a bit to make it clearer that sccb events are always handled regardless of the mask for unconditional reads, while selective reads are handled if the mask is valid. CC: Cornelia Huck <cohuck@redhat.com> CC: Thomas Huth <thuth@redhat.com> CC: Halil Pasic <pasic@linux.ibm.com> CC: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200108144607.878862-1-danielhb413@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-01-27intc/s390_flic_kvm.c: remove unneeded label in kvm_flic_load()Daniel Henrique Barboza
'out' label can be replaced by 'return' with the appropriate value that is set by 'r' right before the jump. Cc: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200106182425.20312-42-danielhb413@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-01-27s390x/sclp.c: remove unneeded label in sclp_service_call()Daniel Henrique Barboza
'out' label can be replaced by 'return' with the appropriate value. The 'r' integer, which is used solely to set the return value for this label, can also be removed. CC: Cornelia Huck <cohuck@redhat.com> CC: Halil Pasic <pasic@linux.ibm.com> CC: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200106182425.20312-39-danielhb413@gmail.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-01-27Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* Register qdev properties as class properties (Marc-André) * Cleanups (Philippe) * virtio-scsi fix (Pan Nengyuan) * Tweak Skylake-v3 model id (Kashyap) * x86 UCODE_REV support and nested live migration fix (myself) * Advisory mode for pvpanic (Zhenwei) # gpg: Signature made Fri 24 Jan 2020 20:16:23 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (58 commits) build-sys: clean up flags included in the linker command line target/i386: Add the 'model-id' for Skylake -v3 CPU models qdev: use object_property_help() qapi/qmp: add ObjectPropertyInfo.default-value qom: introduce object_property_help() qom: simplify qmp_device_list_properties() vl: print default value in object help qdev: register properties as class properties qdev: move instance properties to class properties qdev: rename DeviceClass.props qdev: set properties with device_class_set_props() object: return self in object_ref() object: release all props object: add object_class_property_add_link() object: express const link with link property object: add direct link flag object: rename link "child" to "target" object: check strong flag with & object: do not free class properties object: add object_property_set_default ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-24qdev: register properties as class propertiesMarc-André Lureau
Use class properties facilities to add properties to the class during device_class_set_props(). qdev_property_add_static() must be adapted as PropertyInfo now operates with classes (and not instances), so we must set_default_value() on the ObjectProperty, before calling its init() method on the object instance. Also, PropertyInfo.create() is now exclusively used for class properties. Fortunately, qdev_property_add_static() is only used in target/arm/cpu.c so far, which doesn't use "link" properties (that require create()). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200110153039.1379601-22-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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