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2021-10-22hw/riscv: microchip_pfsoc: Use MachineState::ram and ↵Bin Meng
MachineClass::default_ram_id Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22hw/intc: sifive_plic: Cleanup the irq_request functionAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
2021-10-22hw/intc: sifive_plic: Cleanup the realize functionAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
2021-10-22hw/intc: sifive_plic: Move the propertiesAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
2021-10-22hw/intc: Remove the Ibex PLICAlistair Francis
The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and instead use the SiFive PLIC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis
Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
2021-10-22speed/sdhci: Add trace eventsCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20211018132609.160008-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-22aspeed/smc: Use a container for the flash mmio address spaceCédric Le Goater
Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225 ("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias") introduced an alias for the flash mmio region. Using a container is cleaner. Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20211018132609.160008-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-22aspeed: Add support for the fp5280g2-bmc boardJohn Wang
The fp5280g2-bmc is supported by OpenBMC, It's based on the following device tree https://github.com/openbmc/linux/blob/dev-5.10/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts Signed-off-by: John Wang <wangzhiqiang02@inspur.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211014064548.934799-1-wangzhiqiang02@inspur.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22hw/riscv: virt: Use machine->ram as the system memoryMingwang Li
If default main_mem is used to be registered as the system memory, other memory cannot be initialized. Therefore, the system memory should be initialized to the machine->ram, which consists of the default main_mem and other possible memory required by applications, such as shared hugepage memory in DPDK. Also, the mc->defaul_ram_id should be set to the default main_mem, such as "riscv_virt_board.ram" for the virt machine. Signed-off-by: Mingwang Li <limingwang@huawei.com> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211016030908.40480-1-limingwang@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-21Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into stagingRichard Henderson
Introduce cpu topology support Generate DBG2 table Switch to ssize_t for elf loader return type Fixed sbsa cpu type error message typo Only initialize required submodules for edk2 Dont create device-tree node for empty NUMA node # gpg: Signature made Thu 21 Oct 2021 08:22:32 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-arm-20211021: tests/data/acpi/virt: Update the empty expected file for PPTT hw/arm/virt-acpi-build: Generate PPTT table tests/data/acpi/virt: Add an empty expected file for PPTT hw/acpi/aml-build: Add PPTT table hw/acpi/aml-build: Add Processor hierarchy node structure hw/arm/virt: Add cpu-map to device tree device_tree: Add qemu_fdt_add_path hw/arm/virt: Only describe cpu topology since virt-6.2 bios-tables-test: Generate reference table for virt/DBG2 hw/arm/virt_acpi_build: Generate DBG2 table tests/acpi: Add void table for virt/DBG2 bios-tables-test hw/elf_ops.h: switch to ssize_t for elf loader return type hw/arm/sbsa-ref: Fixed cpu type error message typo. roms/edk2: Only initialize required submodules roms/edk2: Only init brotli submodule to build BaseTools hw/arm/virt: Don't create device-tree node for empty NUMA node tests/acpi: Generate reference blob for IORT rev E.b hw/arm/virt-acpi-build: IORT upgrade up to revision E.b tests/acpi: Get prepared for IORT E.b revision upgrade Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-21hw/arm/virt-acpi-build: Generate PPTT tableYanan Wang
Generate the Processor Properties Topology Table (PPTT) for ARM virt machines supporting it (>= 6.2). Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20211020142125.7516-8-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-21hw/acpi/aml-build: Add PPTT tableAndrew Jones
Add the Processor Properties Topology Table (PPTT) used to describe CPU topology information to ACPI guests. Note, a DT-boot Linux guest with a non-flat CPU topology will see socket and core IDs being sequential integers starting from zero, which is different from ACPI-boot Linux guest, e.g. with -smp 4,sockets=2,cores=2,threads=1 a DT boot produces: cpu: 0 package_id: 0 core_id: 0 cpu: 1 package_id: 0 core_id: 1 cpu: 2 package_id: 1 core_id: 0 cpu: 3 package_id: 1 core_id: 1 an ACPI boot produces: cpu: 0 package_id: 36 core_id: 0 cpu: 1 package_id: 36 core_id: 1 cpu: 2 package_id: 96 core_id: 2 cpu: 3 package_id: 96 core_id: 3 This is due to several reasons: 1) DT cpu nodes do not have an equivalent field to what the PPTT ACPI Processor ID must be, i.e. something equal to the MADT CPU UID or equal to the UID of an ACPI processor container. In both ACPI cases those are platform dependant IDs assigned by the vendor. 2) While QEMU is the vendor for a guest, if the topology specifies SMT (> 1 thread), then, with ACPI, it is impossible to assign a core-id the same value as a package-id, thus it is not possible to have package-id=0 and core-id=0. This is because package and core containers must be in the same ACPI namespace and therefore must have unique UIDs. 3) ACPI processor containers are not mandatorily required for PPTT tables to be used and, due to the limitations of which IDs are selected described above in (2), they are not helpful for QEMU, so we don't build them with this patch. In the absence of them, Linux assigns its own unique IDs. The maintainers have chosen not to use counters from zero, but rather ACPI table offsets, which explains why the numbers are so much larger than with DT. 4) When there is no SMT (threads=1) the core IDs for ACPI boot guests match the logical CPU IDs, because these IDs must be equal to the MADT CPU UID (as no processor containers are present), and QEMU uses the logical CPU ID for these MADT IDs. So in summary, with QEMU as the vendor for the guests, we simply use sequential integers starting from zero for the non-leaf nodes but with ID-valid flag unset, so that guest will ignore them and use table offsets as unique container IDs. And we use logical CPU IDs for the leaf nodes with the ID-valid flag set, which will be consistent with MADT. Currently the implementation of PPTT generation complies with ACPI specification 5.2.29 (Revision 6.3). The 6.3 spec can be found at: https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf Reviewed-by: Eric Auger <eric.auger@redhat.com> Co-developed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20211020142125.7516-6-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-20hw/acpi/aml-build: Add Processor hierarchy node structureYanan Wang
Add a generic API to build Processor hierarchy node structure (Type 0), which is strictly consistent with descriptions in ACPI 6.3: 5.2.29.1. This function will be used to build ACPI PPTT table for cpu topology. Co-developed-by: Ying Fang <fangying1@huawei.com> Co-developed-by: Henglong Fan <fanhenglong@huawei.com> Co-developed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20211020142125.7516-5-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-20hw/arm/virt: Add cpu-map to device treeAndrew Jones
Support device tree CPU topology descriptions. In accordance with the Devicetree Specification, the Linux Doc "arm/cpus.yaml" requires that cpus and cpu nodes in the DT are present. And we have already met the requirement by generating /cpus/cpu@* nodes for members within ms->smp.cpus. Accordingly, we should also create subnodes in cpu-map for the present cpus, each of which relates to an unique cpu node. The Linux Doc "cpu/cpu-topology.txt" states that the hierarchy of CPUs in a SMP system is defined through four entities and they are socket/cluster/core/thread. It is also required that a socket node's child nodes must be one or more cluster nodes. Given that currently we are only provided with information of socket/core/thread, we assume there is one cluster child node in each socket node when creating cpu-map. Co-developed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Message-Id: <20211020142125.7516-4-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-20hw/arm/virt: Only describe cpu topology since virt-6.2Yanan Wang
On existing older machine types, without cpu topology described in ACPI or DT, the guest will populate one by default. With the topology described, it will read the information and set up its topology as instructed, but that may not be the same as what was getting used by default. It's possible that an user application has a dependency on the default topology and if the default one gets changed it will probably behave differently. Based on above consideration we'd better only describe topology information to the guest on 6.2 and later machine types. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-Id: <20211020142125.7516-2-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-20hw/arm/virt_acpi_build: Generate DBG2 tableEric Auger
ARM SBBR specification mandates DBG2 table (Debug Port Table 2) since v1.0 (ARM DEN0044F 8.3.1.7 DBG2). The DBG2 table allows to describe one or more debug ports. Generate an DBG2 table featuring a single debug port, the PL011. The DBG2 specification can be found at "Microsoft Debug Port Table 2 (DBG2)" https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table?redirectedfrom=MSDN Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20211019080037.930641-3-eric.auger@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-21hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernelsThomas Huth
Recent Linux kernels are accessing the PCI device in slot 0 that represents the PCI host bridge. This causes ppc4xx_pci_map_irq() to return -1 which causes an assert() later: hw/pci/pci.c:262: pci_bus_change_irq_level: Assertion `irq_num >= 0' failed. Thus we should allocate an IRQ line for the device in slot 0, too. To avoid changes to the outside of ppc4xx_pci.c, we map it to the internal IRQ number 4 which will then happily be ignored since ppc440_bamboo.c does not wire it up. With these changes it is now possible again to use recent Linux kernels for the bamboo board. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211019091817.469003-1-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21ppc/pegasos2: Implement power-off RTAS function with VOFBALATON Zoltan
This only helps Linux guests as only that seems to use it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <1c1e030f2bbc86e950b3310fb5922facdc21ef86.1634241019.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21ppc/pegasos2: Add constants for PCI config addressesBALATON Zoltan
Define a constant for PCI config addresses to make it clearer what these numbers are. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <9bd8e84d02d91693b71082a1fadeb86e6bce3025.1634241019.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21ppc/pegasos2: Access MV64361 registers via their memory regionBALATON Zoltan
Instead of relying on the mapped address of the MV64361 registers access them via their memory region. This is not a problem at reset time when these registers are mapped at the default address but the guest could change this later and then the RTAS calls accessing PCI config registers could fail. None of the guests actually do this so this only avoids a theoretical problem not seen in practice. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <b6f768023603dc2c4d130720bcecdbea459b7668.1634241019.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21ppc/pegasos2: Implement get-time-of-day RTAS function with VOFBALATON Zoltan
This is needed for Linux to access RTC time. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <6233eb07c680d6c74427e11b9641958f98d53378.1634241019.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21ppc/pegasos2: Warn when using VOF but no kernel is specifiedBALATON Zoltan
Issue a warning when using VOF (which is the default) but no -kernel option given to let users know that it will likely fail as the guest has nothing to run. It is not a hard error because it may still be useful to start the machine without further options for testing or inspecting it from monitor without actually booting it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <a4ec9a900df772b91e9f69ca7a0799d8ae293e5a.1634241019.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21ppc/pegasos2: Restrict memory to 2 gigabytesBALATON Zoltan
The CHRP spec this board confirms to only allows 2 GiB of system memory below 4 GiB as the high 2 GiB is allocated to IO and system resources. To avoid problems with memory overlapping these areas restrict RAM to 2 GiB similar to mac_newworld. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <54f58229a69c9c1cca21bcecad700b3d7052edd5.1634241019.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21hw/ppc: Fix iothread locking in the 405 codeThomas Huth
When using u-boot as firmware with the taihu board, QEMU aborts with this assertion: ERROR:../accel/tcg/tcg-accel-ops.c:79:tcg_handle_interrupt: assertion failed: (qemu_mutex_iothread_locked()) Running QEMU with "-d in_asm" shows that the crash happens when writing to SPR 0x3f2, so we are missing to lock the iothread in the code path here. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211006071140.565952-1-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21spapr/xive: Use xive_esb_rw() to trigger interruptsCédric Le Goater
xive_esb_rw() is the common routine used for memory accesses on ESB page. Use it for triggers also. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211006210546.641102-1-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21hw/ppc/spapr_softmmu: Reduce include listPhilippe Mathieu-Daudé
Commit 962104f0448 ("hw/ppc: moved hcalls that depend on softmmu") introduced a lot of unnecessary #include directives. Remove them. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211006170801.178023-1-philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21target/ppc: Fix the test raising the decrementer exceptionCédric Le Goater
Commit 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer") introduced new int64t variables and broke the test triggering the decrementer exception. Revert partially the change to evaluate both clause of the if statement. Reported-by: Coverity CID 1464061 Fixes: 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer") Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211005053324.441132-1-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21spapr/xive: Add source status helpersCédric Le Goater
and use them to set and test the ASSERTED bit of LSI sources. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211004212141.432954-1-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-20hw/elf_ops.h: switch to ssize_t for elf loader return typeLuc Michel
Until now, int was used as the return type for all the ELF loader related functions. The returned value is the sum of all loaded program headers "MemSize" fields. Because of the overflow check in elf_ops.h, trying to load an ELF bigger than INT_MAX will fail. Switch to ssize_t to remove this limitation. Signed-off-by: Luc Michel <lmichel@kalray.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20211014194325.19917-1-lmichel@kalray.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-20hw/arm/sbsa-ref: Fixed cpu type error message typo.Shuuichirou Ishii
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Message-Id: <20211008063604.670699-1-ishii.shuuichir@fujitsu.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-20hw/arm/virt: Don't create device-tree node for empty NUMA nodeGavin Shan
The empty NUMA node, where no memory resides, are allowed. For example, the following command line specifies two empty NUMA nodes. With this, QEMU fails to boot because of the conflicting device-tree node names, as the following error message indicates. /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ -accel kvm -machine virt,gic-version=host \ -cpu host -smp 4,sockets=2,cores=2,threads=1 \ -m 1024M,slots=16,maxmem=64G \ -object memory-backend-ram,id=mem0,size=512M \ -object memory-backend-ram,id=mem1,size=512M \ -numa node,nodeid=0,cpus=0-1,memdev=mem0 \ -numa node,nodeid=1,cpus=2-3,memdev=mem1 \ -numa node,nodeid=2 \ -numa node,nodeid=3 : qemu-system-aarch64: FDT: Failed to create subnode /memory@80000000: FDT_ERR_EXISTS As specified by linux device-tree binding document, the device-tree nodes for these empty NUMA nodes shouldn't be generated. However, the corresponding NUMA node IDs should be included in the distance map. The memory hotplug through device-tree on ARM64 isn't existing so far and it's not necessary to require the user to provide a distance map. Furthermore, the default distance map Linux generates may even be sufficient. So this simply skips populating the device-tree nodes for these empty NUMA nodes to avoid the error, so that QEMU can be started successfully. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-Id: <20211015124246.23073-1-gshan@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-20hw/arm/virt-acpi-build: IORT upgrade up to revision E.bEric Auger
Upgrade the IORT table from B to E.b specification revision (ARM DEN 0049E.b). The SMMUv3 and root complex node have additional fields. Also unique IORT node identifiers are introduced: they are generated in sequential order. They are not cross-referenced though. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20211014115643.756977-3-eric.auger@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-20q800: drop 8-bit graphic_depth check for Apple 21 inch displayMark Cave-Ayland
The graphic_depth check is no longer required since commit df8abbbadf ("macfb: add common monitor modes supported by the MacOS toolbox ROM") which introduced code in macfb_common_realize() to only allow the resolutions/depths provided in macfb_mode_table to be specified for each display type. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: df8abbbadf ("macfb: add common monitor modes supported by the MacOS toolbox ROM") Message-Id: <20211020141810.7875-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: add NMI handlerMark Cave-Ayland
This allows the programmer's switch to be triggered via the monitor for debugging purposes. Since the CPU level 7 interrupt is level-triggered, use a timer to hold the NMI active for 100ms before releasing it again. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewied-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: wire up remaining IRQs in classic modeMark Cave-Ayland
Explicitly wire up the remaining IRQs in classic mode to enable the use of g_assert_not_reached() in the default case to detect any unexpected IRQs. Add a comment explaining the IRQ routing differences in A/UX mode based upon the comments in NetBSD (also noting that at least A/UX 3.0.1 still uses classic mode). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic modeMark Cave-Ayland
When the hardware is operating in classic mode the SONIC on-board Ethernet IRQ is routed to nubus IRQ 9 instead of directly to the CPU at level 3. This does not affect the framebuffer which although it exists in slot 9, has its own dedicated IRQ on the Quadra 800 hardware. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: wire up auxmode GPIO to GLUEMark Cave-Ayland
This enables the GLUE logic to change its CPU level IRQ routing depending upon whether the hardware has been configured for A/UX mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20mac_via: add GPIO for A/UX modeMark Cave-Ayland
Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating whether the hardware is configured for A/UX mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQsMark Cave-Ayland
In order to allow dynamic routing of IRQs to different IRQ levels on the CPU depending upon port B bit 6, use GLUE IRQ numbers and map them to the the corresponding CPU IRQ level accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: move VIA1 IRQ from level 1 to level 6Mark Cave-Ayland
On a Quadra 800 machine Linux sets via_alt_mapping to 1 and clears port B bit 6 to ensure that the VIA1 IRQ is delivered at level 6 rather than level 1. Even though QEMU doesn't yet emulate this behaviour, Linux still installs the VIA1 level 1 IRQ handler regardless of the value of via_alt_mapping which is why the kernel has been able to boot until now. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20mac_via: update comment for VIA1B_vMystery bitMark Cave-Ayland
According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't particularly descriptive, the patch leaves this to ensure that the constants in mac_via.c remain in sync with Linux's mac_via.h. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20pci: fix PCI resource reserve capability on BEMichael S. Tsirkin
PCI resource reserve capability should use LE format as all other PCI things. If we don't then seabios won't boot: === PCI new allocation pass #1 === PCI: check devices PCI: QEMU resource reserve cap: size 10000000000000 type io PCI: secondary bus 1 size 10000000000000 type io PCI: secondary bus 1 size 00200000 type mem PCI: secondary bus 1 size 00200000 type prefmem === PCI new allocation pass #2 === PCI: out of I/O address space This became more important since we started reserving IO by default, previously no one noticed. Fixes: e2a6290aab ("hw/pcie-root-port: Fix hotplug for PCI devices requiring IO") Cc: marcel.apfelbaum@gmail.com Fixes: 226263fb5c ("hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port") Cc: zuban32s@gmail.com Fixes: 6755e618d0 ("hw/pci: add PCI resource reserve capability to legacy PCI bridge") Cc: jing2.liu@linux.intel.com Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-10-20vhost-vdpa: multiqueue supportJason Wang
This patch implements the multiqueue support for vhost-vdpa. This is done simply by reading the number of queue pairs from the config space and initialize the datapath and control path net client. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-11-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20virtio-net: vhost control virtqueue supportJason Wang
This patch implements the control virtqueue support for vhost. This requires virtio-net to figure out the datapath queue pairs and control virtqueue via is_datapath and pass the number of those two types of virtqueues to vhost_net_start()/vhost_net_stop(). Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-10-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20vhost: record the last virtqueue index for the virtio deviceJason Wang
This patch introduces a new field in the vhost_dev structure to record the last virtqueue index for the virtio device. This will be useful for the vhost backends with 1:N model to start or stop the device after all the vhost_dev structures were started or stopped. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-9-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20virtio-net: use "queue_pairs" instead of "queues" when possibleJason Wang
Most of the time, "queues" really means queue pairs. So this patch switch to use "queue_pairs" to avoid confusion. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-8-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20vhost-net: control virtqueue supportJason Wang
We assume there's no cvq in the past, this is not true when we need control virtqueue support for vhost-user backends. So this patch implements the control virtqueue support for vhost-net. As datapath, the control virtqueue is also required to be coupled with the NetClientState. The vhost_net_start/stop() are tweaked to accept the number of datapath queue pairs plus the the number of control virtqueue for us to start and stop the vhost device. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-7-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20vhost-vdpa: prepare for the multiqueue supportJason Wang
Unlike vhost-kernel, vhost-vdpa adapts a single device multiqueue model. So we need to simply use virtqueue index as the vhost virtqueue index. This is a must for multiqueue to work for vhost-vdpa. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-4-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 06:41:34 +0000