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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2020-06-23
hw/i2c/versatile_i2c: Add definitions for register addresses
Philippe Mathieu-Daudé
2020-06-23
hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
Philippe Mathieu-Daudé
2020-06-23
hw/arm/virt: Add 5.0 HW compat props
Andrew Jones
2020-06-22
hw/rx: Add RX GDB simulator
Yoshinori Sato
2020-06-22
hw/rx: Register R5F562N7 and R5F562N8 MCUs
Philippe Mathieu-Daudé
2020-06-22
hw/rx: Honor -accel qtest
Richard Henderson
2020-06-22
hw/rx: RX62N microcontroller (MCU)
Yoshinori Sato
2020-06-22
hw/char: RX62N serial communication interface (SCI)
Yoshinori Sato
2020-06-22
hw/timer: RX62N compare match timer (CMT)
Yoshinori Sato
2020-06-22
hw/timer: RX62N 8-Bit timer (TMR)
Yoshinori Sato
2020-06-22
hw/intc: RX62N interrupt controller (ICUa)
Yoshinori Sato
2020-06-22
hw/timer/sh_timer: Remove unused 'qemu/timer.h' include
Philippe Mathieu-Daudé
2020-06-22
hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h'
Philippe Mathieu-Daudé
2020-06-22
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...
Peter Maydell
2020-06-19
Merge remote-tracking branch 'remotes/kraxel/tags/audio-20200619-pull-request...
Peter Maydell
2020-06-19
hw/riscv: sifive_u: Add a dummy DDR memory controller device
Bin Meng
2020-06-19
hw/riscv: sifive_u: Sort the SoC memmap table entries
Bin Meng
2020-06-19
hw/riscv: sifive_u: Support different boot source per MSEL pin state
Bin Meng
2020-06-19
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Bin Meng
2020-06-19
hw/riscv: sifive_u: Add a new property msel for MSEL pin state
Bin Meng
2020-06-19
hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
Bin Meng
2020-06-19
hw/riscv: sifive_u: Add reset functionality
Bin Meng
2020-06-19
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
Bin Meng
2020-06-19
hw/riscv: sifive_u: Hook a GPIO controller
Bin Meng
2020-06-19
hw/riscv: sifive_gpio: Add a new 'ngpio' property
Bin Meng
2020-06-19
hw/riscv: sifive_gpio: Clean up the codes
Bin Meng
2020-06-19
hw/riscv: sifive_u: Generate device tree node for OTP
Bin Meng
2020-06-19
hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
Bin Meng
2020-06-19
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
Bin Meng
2020-06-19
hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
Bin Meng
2020-06-19
riscv/opentitan: Connect the UART device
Alistair Francis
2020-06-19
riscv/opentitan: Connect the PLIC device
Alistair Francis
2020-06-19
hw/intc: Initial commit of lowRISC Ibex PLIC
Alistair Francis
2020-06-19
hw/char: Initial commit of Ibex UART
Alistair Francis
2020-06-19
riscv/opentitan: Fix the ROM size
Alistair Francis
2020-06-19
sifive_e: Support the revB machine
Alistair Francis
2020-06-19
tpm: Move backend code under the 'backends/' directory
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Make 'tpm_util.h' publicly accessible as "sysemu/tpm_util.h"
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Move DEFINE_PROP_TPMBE() macro to 'tmp_prop.h' local header
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Move few declarations from 'tpm_util.h' to 'tpm_int.h'
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Make TRACE_TPM_UTIL_SHOW_BUFFER check local to tpm_util.c
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Remove unnecessary 'tpm_int.h' header inclusion
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Move 'hw/acpi/tpm.h' inclusion from header to sources
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Include missing 'qemu/option.h' header
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Do not include 'qemu/osdep.h' in header
Philippe Mathieu-Daudé
2020-06-19
hw/tpm: Rename TPMDEV as TPM_BACKEND in Kconfig
Philippe Mathieu-Daudé
2020-06-19
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into staging
Peter Maydell
2020-06-19
hw/audio/gus: Fix registers 32-bit access
Allan Peramaki
2020-06-18
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into st...
Peter Maydell
2020-06-18
hw/net/e1000e: Do not abort() on invalid PSRCTL register value
Philippe Mathieu-Daudé
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