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2019-12-17xive: Link "xive" property to XiveEndSource::xrtr pointerGreg Kurz
The END source object has both a pointer and a "xive" property pointing to the router object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157383333784.165747.5298512574054268786.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17xive: Link "xive" property to XiveSource::xive pointerGreg Kurz
The source object has both a pointer and a "xive" property pointing to the notifier object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157383333227.165747.12901571295951957951.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17xive: Link "cpu" property to XiveTCTX::cs pointerGreg Kurz
The TCTX object has both a pointer and a "cpu" property pointing to the vCPU object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157383332669.165747.2484056603605646820.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Drop "chip" link from POWER9 PSI objectGreg Kurz
It has no apparent user. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157383383118.166856.2588933416368211047.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Add a "/qemu" device tree nodeCédric Le Goater
It helps skiboot identifying that is running on a QEMU platform. The compatible string will define the POWERPC processor version. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191106142129.4908-1-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Add a PNOR modelCédric Le Goater
On a POWERPC PowerNV system, the host firmware is stored in a PNOR flash chip which contents is mapped on the LPC bus. This model adds a simple dummy device to map the contents of a block device in the host address space. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191021131215.3693-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-16Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' ↵Peter Maydell
into staging MIPS queue for December 16th, 2019 # gpg: Signature made Mon 16 Dec 2019 12:29:24 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-dec-16-2019: MAINTAINERS: Add a file to MIPS section MAINTAINERS: Add three files to Malta section MAINTAINERS: Adjust maintainership for Malta board MAINTAINERS: Adjust maintainership for Fulong 2E board MAINTAINERS: Add a section on UI translation hw/mips: Deprecate the r4k machine mips: fulong 2e: Renovate coding style mips: r4000: Renovate coding style mips: mipssim: Renovate coding style mips: malta: Renovate coding style mips: jazz: Renovate coding style Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20191216-1' into staging target-arm queue: * Add support for Cortex-M7 CPU * exynos4210_gic: Suppress gcc9 format-truncation warnings * aspeed: Various minor bug fixes and improvements * aspeed: Add support for the tacoma-bmc board * Honour HCR_EL32.TID1 and .TID2 trapping requirements * Handle trapping to EL2 of AArch32 VMRS instructions * Handle AArch32 CP15 trapping via HSTR_EL2 * Add support for missing Jazelle system registers * arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on * Add support for DC CVAP & DC CVADP instructions * Fix assertion when SCR.NS is changed in Secure-SVC &c * enable SHPC native hot plug in arm ACPI # gpg: Signature made Mon 16 Dec 2019 11:08:07 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20191216-1: (34 commits) target/arm: ensure we use current exception state after SCR update hw/arm/virt: Simplify by moving the gic in the machine state hw/arm/acpi: enable SHPC native hot plug hw/arm/acpi: simplify AML bit and/or statement hw/arm/sbsa-ref: Simplify by moving the gic in the machine state target/arm: Add support for DC CVAP & DC CVADP ins migration: ram: Switch to ram block writeback Memory: Enable writeback for given memory region tcg: cputlb: Add probe_read arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() target/arm: Add support for missing Jazelle system registers target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 target/arm: Handle trapping to EL2 of AArch32 VMRS instructions target/arm: Honor HCR_EL2.TID1 trapping requirements target/arm: Honor HCR_EL2.TID2 trapping requirements aspeed: Change the "nic" property definition aspeed: Change the "scu" property definition gpio: fix memory leak in aspeed_gpio_init() aspeed: Add support for the tacoma-bmc board aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16hw/mips: Deprecate the r4k machinePhilippe Mathieu-Daudé
The r4k machine was introduced in 2005 (6af0bf9c7) and its last logical change was in 2005 (9542611a6). After that, one can count 164 maintenance commits (QEMU API changes) with the exception of 1 fix in 2015 (memory leak, commit 3ad9fd5a). This machine was introduced as a proof of concept to run a MIPS CPU. Two years later, the Malta machine was added (commit 5856de80), modeling a real platform. Note also this machine has no specification except 5 lines in the header of this file: * emulates a simple machine with ISA-like bus. * ISA IO space mapped to the 0x14000000 (PHYS) and * ISA memory at the 0x10000000 (PHYS, 16Mb in size). * All peripherial devices are attached to this "bus" with * the standard PC ISA addresses. The Linux kernel support for this machine has been dropped more than 10 years ago in commit 302922e5. It is time to deprecate this obsolete machine. Users are recommended to use the Malta board, and its hardware is well documented. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20191125104103.28962-1-philmd@redhat.com>
2019-12-16mips: fulong 2e: Renovate coding styleFilip Bozuta
The script checkpatch.pl located in scripts folder was used to detect all errors and warrnings in files: hw/mips/mips_fulong2e.c hw/isa/vt82c686.c hw/pci-host/bonito.c include/hw/isa/vt82c686.h These mips Fulong 2E machine files were edited and all the errors and warrings generated by the checkpatch.pl script were corrected and then the script was ran again to make sure there are no more errors and warnings. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1575640687-20744-6-git-send-email-Filip.Bozuta@rt-rk.com>
2019-12-16mips: r4000: Renovate coding styleFilip Bozuta
The script checkpatch.pl located in scripts folder was used to detect all errors and warrnings in file: hw/mips/mips_r4k.c This mips r4000 machine file was edited and all the errors and warrings generated by the checkpatch.pl script were corrected and then the script was ran again to make sure there are no more errors and warnings. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1575640687-20744-5-git-send-email-Filip.Bozuta@rt-rk.com>
2019-12-16mips: mipssim: Renovate coding styleFilip Bozuta
The script checkpatch.pl located in scripts folder was used to detect all errors and warrnings in files: hw/mips/mips_mipssim.c hw/net/mipsnet.c All these mips mipssim machine files were edited and all the errors and warrings generated by the checkpatch.pl script were corrected and then the script was ran again to make sure there are no more errors and warnings. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1575640687-20744-4-git-send-email-Filip.Bozuta@rt-rk.com>
2019-12-16mips: malta: Renovate coding styleFilip Bozuta
The script checkpatch.pl located in scripts folder was used to detect all errors and warrnings in files: hw/mips/mips_malta.c hw/mips/gt64xxx_pci.c tests/acceptance/linux_ssh_mips_malta.py All these mips malta machine files were edited and all the errors and warrings generated by the checkpatch.pl script were corrected and then the script was ran again to make sure there are no more errors and warnings. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1575640687-20744-3-git-send-email-Filip.Bozuta@rt-rk.com>
2019-12-16mips: jazz: Renovate coding styleFilip Bozuta
The script checkpatch.pl located in scripts folder was used to detect all errors and warrnings in files: hw/mips/mips_jazz.c hw/display/jazz_led.c hw/dma/rc4030.c All these mips jazz machine files were edited and all the errors and warrings generated by the checkpatch.pl script were corrected and then the script was ran again to make sure there are no more errors and warnings. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1575640687-20744-2-git-send-email-Filip.Bozuta@rt-rk.com>
2019-12-16hw/arm/virt: Simplify by moving the gic in the machine statePhilippe Mathieu-Daudé
Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20191209090306.20433-1-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16hw/arm/acpi: enable SHPC native hot plugHeyi Guo
After the introduction of generic PCIe root port and PCIe-PCI bridge, we will also have SHPC controller on ARM, so just enable SHPC native hot plug. Also update tests/data/acpi/virt/DSDT* to pass "make check". Cc: Shannon Zhao <shannon.zhaosl@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Heyi Guo <guoheyi@huawei.com> Message-id: 20191209063719.23086-3-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16hw/arm/acpi: simplify AML bit and/or statementHeyi Guo
The last argument of AML bit and/or statement is the target variable, so we don't need to use a NULL target and then an additional store operation; using just aml_and() or aml_or() statement is enough. Also update tests/data/acpi/virt/DSDT* to pass "make check". Cc: Shannon Zhao <shannon.zhaosl@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Suggested-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Heyi Guo <guoheyi@huawei.com> Message-id: 20191209063719.23086-2-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16hw/arm/sbsa-ref: Simplify by moving the gic in the machine statePhilippe Mathieu-Daudé
Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20191206162303.30338-1-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Change the "nic" property definitionCédric Le Goater
The Aspeed MII model has a link pointing to its associated FTGMAC100 NIC in the machine. Change the "nic" property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-18-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Change the "scu" property definitionCédric Le Goater
The Aspeed Watchdog and Timer models have a link pointing to the SCU controller model of the machine. Change the "scu" property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-17-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16gpio: fix memory leak in aspeed_gpio_init()PanNengyuan
Address Sanitizer shows memory leak in hw/gpio/aspeed_gpio.c:875 Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: PanNengyuan <pannengyuan@huawei.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-16-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Add support for the tacoma-bmc boardCédric Le Goater
The Tacoma BMC board is replacement board for the BMC of the OpenPOWER Witherspoon system. It uses a AST2600 SoC instead of a AST2500 and the I2C layout is the same as it controls the same main board. Used for HW bringup. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-15-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Remove AspeedBoardConfig array and use AspeedMachineClassCédric Le Goater
AspeedBoardConfig is a redundant way to define class attributes and it complexifies the machine definition and initialization. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-14-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/smc: Add AST2600 timings registersCédric Le Goater
Each CS has its own Read Timing Compensation Register on newer SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-13-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/smc: Do not map disabled segment on the AST2600Cédric Le Goater
The segments can be disabled on the AST2600 (zero register value). CS0 is open by default but not the other CS. This is closing the access to the flash device in user mode and forbids scanning. In the model, check the segment size and disable the associated region when the value is zero. Fixes: bcaa8ddd081c ("aspeed/smc: Add AST2600 support") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-12-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/smc: Restore default AHB window mapping at resetCédric Le Goater
The current model only restores the Segment Register values but leaves the previous CS mapping behind. Introduce a helper setting the register value and mapping the region at the requested address. Use this helper when a Segment register is set and at reset. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-11-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16watchdog/aspeed: Fix AST2600 frequency behaviourJoel Stanley
The AST2600 control register sneakily changed the meaning of bit 4 without anyone noticing. It no longer controls the 1MHz vs APB clock select, and instead always runs at 1MHz. The AST2500 was always 1MHz too, but it retained bit 4, making it read only. We can model both using the same fixed 1MHz calculation. Fixes: 6b2b2a703cad ("hw: wdt_aspeed: Add AST2600 support") Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-10-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16watchdog/aspeed: Improve watchdog timeout messageJoel Stanley
Users benefit from knowing which watchdog timer has expired. The address of the watchdog's registers unambiguously indicates which has expired, so log that. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-9-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/scu: Fix W1C behaviorJoel Stanley
This models the clock write one to clear registers, and fixes up some incorrect behavior in all of the write to clear registers. There was also a typo in one of the register definitions. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-8-clg@kaod.org [clg: checkpatch.pl fixes ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/sdmc: Make ast2600 default 1GJoel Stanley
Most boards have this much. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-7-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/i2c: Add trace eventsCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-6-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/i2c: Add support for DMA transfersCédric Le Goater
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA transfers to and from DRAM. A pair of registers defines the buffer address and the length of the DMA transfer. The address should be aligned on 4 bytes and the maximum length should not exceed 4K. The receive or transmit DMA transfer can then be initiated with specific bits in the Command/Status register of the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Add a DRAM memory region at the SoC levelCédric Le Goater
Currently, we link the DRAM memory region to the FMC model (for DMAs) through a property alias at the SoC level. The I2C model will need a similar region for DMA support, add a DRAM region property at the SoC level for both model to use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/i2c: Check SRAM enablement on AST2500Cédric Le Goater
The SRAM must be enabled before using the Buffer Pool mode or the DMA mode. This is not required on other SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/i2c: Add support for pool buffer transfersCédric Le Goater
The Aspeed I2C controller can operate in different transfer modes : - Byte Buffer mode, using a dedicated register to transfer a byte. This is what the model supports today. - Pool Buffer mode, using an internal SRAM to transfer multiple bytes in the same command sequence. Each SoC has different SRAM characteristics. On the AST2400, 2048 bytes of SRAM are available at offset 0x800 of the controller AHB window. The pool buffer can be configured from 1 to 256 bytes per bus. On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of 16 bytes per bus. On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of 32 bytes per bus. It can be splitted in two for TX and RX but the current model does not add support for it as it it unused by known drivers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16exynos4210_gic: Suppress gcc9 format-truncation warningsDavid Gibson
exynos4210_gic_realize() prints the number of cpus into some temporary buffers, but it only allows 3 bytes space for it. That's plenty: existing machines will only ever set this value to EXYNOS4210_NCPUS (2). But the compiler can't always figure that out, so some[*] gcc9 versions emit -Wformat-truncation warnings. We can fix that by hinting the constraint to the compiler with a suitably placed assert(). [*] The bizarre thing here, is that I've long gotten these warnings compiling in a 32-bit x86 container as host - Fedora 30 with gcc-9.2.1-1.fc30.i686 - but it compiles just fine on my normal x86_64 host - Fedora 30 with and gcc-9.2.1-1.fc30.x86_64. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: deleted stray blank line] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-14s390x/event-facility: Fix realize() error API violationsMarkus Armbruster
sclp_events_bus_realize() dereferences @errp when object_property_set_bool() fails. That's wrong; see the big comment in error.h. Introduced in commit f6102c329c "s390/sclp: rework sclp event facility initialization + device realization". No caller actually passes null. Fix anyway: splice in a local Error *err, and error_propagate(). Cc: David Hildenbrand <david@redhat.com> Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20191204093625.14836-12-armbru@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-14s390x: Don't do a normal reset on the initial cpuJanosch Frank
The initiating cpu needs to be reset with an initial reset. While doing a normal reset followed by a initial reset is not wrong per se, the Ultravisor will only allow the correct reset to be performed. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20191127175046.4911-2-frankja@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-14hw: add compat machines for 5.0Cornelia Huck
Add 5.0 machine types for arm/i440fx/q35/s390x/spapr. For i440fx and q35, unversioned cpu models are still translated to -v1; I'll leave changing this (if desired) to the respective maintainers. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20191112104811.30323-1-cohuck@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
2019-12-14vfio-ccw: Fix error messageBoris Fiuczynski
Signed-off-by: Boris Fiuczynski <fiuczy@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20191128143015.5231-1-fiuczy@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-13Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Pull request # gpg: Signature made Fri 13 Dec 2019 14:32:11 GMT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: iothread: document -object iothread on man page virtio-blk: advertise F_WCE (F_FLUSH) if F_CONFIG_WCE is advertised Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-13virtio-blk: advertise F_WCE (F_FLUSH) if F_CONFIG_WCE is advertisedEvgeny Yakovlev
Virtio spec 1.1 (and earlier), 5.2.5.2 Driver Requirements: Device Initialization: "Devices SHOULD always offer VIRTIO_BLK_F_FLUSH, and MUST offer it if they offer VIRTIO_BLK_F_CONFIG_WCE" Currently F_CONFIG_WCE and F_WCE are not connected to each other. Qemu will advertise F_CONFIG_WCE if config-wce argument is set for virtio-blk device. And F_WCE is advertised only if underlying block backend actually has it's caching enabled. Fix this by advertising F_WCE if F_CONFIG_WCE is also advertised. To preserve backwards compatibility with newer machine types make this behaviour governed by "x-enable-wce-if-config-wce" virtio-blk-device property and introduce hw_compat_4_2 with new property being off by default for all machine types <= 4.2 (but don't introduce 4.3 machine type itself yet). Signed-off-by: Evgeny Yakovlev <wrfsh@yandex-team.ru> Message-Id: <1572978137-189218-1-git-send-email-wrfsh@yandex-team.ru> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-12-13virtio-fs: fix MSI-X nvectors calculationStefan Hajnoczi
The following MSI-X vectors are required: * VIRTIO Configuration Change * hiprio virtqueue * requests virtqueues Fix the calculation to reserve enough MSI-X vectors. Otherwise guest drivers fall back to a sub-optional configuration where all virtqueues share a single vector. This change does not break live migration compatibility since vhost-user-fs-pci devices are not migratable yet. Reported-by: Vivek Goyal <vgoyal@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20191209110759.35227-1-stefanha@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-12-13vhost-user-fs: remove "vhostfd" propertyMarc-André Lureau
The property doesn't make much sense for a vhost-user device. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20191116112016.14872-1-marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-12-02net/virtio: Fix failover error handling crash bugsMarkus Armbruster
Functions that take an Error ** parameter to pass an error to the caller expect the parameter to point to null. failover_replug_primary() violates this precondition in several places: * After qemu_opts_from_qdict() failed, *errp is no longer null. Passing it to error_setg() is wrong, and will trip the assertion in error_setv(). Messed up in commit 150ab54aa6 "net/virtio: fix re-plugging of primary device". Simply drop the error_setg(). * Passing @errp to qemu_opt_set_bool(), hotplug_handler_pre_plug(), and hotplug_handler_plug() is wrong. If one of the first two fails, *errp is no longer null. Risks tripping the same assertion. Moreover, continuing after such errors is unsafe. Messed up in commit 9711cd0dfc "net/virtio: add failover support". Fix by handling each error properly. failover_replug_primary() crashes when passed a null @errp. Also messed up in commit 9711cd0dfc. This bug can't bite as no caller actually passes null. Fix it anyway. Fixes: 9711cd0dfc3fa414f7f64935713c07134ae67971 Fixes: 150ab54aa6934583180f88a2bd540bc6fc4fbff3 Cc: Jens Freimann <jfreimann@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20191130194240.10517-3-armbru@redhat.com> Reviewed-by: Jens Freimann <jfreimann@redhat.com>
2019-12-02net/virtio: Drop useless n->primary_dev not null checksMarkus Armbruster
virtio_net_handle_migration_primary() returns early when it can't ensure n->primary_dev is non-null. Checking it again right after that early return is redundant. Drop. If n->primary_dev is null on entering failover_replug_primary(), @pdev will become null, and pdev->partially_hotplugged will crash. Checking n->primary_dev later is useless. It can't actually be null, because its caller virtio_net_handle_migration_primary() ensures it isn't. Drop the useless check. Cc: Jens Freimann <jfreimann@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20191130194240.10517-2-armbru@redhat.com> Reviewed-by: Jens Freimann <jfreimann@redhat.com>
2019-11-26Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20191126' into staging target-arm queue: * handle FTYPE flag correctly in v7M exception return for v7M CPUs with an FPU (v8M CPUs were already correct) * versal: Add the CRP as unimplemented * Fix ISR_EL1 tracking when executing at EL2 * Honor HCR_EL2.TID3 trapping requirements # gpg: Signature made Tue 26 Nov 2019 14:11:50 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20191126: target/arm: Honor HCR_EL2.TID3 trapping requirements target/arm: Fix ISR_EL1 tracking when executing at EL2 hw/arm: versal: Add the CRP as unimplemented target/arm: Fix handling of cortex-m FTYPE flag in EXCRET Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-11-26Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191126' ↵Peter Maydell
into staging ppc patch queue for 2019-11-26 Here's the first 4.2 hard freeze pull request from me. This has: * A fix for some testcases that cause errors on older host kernels (e.g. RHEL7), with our new default configuration of VSMT mode * Changes to make VFIO devices interact properly with change of irq chip caused by PAPR feature negotiation. This is more involved than I would like, but it's a problem in real use cases and I can't see an easier way to handle it. * Fix an error with ms6522 counters for the g3beige machine * Fix a coverity warning # gpg: Signature made Tue 26 Nov 2019 05:52:16 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.2-20191126: ppc/spapr_events: fix potential NULL pointer dereference in rtas_event_log_dequeue mos6522: update counters when timer interrupts are off spapr: Work around spurious warnings from vfio INTx initialization spapr: Handle irq backend changes with VFIO PCI devices vfio/pci: Respond to KVM irqchip change notifier vfio/pci: Split vfio_intx_update() kvm: Introduce KVM irqchip change notifier pseries: fix migration-test and pxe-test Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-11-26hw/arm: versal: Add the CRP as unimplementedEdgar E. Iglesias
Add the CRP as unimplemented thus avoiding bus errors when guests access these registers. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-11-26Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' ↵Peter Maydell
into staging RISC-V Patches for 4.2-rc3 This tag contains two patches that I'd like to target for 4.2-rc3: * A fix to the DT entry for the SiFive test finisher. * A fix to the spike board's HTIF interface. This passes "make check" and boots OE for me. # gpg: Signature made Mon 25 Nov 2019 20:51:13 GMT # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.2-rc3: hw/riscv: Add optional symbol callback ptr to riscv_load_kernel() RISC-V: virt: This is a "sifive,test1" test finisher Signed-off-by: Peter Maydell <peter.maydell@linaro.org>